summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/reset
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
commitebde8820a04dd73a09f50ba84b8cf8ec3773d6ba (patch)
tree031d15dcd26f5b737adddc5042a3ddabbb6051f7 /dts/Bindings/reset
parent15af9fc8cc9e18409893d2375271d64cac76924a (diff)
downloadbarebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.gz
barebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.xz
dts: update to v4.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/reset')
-rw-r--r--dts/Bindings/reset/lantiq,reset.txt30
-rw-r--r--dts/Bindings/reset/nxp,lpc1850-rgu.txt1
-rw-r--r--dts/Bindings/reset/renesas,rst.txt1
-rw-r--r--dts/Bindings/reset/uniphier-reset.txt27
4 files changed, 56 insertions, 3 deletions
diff --git a/dts/Bindings/reset/lantiq,reset.txt b/dts/Bindings/reset/lantiq,reset.txt
new file mode 100644
index 000000000..c6aef36b7
--- /dev/null
+++ b/dts/Bindings/reset/lantiq,reset.txt
@@ -0,0 +1,30 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+This node has to be a sub node of the Lantiq RCU block.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,danube-reset"
+ "lantiq,xrx200-reset"
+- reg : Defines the following sets of registers in the parent
+ syscon device
+ - Offset of the reset set register
+ - Offset of the reset status register
+- #reset-cells : Specifies the number of cells needed to encode the
+ reset line, should be 2.
+ The first cell takes the reset set bit and the
+ second cell takes the status bit.
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+ reset0: reset-controller@10 {
+ compatible = "lantiq,xrx200-reset";
+ reg <0x10 0x04>, <0x14 0x04>;
+
+ #reset-cells = <2>;
+ };
diff --git a/dts/Bindings/reset/nxp,lpc1850-rgu.txt b/dts/Bindings/reset/nxp,lpc1850-rgu.txt
index b4e96a278..05d5be48d 100644
--- a/dts/Bindings/reset/nxp,lpc1850-rgu.txt
+++ b/dts/Bindings/reset/nxp,lpc1850-rgu.txt
@@ -80,5 +80,4 @@ mac: ethernet@40010000 {
clock-names = "stmmaceth";
resets = <&rgu 22>;
reset-names = "stmmaceth";
- status = "disabled";
};
diff --git a/dts/Bindings/reset/renesas,rst.txt b/dts/Bindings/reset/renesas,rst.txt
index fe5e0f37b..e5a03ffe0 100644
--- a/dts/Bindings/reset/renesas,rst.txt
+++ b/dts/Bindings/reset/renesas,rst.txt
@@ -26,6 +26,7 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
+ - "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.
diff --git a/dts/Bindings/reset/uniphier-reset.txt b/dts/Bindings/reset/uniphier-reset.txt
index 83ab0f599..68a6f487c 100644
--- a/dts/Bindings/reset/uniphier-reset.txt
+++ b/dts/Bindings/reset/uniphier-reset.txt
@@ -6,7 +6,6 @@ System reset
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-reset" - for sLD3 SoC
"socionext,uniphier-ld4-reset" - for LD4 SoC
"socionext,uniphier-pro4-reset" - for Pro4 SoC
"socionext,uniphier-sld8-reset" - for sLD8 SoC
@@ -37,7 +36,6 @@ Media I/O (MIO) reset, SD reset
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
@@ -92,3 +90,28 @@ Example:
other nodes ...
};
+
+
+Analog signal amplifier reset
+-----------------------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
+ "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
+- #reset-cells: should be 1.
+
+Example:
+
+ adamv@57920000 {
+ compatible = "socionext,uniphier-ld11-adamv",
+ "simple-mfd", "syscon";
+ reg = <0x57920000 0x1000>;
+
+ adamv_rst: reset {
+ compatible = "socionext,uniphier-ld11-adamv-reset";
+ #reset-cells = <1>;
+ };
+
+ other nodes ...
+ };