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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-09 14:49:17 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-17 09:37:13 +0100 |
commit | f826d85b7ab0924d5bf1a5458c49e7f7d8207a23 (patch) | |
tree | dd6354e00da0aa143d1db6164e1a455dddb9b892 /dts/Bindings/riscv | |
parent | 0e37f94fbe1bd189f35b3e1718549ec2f4a710ee (diff) | |
download | barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.gz barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.xz |
dts: update to v5.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/riscv')
-rw-r--r-- | dts/Bindings/riscv/canaan.yaml | 47 | ||||
-rw-r--r-- | dts/Bindings/riscv/cpus.yaml | 8 | ||||
-rw-r--r-- | dts/Bindings/riscv/sifive-l2-cache.yaml | 35 | ||||
-rw-r--r-- | dts/Bindings/riscv/sifive.yaml | 17 |
4 files changed, 98 insertions, 9 deletions
diff --git a/dts/Bindings/riscv/canaan.yaml b/dts/Bindings/riscv/canaan.yaml new file mode 100644 index 0000000000..f8f3f286bd --- /dev/null +++ b/dts/Bindings/riscv/canaan.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/canaan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan SoC-based boards + +maintainers: + - Damien Le Moal <damien.lemoal@wdc.com> + +description: + Canaan Kendryte K210 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sipeed,maix-bit + - const: sipeed,maix-bitm + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-go + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-dock-m1 + - const: sipeed,maix-dock-m1w + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maixduino + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-kd233 + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-k210 + +additionalProperties: true + +... diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml index c6925e0b16..e534f6a7cf 100644 --- a/dts/Bindings/riscv/cpus.yaml +++ b/dts/Bindings/riscv/cpus.yaml @@ -28,11 +28,18 @@ properties: - items: - enum: - sifive,rocket0 + - sifive,bullet0 - sifive,e5 + - sifive,e7 - sifive,e51 + - sifive,e71 - sifive,u54-mc + - sifive,u74-mc - sifive,u54 + - sifive,u74 - sifive,u5 + - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -50,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: diff --git a/dts/Bindings/riscv/sifive-l2-cache.yaml b/dts/Bindings/riscv/sifive-l2-cache.yaml index efc0198eeb..23b2276143 100644 --- a/dts/Bindings/riscv/sifive-l2-cache.yaml +++ b/dts/Bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -52,10 +55,13 @@ properties: cache-unified: true interrupts: - description: | - Must contain entries for DirError, DataError and DataFail signals. minItems: 3 - maxItems: 3 + maxItems: 4 + items: + - description: DirError interrupt + - description: DataError interrupt + - description: DataFail interrupt + - description: DirFail interrupt reg: maxItems: 1 @@ -63,10 +69,31 @@ properties: next-level-cache: true memory-region: + maxItems: 1 description: | The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: + compatible: + contains: + const: sifive,fu540-c000-ccache + +then: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + +else: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError, DataFail, DirFail signals. + minItems: 4 + additionalProperties: false required: diff --git a/dts/Bindings/riscv/sifive.yaml b/dts/Bindings/riscv/sifive.yaml index 3a8647d1da..ee0a239af4 100644 --- a/dts/Bindings/riscv/sifive.yaml +++ b/dts/Bindings/riscv/sifive.yaml @@ -17,11 +17,18 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - sifive,hifive-unleashed-a00 - - const: sifive,fu540-c000 - - const: sifive,fu540 + oneOf: + - items: + - enum: + - sifive,hifive-unleashed-a00 + - const: sifive,fu540-c000 + - const: sifive,fu540 + + - items: + - enum: + - sifive,hifive-unmatched-a00 + - const: sifive,fu740-c000 + - const: sifive,fu740 additionalProperties: true |