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authorSascha Hauer <s.hauer@pengutronix.de>2018-05-08 08:14:56 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-05-08 08:14:56 +0200
commit6b85c20d46812bdbc062b863261c3e5100e30556 (patch)
treee067c9889eaf55d5e793b05a14000276f2669e9f /dts/Bindings/rng/omap_rng.txt
parent9d8c00bdf7c1e8b614a797f0a15fa45bf6387224 (diff)
downloadbarebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.gz
barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.xz
dts: update to v4.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/rng/omap_rng.txt')
-rw-r--r--dts/Bindings/rng/omap_rng.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/dts/Bindings/rng/omap_rng.txt b/dts/Bindings/rng/omap_rng.txt
index 9cf7876ab4..ea434ce50f 100644
--- a/dts/Bindings/rng/omap_rng.txt
+++ b/dts/Bindings/rng/omap_rng.txt
@@ -13,7 +13,12 @@ Required properties:
- interrupts : the interrupt number for the RNG module.
Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
- clocks: the trng clock source. Only mandatory for the
- "inside-secure,safexcel-eip76" compatible.
+ "inside-secure,safexcel-eip76" compatible, the second clock is
+ needed for the Armada 7K/8K SoCs
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for the second
+ one
+
Example:
/* AM335x */