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authorSascha Hauer <s.hauer@pengutronix.de>2015-02-09 08:45:25 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-02-11 09:50:08 +0100
commitab001302c8e1718110bb8839c270d2caa817b214 (patch)
treef5ab4feb5242e548917c3536b8510080df9a4e8f /dts/Bindings/rtc
parentc937ef5d34ede89ae382cfe6d98ba366859a65af (diff)
downloadbarebox-ab001302c8e1718110bb8839c270d2caa817b214.tar.gz
barebox-ab001302c8e1718110bb8839c270d2caa817b214.tar.xz
dts: update to v3.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/rtc')
-rw-r--r--dts/Bindings/rtc/atmel,at91sam9-rtc.txt23
-rw-r--r--dts/Bindings/rtc/rtc-omap.txt9
-rw-r--r--dts/Bindings/rtc/rtc-opal.txt16
3 files changed, 47 insertions, 1 deletions
diff --git a/dts/Bindings/rtc/atmel,at91sam9-rtc.txt b/dts/Bindings/rtc/atmel,at91sam9-rtc.txt
new file mode 100644
index 000000000..6ae79d184
--- /dev/null
+++ b/dts/Bindings/rtc/atmel,at91sam9-rtc.txt
@@ -0,0 +1,23 @@
+Atmel AT91SAM9260 Real Time Timer
+
+Required properties:
+- compatible: should be: "atmel,at91sam9260-rtt"
+- reg: should encode the memory region of the RTT controller
+- interrupts: rtt alarm/event interrupt
+- clocks: should contain the 32 KHz slow clk that will drive the RTT block.
+- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store
+ the time base when the RTT is used as an RTC.
+ The first cell should point to the GPBR node and the second one
+ encode the offset within the GPBR block (or in other words, the
+ GPBR register used to store the time base).
+
+
+Example:
+
+rtt@fffffd20 {
+ compatible = "atmel,at91sam9260-rtt";
+ reg = <0xfffffd20 0x10>;
+ interrupts = <1 4 7>;
+ clocks = <&clk32k>;
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+};
diff --git a/dts/Bindings/rtc/rtc-omap.txt b/dts/Bindings/rtc/rtc-omap.txt
index 5a0f02d34..4ba4dbd34 100644
--- a/dts/Bindings/rtc/rtc-omap.txt
+++ b/dts/Bindings/rtc/rtc-omap.txt
@@ -5,11 +5,17 @@ Required properties:
- "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
- "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
This RTC IP has special WAKE-EN Register to enable
- Wakeup generation for event Alarm.
+ Wakeup generation for event Alarm. It can also be
+ used to control an external PMIC via the
+ pmic_power_en pin.
- reg: Address range of rtc register set
- interrupts: rtc timer, alarm interrupts in order
- interrupt-parent: phandle for the interrupt controller
+Optional properties:
+- system-power-controller: whether the rtc is controlling the system power
+ through pmic_power_en
+
Example:
rtc@1c23000 {
@@ -18,4 +24,5 @@ rtc@1c23000 {
interrupts = <19
19>;
interrupt-parent = <&intc>;
+ system-power-controller;
};
diff --git a/dts/Bindings/rtc/rtc-opal.txt b/dts/Bindings/rtc/rtc-opal.txt
new file mode 100644
index 000000000..af87e5eca
--- /dev/null
+++ b/dts/Bindings/rtc/rtc-opal.txt
@@ -0,0 +1,16 @@
+IBM OPAL real-time clock
+------------------------
+
+Required properties:
+- comapatible: Should be "ibm,opal-rtc"
+
+Optional properties:
+- has-tpo: Decides if the wakeup is supported or not.
+
+Example:
+ rtc {
+ compatible = "ibm,opal-rtc";
+ has-tpo;
+ phandle = <0x10000029>;
+ linux,phandle = <0x10000029>;
+ };