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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 08:26:30 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 17:23:13 +0200 |
commit | 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch) | |
tree | dd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/Bindings/serial/xlnx,opb-uartlite.txt | |
parent | 625eea2765d94aee016cf25d9cabecde8eae0775 (diff) | |
download | barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.xz |
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/serial/xlnx,opb-uartlite.txt')
-rw-r--r-- | dts/Bindings/serial/xlnx,opb-uartlite.txt | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.txt b/dts/Bindings/serial/xlnx,opb-uartlite.txt new file mode 100644 index 0000000000..c37deb44de --- /dev/null +++ b/dts/Bindings/serial/xlnx,opb-uartlite.txt @@ -0,0 +1,23 @@ +Xilinx Axi Uartlite controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Can be either of + "xlnx,xps-uartlite-1.00.a" + "xlnx,opb-uartlite-1.00.b" +- reg : Physical base address and size of the Axi Uartlite + registers map. +- interrupts : Should contain the UART controller interrupt. + +Optional properties: +- port-number : Set Uart port number +- clock-names : Should be "s_axi_aclk" +- clocks : Input clock specifier. Refer to common clock bindings. + +Example: +serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x0 0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; +}; |