dts: update to v5.16-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

11 files changed, 189 insertions, 84 deletions

diff --git a/dts/Bindings/serial/8250_omap.yaml b/dts/Bindings/serial/8250_omap.yaml
index 70ca61688b..7b34ec8fa9 100644
--- a/dts/Bindings/serial/8250_omap.yaml
+++ b/dts/Bindings/serial/8250_omap.yaml
@@ -86,7 +86,7 @@ required:
   - reg
   - interrupts
 
-additionalProperties: false
+unevaluatedProperties: false
 
 if:
   properties:
diff --git a/dts/Bindings/serial/brcm,bcm6345-uart.txt b/dts/Bindings/serial/brcm,bcm6345-uart.txt
deleted file mode 100644
index 8b2b046025..0000000000
--- a/dts/Bindings/serial/brcm,bcm6345-uart.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-* BCM63xx UART
-
-Required properties:
-
-- compatible: "brcm,bcm6345-uart"
-
-- reg: The base address of the UART register bank.
-
-- interrupts: A single interrupt specifier.
-
-- clocks: Clock driving the hardware; used to figure out the baud rate
-  divisor.
-
-
-Optional properties:
-
-- clock-names: Should be "refclk".
-
-Example:
-
-	uart0: serial@14e00520 {
-		compatible = "brcm,bcm6345-uart";
-		reg = <0x14e00520 0x18>;
-		interrupt-parent = <&periph_intc>;
-		interrupts = <2>;
-		clocks = <&periph_clk>;
-		clock-names = "refclk";
-	};
-
-	clocks {
-		periph_clk: periph_clk@0 {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <54000000>;
-		};
-	};
diff --git a/dts/Bindings/serial/brcm,bcm6345-uart.yaml b/dts/Bindings/serial/brcm,bcm6345-uart.yaml
new file mode 100644
index 0000000000..a22285c43f
--- /dev/null
+++ b/dts/Bindings/serial/brcm,bcm6345-uart.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/brcm,bcm6345-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BCM63xx UART
+
+maintainers:
+  - Rafał Miłecki <rafal@milecki.pl>
+
+allOf:
+  - $ref: serial.yaml#
+
+properties:
+  compatible:
+    const: brcm,bcm6345-uart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: refclk
+
+unevaluatedProperties: false
+
+required:
+  - reg
+  - interrupts
+  - clocks
+
+examples:
+  - |
+    serial@14e00520 {
+        compatible = "brcm,bcm6345-uart";
+        reg = <0x14e00520 0x18>;
+        interrupt-parent = <&periph_intc>;
+        interrupts = <2>;
+        clocks = <&periph_clk>;
+        clock-names = "refclk";
+    };
diff --git a/dts/Bindings/serial/fsl,s32-linflexuart.txt b/dts/Bindings/serial/fsl,s32-linflexuart.txt
deleted file mode 100644
index f1bbe0826b..0000000000
--- a/dts/Bindings/serial/fsl,s32-linflexuart.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Freescale LINFlexD UART
-
-The LINFlexD controller implements several LIN protocol versions, as well as
-support for full-duplex UART communication through 8-bit and 9-bit frames.
-
-See chapter 47 ("LINFlexD") in the reference manual[1].
-
-Required properties:
-- compatible :
-  - "fsl,s32v234-linflexuart" for LINFlexD configured in UART mode, which
-    is compatible with the one integrated on S32V234 SoC
-- reg : Address and length of the register set for the device
-- interrupts : Should contain uart interrupt
-
-Example:
-uart0: serial@40053000 {
-	compatible = "fsl,s32v234-linflexuart";
-	reg = <0x0 0x40053000 0x0 0x1000>;
-	interrupts = <0 59 4>;
-};
-
-[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM
diff --git a/dts/Bindings/serial/fsl,s32-linflexuart.yaml b/dts/Bindings/serial/fsl,s32-linflexuart.yaml
new file mode 100644
index 0000000000..8b643bae3c
--- /dev/null
+++ b/dts/Bindings/serial/fsl,s32-linflexuart.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale LINFlexD UART
+
+description: |
+  The LINFlexD controller implements several LIN protocol versions, as well
+  as support for full-duplex UART communication through 8-bit and 9-bit
+  frames. See chapter 47 ("LINFlexD") in the reference manual
+  https://www.nxp.com/webapp/Download?colCode=S32V234RM.
+
+maintainers:
+  - Chester Lin <clin@suse.com>
+
+allOf:
+  - $ref: "serial.yaml"
+
+properties:
+  compatible:
+    oneOf:
+      - const: fsl,s32v234-linflexuart
+      - items:
+          - const: nxp,s32g2-linflexuart
+          - const: fsl,s32v234-linflexuart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    serial@40053000 {
+        compatible = "fsl,s32v234-linflexuart";
+        reg = <0x40053000 0x1000>;
+        interrupts = <0 59 4>;
+    };
diff --git a/dts/Bindings/serial/ingenic,uart.yaml b/dts/Bindings/serial/ingenic,uart.yaml
index b432d4dff7..9ca7a18ecd 100644
--- a/dts/Bindings/serial/ingenic,uart.yaml
+++ b/dts/Bindings/serial/ingenic,uart.yaml
@@ -71,7 +71,7 @@ unevaluatedProperties: false
 
 examples:
   - |
-    #include <dt-bindings/clock/jz4780-cgu.h>
+    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
     #include <dt-bindings/dma/jz4780-dma.h>
     #include <dt-bindings/gpio/gpio.h>
     serial@10032000 {
diff --git a/dts/Bindings/serial/samsung_uart.yaml b/dts/Bindings/serial/samsung_uart.yaml
index f064e5b76c..2940afb874 100644
--- a/dts/Bindings/serial/samsung_uart.yaml
+++ b/dts/Bindings/serial/samsung_uart.yaml
@@ -26,6 +26,7 @@ properties:
           - samsung,s3c6400-uart
           - samsung,s5pv210-uart
           - samsung,exynos4210-uart
+          - samsung,exynos850-uart
 
   reg:
     maxItems: 1
diff --git a/dts/Bindings/serial/sprd-uart.yaml b/dts/Bindings/serial/sprd-uart.yaml
index 09f6283f3c..a444bebd2c 100644
--- a/dts/Bindings/serial/sprd-uart.yaml
+++ b/dts/Bindings/serial/sprd-uart.yaml
@@ -19,6 +19,7 @@ properties:
           - enum:
               - sprd,sc9860-uart
               - sprd,sc9863a-uart
+              - sprd,ums512-uart
           - const: sprd,sc9836-uart
       - const: sprd,sc9836-uart
 
diff --git a/dts/Bindings/serial/st,stm32-uart.yaml b/dts/Bindings/serial/st,stm32-uart.yaml
index f50f4ca893..333dc42722 100644
--- a/dts/Bindings/serial/st,stm32-uart.yaml
+++ b/dts/Bindings/serial/st,stm32-uart.yaml
@@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 maintainers:
-  - Erwan Le Ray <erwan.leray@st.com>
+  - Erwan Le Ray <erwan.leray@foss.st.com>
 
 title: STMicroelectronics STM32 USART bindings
 
diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.txt b/dts/Bindings/serial/xlnx,opb-uartlite.txt
deleted file mode 100644
index c37deb44de..0000000000
--- a/dts/Bindings/serial/xlnx,opb-uartlite.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Xilinx Axi Uartlite controller Device Tree Bindings
----------------------------------------------------------
-
-Required properties:
-- compatible		: Can be either of
-				"xlnx,xps-uartlite-1.00.a"
-				"xlnx,opb-uartlite-1.00.b"
-- reg			: Physical base address and size of the Axi Uartlite
-			  registers map.
-- interrupts		: Should contain the UART controller interrupt.
-
-Optional properties:
-- port-number		: Set Uart port number
-- clock-names		: Should be "s_axi_aclk"
-- clocks		: Input clock specifier. Refer to common clock bindings.
-
-Example:
-serial@800c0000 {
-	compatible = "xlnx,xps-uartlite-1.00.a";
-	reg = <0x0 0x800c0000 0x10000>;
-	interrupts = <0x0 0x6e 0x1>;
-	port-number = <0>;
-};
diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.yaml b/dts/Bindings/serial/xlnx,opb-uartlite.yaml
new file mode 100644
index 0000000000..f7617b88c7
--- /dev/null
+++ b/dts/Bindings/serial/xlnx,opb-uartlite.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Axi Uartlite
+
+maintainers:
+  - Peter Korsgaard <jacmet@sunsite.dk>
+
+properties:
+  compatible:
+    contains:
+      enum:
+        - xlnx,xps-uartlite-1.00.a
+        - xlnx,opb-uartlite-1.00.b
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  port-number:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Set Uart port number
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: s_axi_aclk
+
+  current-speed:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The fixed baud rate that the device was configured for.
+
+  xlnx,data-bits:
+    enum: [5, 6, 7, 8]
+    description:
+      The fixed number of data bits that the device was configured for.
+
+  xlnx,use-parity:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    description:
+      Whether parity checking was enabled when the device was configured.
+
+  xlnx,odd-parity:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    description:
+      Whether odd parity was configured.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - current-speed
+  - xlnx,data-bits
+  - xlnx,use-parity
+
+allOf:
+  - $ref: /schemas/serial.yaml#
+  - if:
+      properties:
+        xlnx,use-parity:
+          contains:
+            const: 1
+    then:
+      required:
+        - xlnx,odd-parity
+
+unevaluatedProperties: false
+
+examples:
+  - |
+      serial@800c0000 {
+        compatible = "xlnx,xps-uartlite-1.00.a";
+        reg = <0x800c0000 0x10000>;
+        interrupts = <0x0 0x6e 0x1>;
+        port-number = <0>;
+        current-speed = <115200>;
+        xlnx,data-bits = <8>;
+        xlnx,use-parity = <0>;
+      };
+...