dts: update to v5.11-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

5 files changed, 48 insertions, 4 deletions

diff --git a/dts/Bindings/serial/8250.yaml b/dts/Bindings/serial/8250.yaml
index c1d4c196f0..f54cae9ff7 100644
--- a/dts/Bindings/serial/8250.yaml
+++ b/dts/Bindings/serial/8250.yaml
@@ -126,7 +126,7 @@ properties:
     maxItems: 1
 
   current-speed:
-    $ref: /schemas/types.yaml#definitions/uint32
+    $ref: /schemas/types.yaml#/definitions/uint32
     description: The current active speed of the UART.
 
   reg-offset:
@@ -154,7 +154,7 @@ properties:
       Set to indicate that the port does not implement loopback test mode.
 
   fifo-size:
-    $ref: /schemas/types.yaml#definitions/uint32
+    $ref: /schemas/types.yaml#/definitions/uint32
     description: The fifo size of the UART.
 
   auto-flow-control:
@@ -165,7 +165,7 @@ properties:
       property.
 
   tx-threshold:
-    $ref: /schemas/types.yaml#definitions/uint32
+    $ref: /schemas/types.yaml#/definitions/uint32
     description: |
       Specify the TX FIFO low water indication for parts with programmable
       TX FIFO thresholds.
diff --git a/dts/Bindings/serial/litex,liteuart.yaml b/dts/Bindings/serial/litex,liteuart.yaml
new file mode 100644
index 0000000000..c4f1f489dc
--- /dev/null
+++ b/dts/Bindings/serial/litex,liteuart.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LiteUART serial controller
+
+maintainers:
+  - Karol Gugala <kgugala@antmicro.com>
+  - Mateusz Holenko <mholenko@antmicro.com>
+
+description: |
+  LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports
+  multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.
+
+properties:
+  compatible:
+    const: litex,liteuart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    uart0: serial@e0001800 {
+      compatible = "litex,liteuart";
+      reg = <0xe0001800 0x100>;
+      interrupts = <2>;
+    };
diff --git a/dts/Bindings/serial/omap_serial.txt b/dts/Bindings/serial/omap_serial.txt
index dcba86b0a0..c2db8cabf2 100644
--- a/dts/Bindings/serial/omap_serial.txt
+++ b/dts/Bindings/serial/omap_serial.txt
@@ -1,6 +1,7 @@
 OMAP UART controller
 
 Required properties:
+- compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers
 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
 - compatible : should be "ti,am654-uart" for AM654 controllers
 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
diff --git a/dts/Bindings/serial/renesas,scif.yaml b/dts/Bindings/serial/renesas,scif.yaml
index eda3d2c6bd..672158906c 100644
--- a/dts/Bindings/serial/renesas,scif.yaml
+++ b/dts/Bindings/serial/renesas,scif.yaml
@@ -60,6 +60,7 @@ properties:
               - renesas,scif-r8a77980     # R-Car V3H
               - renesas,scif-r8a77990     # R-Car E3
               - renesas,scif-r8a77995     # R-Car D3
+              - renesas,scif-r8a779a0     # R-Car V3U
           - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
           - const: renesas,scif           # generic SCIF compatible UART
 
diff --git a/dts/Bindings/serial/sifive-serial.yaml b/dts/Bindings/serial/sifive-serial.yaml
index 92283f693d..3ac5c7ff27 100644
--- a/dts/Bindings/serial/sifive-serial.yaml
+++ b/dts/Bindings/serial/sifive-serial.yaml
@@ -17,7 +17,9 @@ allOf:
 properties:
   compatible:
     items:
-      - const: sifive,fu540-c000-uart
+      - enum:
+          - sifive,fu540-c000-uart
+          - sifive,fu740-c000-uart
       - const: sifive,uart0
 
     description: