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authorSascha Hauer <s.hauer@pengutronix.de>2019-06-05 00:06:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-06-11 09:11:11 +0200
commit796af3473b8222bcd89aa63e9886c355a6baf95d (patch)
treead357b2756bda409b46747faaaf57a0ffd003c9c /dts/Bindings/serial
parent649b9ebcf53d697277bcdb01334dbcd563a33aa8 (diff)
downloadbarebox-796af3473b8222bcd89aa63e9886c355a6baf95d.tar.gz
barebox-796af3473b8222bcd89aa63e9886c355a6baf95d.tar.xz
dts: update to v5.2-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/serial')
-rw-r--r--dts/Bindings/serial/cdns,uart.txt5
-rw-r--r--dts/Bindings/serial/mtk-uart.txt4
-rw-r--r--dts/Bindings/serial/nxp,sc16is7xx.txt2
-rw-r--r--dts/Bindings/serial/sifive-serial.txt33
-rw-r--r--dts/Bindings/serial/sprd-uart.txt17
5 files changed, 58 insertions, 3 deletions
diff --git a/dts/Bindings/serial/cdns,uart.txt b/dts/Bindings/serial/cdns,uart.txt
index 227bb770b0..4efc560f90 100644
--- a/dts/Bindings/serial/cdns,uart.txt
+++ b/dts/Bindings/serial/cdns,uart.txt
@@ -12,6 +12,11 @@ Required properties:
See ../clocks/clock-bindings.txt for details.
+Optional properties:
+- cts-override : Override the CTS modem status signal. This signal will
+ always be reported as active instead of being obtained from the modem status
+ register. Define this if your serial port does not use this pin
+
Example:
uart@e0000000 {
compatible = "cdns,uart-r1p8";
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index bcfb13194f..c6b5262eb3 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -1,4 +1,4 @@
-* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
+* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
Required properties:
- compatible should contain:
@@ -13,10 +13,12 @@ Required properties:
* "mediatek,mt6797-uart" for MT6797 compatible UARTS
* "mediatek,mt7622-uart" for MT7622 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
+ * "mediatek,mt7629-uart" for MT7629 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
+ * "mediatek,mt8516-uart" for MT8516 compatible UARTS
* "mediatek,mt6577-uart" for MT6577 and all of the above
- reg: The base address of the UART register bank.
diff --git a/dts/Bindings/serial/nxp,sc16is7xx.txt b/dts/Bindings/serial/nxp,sc16is7xx.txt
index e7921a8e27..c1091a923a 100644
--- a/dts/Bindings/serial/nxp,sc16is7xx.txt
+++ b/dts/Bindings/serial/nxp,sc16is7xx.txt
@@ -12,6 +12,8 @@ Required properties:
- reg: I2C address of the SC16IS7xx device.
- interrupts: Should contain the UART interrupt
- clocks: Reference to the IC source clock.
+ OR (when there is no clock provider visible to the platform)
+- clock-frequency: The source clock frequency for the IC.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
diff --git a/dts/Bindings/serial/sifive-serial.txt b/dts/Bindings/serial/sifive-serial.txt
new file mode 100644
index 0000000000..c86b1e5241
--- /dev/null
+++ b/dts/Bindings/serial/sifive-serial.txt
@@ -0,0 +1,33 @@
+SiFive asynchronous serial interface (UART)
+
+Required properties:
+
+- compatible: should be something similar to
+ "sifive,<chip>-uart" for the UART as integrated
+ on a particular chip, and "sifive,uart<version>" for the
+ general UART IP block programming model. Supported
+ compatible strings as of the date of this writing are:
+ "sifive,fu540-c000-uart" for the SiFive UART v0 as
+ integrated onto the SiFive FU540 chip, or "sifive,uart0"
+ for the SiFive UART v0 IP block with no chip integration
+ tweaks (if any)
+- reg: address and length of the register space
+- interrupts: Should contain the UART interrupt identifier
+- clocks: Should contain a clock identifier for the UART's parent clock
+
+
+UART HDL that corresponds to the IP block version numbers can be found
+here:
+
+https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
+
+
+Example:
+
+uart0: serial@10010000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ interrupt-parent = <&plic0>;
+ interrupts = <80>;
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+};
diff --git a/dts/Bindings/serial/sprd-uart.txt b/dts/Bindings/serial/sprd-uart.txt
index cab40f0f6f..9607dc6162 100644
--- a/dts/Bindings/serial/sprd-uart.txt
+++ b/dts/Bindings/serial/sprd-uart.txt
@@ -7,7 +7,17 @@ Required properties:
- reg: offset and length of the register set for the device
- interrupts: exactly one interrupt specifier
-- clocks: phandles to input clocks.
+- clock-names: Should contain following entries:
+ "enable" for UART module enable clock,
+ "uart" for UART clock,
+ "source" for UART source (parent) clock.
+- clocks: Should contain a clock specifier for each entry in clock-names.
+ UART clock and source clock are optional properties, but enable clock
+ is required.
+
+Optional properties:
+- dma-names: Should contain "rx" for receive and "tx" for transmit channels.
+- dmas: A list of dma specifiers, one for each entry in dma-names.
Example:
uart0: serial@0 {
@@ -15,5 +25,8 @@ Example:
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ext_26m>;
+ dma-names = "rx", "tx";
+ dmas = <&ap_dma 19>, <&ap_dma 20>;
+ clock-names = "enable", "uart", "source";
+ clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>;
};