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authorSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
commit574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (patch)
tree3fbe9ed379bc0d6c536860845e85a4ede4b36bbc /dts/Bindings/soc
parent179dedbc6d85d7ea7c8013513b364a75f32943e8 (diff)
downloadbarebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.gz
barebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.xz
dts: update to v5.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/soc')
-rw-r--r--dts/Bindings/soc/amlogic/amlogic,canvas.txt33
-rw-r--r--dts/Bindings/soc/amlogic/amlogic,canvas.yaml49
-rw-r--r--dts/Bindings/soc/bcm/brcm,bcm2835-pm.txt2
-rw-r--r--dts/Bindings/soc/fsl/rcpm.txt14
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt2
-rw-r--r--dts/Bindings/soc/qcom/qcom,smd-rpm.txt1
-rw-r--r--dts/Bindings/soc/rockchip/grf.txt18
-rw-r--r--dts/Bindings/soc/ti/sci-pm-domain.txt2
8 files changed, 78 insertions, 43 deletions
diff --git a/dts/Bindings/soc/amlogic/amlogic,canvas.txt b/dts/Bindings/soc/amlogic/amlogic,canvas.txt
deleted file mode 100644
index e876f3ce54..0000000000
--- a/dts/Bindings/soc/amlogic/amlogic,canvas.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Amlogic Canvas
-================================
-
-A canvas is a collection of metadata that describes a pixel buffer.
-Those metadata include: width, height, phyaddr, wrapping and block mode.
-Starting with GXBB the endianness can also be described.
-
-Many IPs within Amlogic SoCs rely on canvas indexes to read/write pixel data
-rather than use the phy addresses directly. For instance, this is the case for
-the video decoders and the display.
-
-Amlogic SoCs have 256 canvas.
-
-Device Tree Bindings:
----------------------
-
-Video Lookup Table
---------------------------
-
-Required properties:
-- compatible: has to be one of:
- - "amlogic,meson8-canvas", "amlogic,canvas" on Meson8
- - "amlogic,meson8b-canvas", "amlogic,canvas" on Meson8b
- - "amlogic,meson8m2-canvas", "amlogic,canvas" on Meson8m2
- - "amlogic,canvas" on GXBB and newer
-- reg: Base physical address and size of the canvas registers.
-
-Example:
-
-canvas: video-lut@48 {
- compatible = "amlogic,canvas";
- reg = <0x0 0x48 0x0 0x14>;
-};
diff --git a/dts/Bindings/soc/amlogic/amlogic,canvas.yaml b/dts/Bindings/soc/amlogic/amlogic,canvas.yaml
new file mode 100644
index 0000000000..f548594d02
--- /dev/null
+++ b/dts/Bindings/soc/amlogic/amlogic,canvas.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Canvas Video Lookup Table
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+ - Maxime Jourdan <mjourdan@baylibre.com>
+
+description: |
+ A canvas is a collection of metadata that describes a pixel buffer.
+ Those metadata include: width, height, phyaddr, wrapping and block mode.
+ Starting with GXBB the endianness can also be described.
+
+ Many IPs within Amlogic SoCs rely on canvas indexes to read/write pixel data
+ rather than use the phy addresses directly. For instance, this is the case for
+ the video decoders and the display.
+
+ Amlogic SoCs have 256 canvas.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amlogic,meson8-canvas
+ - amlogic,meson8b-canvas
+ - amlogic,meson8m2-canvas
+ - const: amlogic,canvas
+ - const: amlogic,canvas # GXBB and newer SoCs
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ canvas: video-lut@48 {
+ compatible = "amlogic,canvas";
+ reg = <0x48 0x14>;
+ };
+
diff --git a/dts/Bindings/soc/bcm/brcm,bcm2835-pm.txt b/dts/Bindings/soc/bcm/brcm,bcm2835-pm.txt
index 3b7d329563..72ff033565 100644
--- a/dts/Bindings/soc/bcm/brcm,bcm2835-pm.txt
+++ b/dts/Bindings/soc/bcm/brcm,bcm2835-pm.txt
@@ -26,7 +26,7 @@ Optional properties:
system power. This node follows the power controller bindings[3].
[1] Documentation/devicetree/bindings/reset/reset.txt
-[2] Documentation/devicetree/bindings/power/power_domain.txt
+[2] Documentation/devicetree/bindings/power/power-domain.yaml
[3] Documentation/devicetree/bindings/power/power-controller.txt
Example:
diff --git a/dts/Bindings/soc/fsl/rcpm.txt b/dts/Bindings/soc/fsl/rcpm.txt
index e284e4e1cc..5a33619d88 100644
--- a/dts/Bindings/soc/fsl/rcpm.txt
+++ b/dts/Bindings/soc/fsl/rcpm.txt
@@ -5,7 +5,7 @@ and power management.
Required properites:
- reg : Offset and length of the register set of the RCPM block.
- - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
+ - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
fsl,rcpm-wakeup property.
- compatible : Must contain a chip-specific RCPM block compatible string
and (if applicable) may contain a chassis-version RCPM compatible
@@ -20,6 +20,7 @@ Required properites:
* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+ * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
@@ -27,14 +28,19 @@ Chassis Version Example Chips
--------------- -------------------------------
1.0 p4080, p5020, p5040, p2041, p3041
2.0 t4240, b4860, b4420
-2.1 t1040, ls1021
+2.1 t1040,
+2.1+ ls1021a, ls1012a, ls1043a, ls1046a
+
+Optional properties:
+ - little-endian : RCPM register block is Little Endian. Without it RCPM
+ will be Big Endian (default case).
Example:
The RCPM node for T4240:
rcpm: global-utilities@e2000 {
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
reg = <0xe2000 0x1000>;
- fsl,#rcpm-wakeup-cells = <2>;
+ #fsl,rcpm-wakeup-cells = <2>;
};
* Freescale RCPM Wakeup Source Device Tree Bindings
@@ -44,7 +50,7 @@ can be used as a wakeup source.
- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
register cells. The number of IPPDEXPCR register cells is defined in
- "fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is
+ "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
the bit mask that should be set in IPPDEXPCR0, and the second register
cell is for IPPDEXPCR1, and so on.
diff --git a/dts/Bindings/soc/mediatek/scpsys.txt b/dts/Bindings/soc/mediatek/scpsys.txt
index 876693a7ad..8f469d8583 100644
--- a/dts/Bindings/soc/mediatek/scpsys.txt
+++ b/dts/Bindings/soc/mediatek/scpsys.txt
@@ -8,7 +8,7 @@ The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
domain control.
The driver implements the Generic PM domain bindings described in
-power/power_domain.txt. It provides the power domains defined in
+power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt2701-power.h
diff --git a/dts/Bindings/soc/qcom/qcom,smd-rpm.txt b/dts/Bindings/soc/qcom/qcom,smd-rpm.txt
index f3fa313963..616fddcd09 100644
--- a/dts/Bindings/soc/qcom/qcom,smd-rpm.txt
+++ b/dts/Bindings/soc/qcom/qcom,smd-rpm.txt
@@ -22,6 +22,7 @@ resources.
"qcom,rpm-apq8084"
"qcom,rpm-msm8916"
"qcom,rpm-msm8974"
+ "qcom,rpm-msm8976"
"qcom,rpm-msm8998"
"qcom,rpm-sdm660"
"qcom,rpm-qcs404"
diff --git a/dts/Bindings/soc/rockchip/grf.txt b/dts/Bindings/soc/rockchip/grf.txt
index 46e27cd69f..f96511aa38 100644
--- a/dts/Bindings/soc/rockchip/grf.txt
+++ b/dts/Bindings/soc/rockchip/grf.txt
@@ -10,6 +10,12 @@ From RK3368 SoCs, the GRF is divided into two sections,
On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
+ON RK3308 SoC, the GRF is divided into four sections:
+- GRF, used for general non-secure system,
+- SGRF, used for general secure system,
+- DETECTGRF, used for audio codec system,
+- COREGRF, used for pvtm,
+
Required Properties:
- compatible: GRF should be one of the following:
@@ -19,19 +25,25 @@ Required Properties:
- "rockchip,rk3188-grf", "syscon": for rk3188
- "rockchip,rk3228-grf", "syscon": for rk3228
- "rockchip,rk3288-grf", "syscon": for rk3288
+ - "rockchip,rk3308-grf", "syscon": for rk3308
- "rockchip,rk3328-grf", "syscon": for rk3328
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
- "rockchip,rv1108-grf", "syscon": for rv1108
+- compatible: DETECTGRF should be one of the following:
+ - "rockchip,rk3308-detect-grf", "syscon": for rk3308
+- compatilbe: COREGRF should be one of the following:
+ - "rockchip,rk3308-core-grf", "syscon": for rk3308
- compatible: PMUGRF should be one of the following:
- "rockchip,px30-pmugrf", "syscon": for px30
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
-- compatible: SGRF should be one of the following
+- compatible: SGRF should be one of the following:
- "rockchip,rk3288-sgrf", "syscon": for rk3288
-- compatible: USB2PHYGRF should be one of the followings
+- compatible: USB2PHYGRF should be one of the following:
+ - "rockchip,px30-usb2phy-grf", "syscon": for px30
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
-- compatible: USBGRF should be one of the following
+- compatible: USBGRF should be one of the following:
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/soc/ti/sci-pm-domain.txt b/dts/Bindings/soc/ti/sci-pm-domain.txt
index f541d1f776..6217e64309 100644
--- a/dts/Bindings/soc/ti/sci-pm-domain.txt
+++ b/dts/Bindings/soc/ti/sci-pm-domain.txt
@@ -12,7 +12,7 @@ PM Domain Node
==============
The PM domain node represents the global PM domain managed by the PMMC, which
in this case is the implementation as documented by the generic PM domain
-bindings in Documentation/devicetree/bindings/power/power_domain.txt. Because
+bindings in Documentation/devicetree/bindings/power/power-domain.yaml. Because
this relies on the TI SCI protocol to communicate with the PMMC it must be a
child of the pmmc node.