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authorSascha Hauer <s.hauer@pengutronix.de>2018-09-11 08:26:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-09-11 17:23:13 +0200
commit35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch)
treedd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/Bindings/sound/amlogic,axg-fifo.txt
parent625eea2765d94aee016cf25d9cabecde8eae0775 (diff)
downloadbarebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz
barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.xz
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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+* Amlogic Audio FIFO controllers
+
+Required properties:
+- compatible: 'amlogic,axg-toddr' or
+ 'amlogic,axg-frddr'
+- reg: physical base address of the controller and length of memory
+ mapped region.
+- interrupts: interrupt specifier for the fifo.
+- clocks: phandle to the fifo peripheral clock provided by the audio
+ clock controller.
+- resets: phandle to memory ARB line provided by the arb reset controller.
+- #sound-dai-cells: must be 0.
+
+Example of FRDDR A on the A113 SoC:
+
+frddr_a: audio-controller@1c0 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x1c0 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+ resets = <&arb AXG_ARB_FRDDR_A>;
+};