path: root/dts/Bindings/spi
diff options
authorSascha Hauer <>2017-11-28 11:02:14 +0100
committerSascha Hauer <>2017-11-28 11:06:44 +0100
commit2e9cce8fb1f577088e2b20ae2f461130e13ad190 (patch)
treef82ae53e88d36e07608be1b3159da296ed025ef1 /dts/Bindings/spi
parentc68d466d263827692aa809e6b34abb90a1cab515 (diff)
dts: update to v4.15-rc1
Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'dts/Bindings/spi')
7 files changed, 80 insertions, 6 deletions
diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt
index e865855726..bdd8395901 100644
--- a/dts/Bindings/spi/sh-msiof.txt
+++ b/dts/Bindings/spi/sh-msiof.txt
@@ -1,7 +1,9 @@
Renesas MSIOF spi controller
Required properties:
-- compatible : "renesas,msiof-r8a7790" (R-Car H2)
+- compatible : "renesas,msiof-r8a7743" (RZ/G1M)
+ "renesas,msiof-r8a7745" (RZ/G1E)
+ "renesas,msiof-r8a7790" (R-Car H2)
"renesas,msiof-r8a7791" (R-Car M2-W)
"renesas,msiof-r8a7792" (R-Car V2H)
"renesas,msiof-r8a7793" (R-Car M2-N)
@@ -10,7 +12,7 @@ Required properties:
"renesas,msiof-r8a7796" (R-Car M3-W)
"renesas,msiof-sh73a0" (SH-Mobile AG5)
"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
- "renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
+ "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
"renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
"renesas,sh-msiof" (deprecated)
diff --git a/dts/Bindings/spi/spi-davinci.txt b/dts/Bindings/spi/spi-davinci.txt
index f5916c92fe..1925277bfc 100644
--- a/dts/Bindings/spi/spi-davinci.txt
+++ b/dts/Bindings/spi/spi-davinci.txt
@@ -24,6 +24,16 @@ Required properties:
based on a specific SoC configuration.
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
+ For 66AK2G this property should be set per binding,
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+SoC-specific Required Properties:
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the SPI device id
+ value. This property is as per the binding,
- cs-gpios: gpio chip selects
diff --git a/dts/Bindings/spi/spi-fsl-dspi.txt b/dts/Bindings/spi/spi-fsl-dspi.txt
index 13b1fcc846..dcc7eaada5 100644
--- a/dts/Bindings/spi/spi-fsl-dspi.txt
+++ b/dts/Bindings/spi/spi-fsl-dspi.txt
@@ -5,6 +5,7 @@ Required properties:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
+ "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
- clocks: from common clock binding: handle to dspi clock.
diff --git a/dts/Bindings/spi/spi-rspi.txt b/dts/Bindings/spi/spi-rspi.txt
index 8f4169f639..3b02b3a7cf 100644
--- a/dts/Bindings/spi/spi-rspi.txt
+++ b/dts/Bindings/spi/spi-rspi.txt
@@ -5,11 +5,14 @@ Required properties:
"renesas,rspi-<soctype>", "renesas,rspi" as fallback.
For Renesas Serial Peripheral Interface on RZ/A1H:
"renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
- For Quad Serial Peripheral Interface on R-Car Gen2:
+ For Quad Serial Peripheral Interface on R-Car Gen2 and
+ RZ/G1 devices:
"renesas,qspi-<soctype>", "renesas,qspi" as fallback.
Examples with soctypes are:
- "renesas,rspi-sh7757" (SH)
- "renesas,rspi-r7s72100" (RZ/A1H)
+ - "renesas,qspi-r8a7743" (RZ/G1M)
+ - "renesas,qspi-r8a7745" (RZ/G1E)
- "renesas,qspi-r8a7790" (R-Car H2)
- "renesas,qspi-r8a7791" (R-Car M2-W)
- "renesas,qspi-r8a7792" (R-Car V2H)
diff --git a/dts/Bindings/spi/spi-sprd-adi.txt b/dts/Bindings/spi/spi-sprd-adi.txt
new file mode 100644
index 0000000000..8de589b376
--- /dev/null
+++ b/dts/Bindings/spi/spi-sprd-adi.txt
@@ -0,0 +1,58 @@
+Spreadtrum ADI controller
+ADI is the abbreviation of Anolog-Digital interface, which is used to access
+analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
+framework for its hardware implementation is alike to SPI bus and its timing
+is compatile to SPI timing.
+ADI controller has 50 channels including 2 software read/write channels and
+48 hardware channels to access analog chip. For 2 software read/write channels,
+users should set ADI registers to access analog chip. For hardware channels,
+we can configure them to allow other hardware components to use it independently,
+which means we can just link one analog chip address to one hardware channel,
+then users can access the mapped analog chip address by this hardware channel
+triggered by hardware components instead of ADI software channels.
+Thus we introduce one property named "sprd,hw-channels" to configure hardware
+channels, the first value specifies the hardware channel id which is used to
+transfer data triggered by hardware automatically, and the second value specifies
+the analog chip address where user want to access by hardware components.
+Since we have multi-subsystems will use unique ADI to access analog chip, when
+one system is reading/writing data by ADI software channels, that should be under
+one hardware spinlock protection to prevent other systems from reading/writing
+data by ADI software channels at the same time, or two parallel routine of setting
+ADI registers will make ADI controller registers chaos to lead incorrect results.
+Then we need one hardware spinlock to synchronize between the multiple subsystems.
+Required properties:
+- compatible: Should be "sprd,sc9860-adi".
+- reg: Offset and length of ADI-SPI controller register space.
+- hwlocks: Reference to a phandle of a hwlock provider node.
+- hwlock-names: Reference to hwlock name strings defined in the same order
+ as the hwlocks, should be "adi".
+- #address-cells: Number of cells required to define a chip select address
+ on the ADI-SPI bus. Should be set to 1.
+- #size-cells: Size of cells required to define a chip select address size
+ on the ADI-SPI bus. Should be set to 0.
+Optional properties:
+- sprd,hw-channels: This is an array of channel values up to 49 channels.
+ The first value specifies the hardware channel id which is used to
+ transfer data triggered by hardware automatically, and the second
+ value specifies the analog chip address where user want to access
+ by hardware components.
+SPI slave nodes must be children of the SPI controller node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+ adi_bus: spi@40030000 {
+ compatible = "sprd,sc9860-adi";
+ reg = <0 0x40030000 0 0x10000>;
+ hwlocks = <&hwlock1 0>;
+ hwlock-names = "adi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sprd,hw-channels = <30 0x8c20>;
+ };
diff --git a/dts/Bindings/spi/spi-sun4i.txt b/dts/Bindings/spi/spi-sun4i.txt
index 484bbff533..c75d604a82 100644
--- a/dts/Bindings/spi/spi-sun4i.txt
+++ b/dts/Bindings/spi/spi-sun4i.txt
@@ -12,7 +12,7 @@ Required properties:
-spi1: spi@01c06000 {
+spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
diff --git a/dts/Bindings/spi/spi-sun6i.txt b/dts/Bindings/spi/spi-sun6i.txt
index ab1811354c..435a8e0731 100644
--- a/dts/Bindings/spi/spi-sun6i.txt
+++ b/dts/Bindings/spi/spi-sun6i.txt
@@ -19,7 +19,7 @@ Optional properties:
-spi1: spi@01c69000 {
+spi1: spi@1c69000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c69000 0x1000>;
interrupts = <0 66 4>;
@@ -28,7 +28,7 @@ spi1: spi@01c69000 {
resets = <&ahb1_rst 21>;
-spi0: spi@01c68000 {
+spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;