summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/spi
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
commit574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (patch)
tree3fbe9ed379bc0d6c536860845e85a4ede4b36bbc /dts/Bindings/spi
parent179dedbc6d85d7ea7c8013513b364a75f32943e8 (diff)
downloadbarebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.gz
barebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.xz
dts: update to v5.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/spi')
-rw-r--r--dts/Bindings/spi/renesas,hspi.yaml57
-rw-r--r--dts/Bindings/spi/renesas,rzn1-spi.txt11
-rw-r--r--dts/Bindings/spi/renesas,sh-msiof.yaml159
-rw-r--r--dts/Bindings/spi/sh-hspi.txt26
-rw-r--r--dts/Bindings/spi/sh-msiof.txt105
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.txt3
-rw-r--r--dts/Bindings/spi/spi-sifive.txt37
-rw-r--r--dts/Bindings/spi/spi-sifive.yaml86
-rw-r--r--dts/Bindings/spi/spi-stm32-qspi.txt47
-rw-r--r--dts/Bindings/spi/spi-xilinx.txt4
-rw-r--r--dts/Bindings/spi/st,stm32-qspi.yaml83
11 files changed, 401 insertions, 217 deletions
diff --git a/dts/Bindings/spi/renesas,hspi.yaml b/dts/Bindings/spi/renesas,hspi.yaml
new file mode 100644
index 0000000000..c429cf4bea
--- /dev/null
+++ b/dts/Bindings/spi/renesas,hspi.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/renesas,hspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas HSPI
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,hspi-r8a7778 # R-Car M1A
+ - renesas,hspi-r8a7779 # R-Car H1
+ - const: renesas,hspi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7778-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ hspi0: spi@fffc7000 {
+ compatible = "renesas,hspi-r8a7778", "renesas,hspi";
+ reg = <0xfffc7000 0x18>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
diff --git a/dts/Bindings/spi/renesas,rzn1-spi.txt b/dts/Bindings/spi/renesas,rzn1-spi.txt
new file mode 100644
index 0000000000..fb1a672863
--- /dev/null
+++ b/dts/Bindings/spi/renesas,rzn1-spi.txt
@@ -0,0 +1,11 @@
+Renesas RZ/N1 SPI Controller
+
+This controller is based on the Synopsys DW Synchronous Serial Interface and
+inherits all properties defined in snps,dw-apb-ssi.txt except for the
+compatible property.
+
+Required properties:
+- compatible : The device specific string followed by the generic RZ/N1 string.
+ Therefore it must be one of:
+ "renesas,r9a06g032-spi", "renesas,rzn1-spi"
+ "renesas,r9a06g033-spi", "renesas,rzn1-spi"
diff --git a/dts/Bindings/spi/renesas,sh-msiof.yaml b/dts/Bindings/spi/renesas,sh-msiof.yaml
new file mode 100644
index 0000000000..b6c1dd2a9c
--- /dev/null
+++ b/dts/Bindings/spi/renesas,sh-msiof.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas MSIOF SPI controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: renesas,msiof-sh73a0 # SH-Mobile AG5
+ - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
+ # device
+ - items:
+ - enum:
+ - renesas,msiof-r8a7743 # RZ/G1M
+ - renesas,msiof-r8a7744 # RZ/G1N
+ - renesas,msiof-r8a7745 # RZ/G1E
+ - renesas,msiof-r8a77470 # RZ/G1C
+ - renesas,msiof-r8a7790 # R-Car H2
+ - renesas,msiof-r8a7791 # R-Car M2-W
+ - renesas,msiof-r8a7792 # R-Car V2H
+ - renesas,msiof-r8a7793 # R-Car M2-N
+ - renesas,msiof-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-msiof # generic R-Car Gen2 and RZ/G1
+ # compatible device
+ - items:
+ - enum:
+ - renesas,msiof-r8a774a1 # RZ/G2M
+ - renesas,msiof-r8a774b1 # RZ/G2N
+ - renesas,msiof-r8a774c0 # RZ/G2E
+ - renesas,msiof-r8a7795 # R-Car H3
+ - renesas,msiof-r8a7796 # R-Car M3-W
+ - renesas,msiof-r8a77965 # R-Car M3-N
+ - renesas,msiof-r8a77970 # R-Car V3M
+ - renesas,msiof-r8a77980 # R-Car V3H
+ - renesas,msiof-r8a77990 # R-Car E3
+ - renesas,msiof-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2
+ # compatible device
+ - items:
+ - const: renesas,sh-msiof # deprecated
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ oneOf:
+ - items:
+ - description: CPU and DMA engine registers
+ - items:
+ - description: CPU registers
+ - description: DMA engine registers
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ num-cs:
+ description: |
+ Total number of chip selects (default is 1).
+ Up to 3 native chip selects are supported:
+ 0: MSIOF_SYNC
+ 1: MSIOF_SS1
+ 2: MSIOF_SS2
+ Hardware limitations related to chip selects:
+ - Native chip selects are always deasserted in between transfers
+ that are part of the same message. Use cs-gpios to work around
+ this.
+ - All slaves using native chip selects must use the same spi-cs-high
+ configuration. Use cs-gpios to work around this.
+ - When using GPIO chip selects, at least one native chip select must
+ be left unused, as it will be driven anyway.
+ minimum: 1
+ maximum: 3
+ default: 1
+
+ dmas:
+ minItems: 2
+ maxItems: 4
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum: [ tx, rx ]
+
+ renesas,dtdl:
+ description: delay sync signal (setup) in transmit mode.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum:
+ - 0 # no bit delay
+ - 50 # 0.5-clock-cycle delay
+ - 100 # 1-clock-cycle delay
+ - 150 # 1.5-clock-cycle delay
+ - 200 # 2-clock-cycle delay
+
+ renesas,syncdl:
+ description: delay sync signal (hold) in transmit mode
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum:
+ - 0 # no bit delay
+ - 50 # 0.5-clock-cycle delay
+ - 100 # 1-clock-cycle delay
+ - 150 # 1.5-clock-cycle delay
+ - 200 # 2-clock-cycle delay
+ - 300 # 3-clock-cycle delay
+
+ renesas,tx-fifo-size:
+ # deprecated for soctype-specific bindings
+ description: |
+ Override the default TX fifo size. Unit is words. Ignored if 0.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ default: 64
+
+ renesas,rx-fifo-size:
+ # deprecated for soctype-specific bindings
+ description: |
+ Override the default RX fifo size. Unit is words. Ignored if 0.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ default: 64
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/spi/sh-hspi.txt b/dts/Bindings/spi/sh-hspi.txt
deleted file mode 100644
index b9d1e4d11a..0000000000
--- a/dts/Bindings/spi/sh-hspi.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Renesas HSPI.
-
-Required properties:
-- compatible : "renesas,hspi-<soctype>", "renesas,hspi" as fallback.
- Examples with soctypes are:
- - "renesas,hspi-r8a7778" (R-Car M1)
- - "renesas,hspi-r8a7779" (R-Car H1)
-- reg : Offset and length of the register set for the device
-- interrupts : Interrupt specifier
-- #address-cells : Must be <1>
-- #size-cells : Must be <0>
-
-Pinctrl properties might be needed, too. See
-Documentation/devicetree/bindings/pinctrl/renesas,*.
-
-Example:
-
- hspi0: spi@fffc7000 {
- compatible = "renesas,hspi-r8a7778", "renesas,hspi";
- reg = <0xfffc7000 0x18>;
- interrupt-parent = <&gic>;
- interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt
deleted file mode 100644
index 18e14ee257..0000000000
--- a/dts/Bindings/spi/sh-msiof.txt
+++ /dev/null
@@ -1,105 +0,0 @@
-Renesas MSIOF spi controller
-
-Required properties:
-- compatible : "renesas,msiof-r8a7743" (RZ/G1M)
- "renesas,msiof-r8a7744" (RZ/G1N)
- "renesas,msiof-r8a7745" (RZ/G1E)
- "renesas,msiof-r8a77470" (RZ/G1C)
- "renesas,msiof-r8a774a1" (RZ/G2M)
- "renesas,msiof-r8a774c0" (RZ/G2E)
- "renesas,msiof-r8a7790" (R-Car H2)
- "renesas,msiof-r8a7791" (R-Car M2-W)
- "renesas,msiof-r8a7792" (R-Car V2H)
- "renesas,msiof-r8a7793" (R-Car M2-N)
- "renesas,msiof-r8a7794" (R-Car E2)
- "renesas,msiof-r8a7795" (R-Car H3)
- "renesas,msiof-r8a7796" (R-Car M3-W)
- "renesas,msiof-r8a77965" (R-Car M3-N)
- "renesas,msiof-r8a77970" (R-Car V3M)
- "renesas,msiof-r8a77980" (R-Car V3H)
- "renesas,msiof-r8a77990" (R-Car E3)
- "renesas,msiof-r8a77995" (R-Car D3)
- "renesas,msiof-sh73a0" (SH-Mobile AG5)
- "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
- "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
- "renesas,rcar-gen3-msiof" (generic R-Car Gen3 and RZ/G2 compatible device)
- "renesas,sh-msiof" (deprecated)
-
- When compatible with the generic version, nodes
- must list the SoC-specific version corresponding
- to the platform first followed by the generic
- version.
-
-- reg : A list of offsets and lengths of the register sets for
- the device.
- If only one register set is present, it is to be used
- by both the CPU and the DMA engine.
- If two register sets are present, the first is to be
- used by the CPU, and the second is to be used by the
- DMA engine.
-- interrupts : Interrupt specifier
-- #address-cells : Must be <1>
-- #size-cells : Must be <0>
-
-Optional properties:
-- clocks : Must contain a reference to the functional clock.
-- num-cs : Total number of chip selects (default is 1).
- Up to 3 native chip selects are supported:
- 0: MSIOF_SYNC
- 1: MSIOF_SS1
- 2: MSIOF_SS2
- Hardware limitations related to chip selects:
- - Native chip selects are always deasserted in
- between transfers that are part of the same
- message. Use cs-gpios to work around this.
- - All slaves using native chip selects must use the
- same spi-cs-high configuration. Use cs-gpios to
- work around this.
- - When using GPIO chip selects, at least one native
- chip select must be left unused, as it will be
- driven anyway.
-- dmas : Must contain a list of two references to DMA
- specifiers, one for transmission, and one for
- reception.
-- dma-names : Must contain a list of two DMA names, "tx" and "rx".
-- spi-slave : Empty property indicating the SPI controller is used
- in slave mode.
-- renesas,dtdl : delay sync signal (setup) in transmit mode.
- Must contain one of the following values:
- 0 (no bit delay)
- 50 (0.5-clock-cycle delay)
- 100 (1-clock-cycle delay)
- 150 (1.5-clock-cycle delay)
- 200 (2-clock-cycle delay)
-
-- renesas,syncdl : delay sync signal (hold) in transmit mode.
- Must contain one of the following values:
- 0 (no bit delay)
- 50 (0.5-clock-cycle delay)
- 100 (1-clock-cycle delay)
- 150 (1.5-clock-cycle delay)
- 200 (2-clock-cycle delay)
- 300 (3-clock-cycle delay)
-
-Optional properties, deprecated for soctype-specific bindings:
-- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
- (default is 64)
-- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
- (default is 64)
-
-Pinctrl properties might be needed, too. See
-Documentation/devicetree/bindings/pinctrl/renesas,*.
-
-Example:
-
- msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
- interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
- dmas = <&dmac0 0x51>, <&dmac0 0x52>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- };
diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.txt b/dts/Bindings/spi/snps,dw-apb-ssi.txt
index f54c8c3639..3ed08ee9fe 100644
--- a/dts/Bindings/spi/snps,dw-apb-ssi.txt
+++ b/dts/Bindings/spi/snps,dw-apb-ssi.txt
@@ -16,7 +16,8 @@ Required properties:
Optional properties:
- clock-names : Contains the names of the clocks:
"ssi_clk", for the core clock used to generate the external SPI clock.
- "pclk", the interface clock, required for register access.
+ "pclk", the interface clock, required for register access. If a clock domain
+ used to enable this clock then it should be named "pclk_clkdomain".
- cs-gpios : Specifies the gpio pins to be used for chipselects.
- num-cs : The number of chipselects. If omitted, this will default to 4.
- reg-io-width : The I/O register width (in bytes) implemented by this
diff --git a/dts/Bindings/spi/spi-sifive.txt b/dts/Bindings/spi/spi-sifive.txt
deleted file mode 100644
index 3f5c6e4389..0000000000
--- a/dts/Bindings/spi/spi-sifive.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-SiFive SPI controller Device Tree Bindings
-------------------------------------------
-
-Required properties:
-- compatible : Should be "sifive,<chip>-spi" and "sifive,spi<version>".
- Supported compatible strings are:
- "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
- onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
- SPI v0 IP block with no chip integration tweaks.
- Please refer to sifive-blocks-ip-versioning.txt for details
-- reg : Physical base address and size of SPI registers map
- A second (optional) range can indicate memory mapped flash
-- interrupts : Must contain one entry
-- interrupt-parent : Must be core interrupt controller
-- clocks : Must reference the frequency given to the controller
-- #address-cells : Must be '1', indicating which CS to use
-- #size-cells : Must be '0'
-
-Optional properties:
-- sifive,fifo-depth : Depth of hardware queues; defaults to 8
-- sifive,max-bits-per-word : Maximum bits per word; defaults to 8
-
-SPI RTL that corresponds to the IP block version numbers can be found here:
-https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
-
-Example:
- spi: spi@10040000 {
- compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
- interrupt-parent = <&plic>;
- interrupts = <51>;
- clocks = <&tlclk>;
- #address-cells = <1>;
- #size-cells = <0>;
- sifive,fifo-depth = <8>;
- sifive,max-bits-per-word = <8>;
- };
diff --git a/dts/Bindings/spi/spi-sifive.yaml b/dts/Bindings/spi/spi-sifive.yaml
new file mode 100644
index 0000000000..140e4351a1
--- /dev/null
+++ b/dts/Bindings/spi/spi-sifive.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive SPI controller
+
+maintainers:
+ - Pragnesh Patel <pragnesh.patel@sifive.com>
+ - Paul Walmsley <paul.walmsley@sifive.com>
+ - Palmer Dabbelt <palmer@sifive.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ items:
+ - const: sifive,fu540-c000-spi
+ - const: sifive,spi0
+
+ description:
+ Should be "sifive,<chip>-spi" and "sifive,spi<version>".
+ Supported compatible strings are -
+ "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
+ onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
+ SPI v0 IP block with no chip integration tweaks.
+ Please refer to sifive-blocks-ip-versioning.txt for details
+
+ SPI RTL that corresponds to the IP block version numbers can be found here -
+ https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
+
+ reg:
+ maxItems: 1
+
+ description:
+ Physical base address and size of SPI registers map
+ A second (optional) range can indicate memory mapped flash
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ description:
+ Must reference the frequency given to the controller
+
+ sifive,fifo-depth:
+ description:
+ Depth of hardware queues; defaults to 8
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - enum: [ 8 ]
+ - default: 8
+
+ sifive,max-bits-per-word:
+ description:
+ Maximum bits per word; defaults to 8
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8 ]
+ - default: 8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ spi: spi@10040000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic>;
+ interrupts = <51>;
+ clocks = <&tlclk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sifive,fifo-depth = <8>;
+ sifive,max-bits-per-word = <8>;
+ };
+
+...
diff --git a/dts/Bindings/spi/spi-stm32-qspi.txt b/dts/Bindings/spi/spi-stm32-qspi.txt
deleted file mode 100644
index bfc038b947..0000000000
--- a/dts/Bindings/spi/spi-stm32-qspi.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* STMicroelectronics Quad Serial Peripheral Interface(QSPI)
-
-Required properties:
-- compatible: should be "st,stm32f469-qspi"
-- reg: the first contains the register location and length.
- the second contains the memory mapping address and length
-- reg-names: should contain the reg names "qspi" "qspi_mm"
-- interrupts: should contain the interrupt for the device
-- clocks: the phandle of the clock needed by the QSPI controller
-- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
-
-Optional properties:
-- resets: must contain the phandle to the reset controller.
-
-A spi flash (NOR/NAND) must be a child of spi node and could have some
-properties. Also see jedec,spi-nor.txt.
-
-Required properties:
-- reg: chip-Select number (QSPI controller may connect 2 flashes)
-- spi-max-frequency: max frequency of spi bus
-
-Optional properties:
-- spi-rx-bus-width: see ./spi-bus.txt for the description
-- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
-Documentation/devicetree/bindings/dma/dma.txt.
-- dma-names: DMA request names should include "tx" and "rx" if present.
-
-Example:
-
-qspi: spi@a0001000 {
- compatible = "st,stm32f469-qspi";
- reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
- reg-names = "qspi", "qspi_mm";
- interrupts = <91>;
- resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
- clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi0>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- ...
- };
-};
diff --git a/dts/Bindings/spi/spi-xilinx.txt b/dts/Bindings/spi/spi-xilinx.txt
index dc924a5f71..5f4ed3e5c9 100644
--- a/dts/Bindings/spi/spi-xilinx.txt
+++ b/dts/Bindings/spi/spi-xilinx.txt
@@ -8,7 +8,8 @@ Required properties:
number.
Optional properties:
-- xlnx,num-ss-bits : Number of chip selects used.
+- xlnx,num-ss-bits : Number of chip selects used.
+- xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified
Example:
axi_quad_spi@41e00000 {
@@ -17,5 +18,6 @@ Example:
interrupts = <0 31 1>;
reg = <0x41e00000 0x10000>;
xlnx,num-ss-bits = <0x1>;
+ xlnx,num-transfer-bits = <32>;
};
diff --git a/dts/Bindings/spi/st,stm32-qspi.yaml b/dts/Bindings/spi/st,stm32-qspi.yaml
new file mode 100644
index 0000000000..3665a5fe6b
--- /dev/null
+++ b/dts/Bindings/spi/st,stm32-qspi.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings
+
+maintainers:
+ - Christophe Kerello <christophe.kerello@st.com>
+ - Patrice Chotard <patrice.chotard@st.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ const: st,stm32f469-qspi
+
+ reg:
+ items:
+ - description: registers
+ - description: memory mapping
+
+ reg-names:
+ items:
+ - const: qspi
+ - const: qspi_mm
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: tx DMA channel
+ - description: rx DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ spi@58003000 {
+ compatible = "st,stm32f469-qspi";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
+ <&mdma1 22 0x10 0x100008 0x0 0x0>;
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+ };
+
+...