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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:33:55 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:40 +0100 |
commit | 940968e2208b97d74e18b082500f35e463bcece5 (patch) | |
tree | 206eb7f6adcd584407f48057a475cb8f4c4f64ff /dts/Bindings/spi | |
parent | a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (diff) | |
download | barebox-940968e2208b97d74e18b082500f35e463bcece5.tar.gz barebox-940968e2208b97d74e18b082500f35e463bcece5.tar.xz |
dts: update to v4.3-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/spi')
-rw-r--r-- | dts/Bindings/spi/spi-mt65xx.txt | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/dts/Bindings/spi/spi-mt65xx.txt b/dts/Bindings/spi/spi-mt65xx.txt index dcefc43827..6160ffbcb3 100644 --- a/dts/Bindings/spi/spi-mt65xx.txt +++ b/dts/Bindings/spi/spi-mt65xx.txt @@ -15,17 +15,18 @@ Required properties: - interrupts: Should contain spi interrupt - clocks: phandles to input clocks. - The first should be <&topckgen CLK_TOP_SPI_SEL>. - The second should be one of the following. + The first should be one of the following. It's PLL. - <&clk26m>: specify parent clock 26MHZ. - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ. It's the default one. - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ. - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. + The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux. + The third is <&pericfg CLK_PERI_SPI0>. It's clock gate. -- clock-names: shall be "spi-clk" for the controller clock, and - "parent-clk" for the parent clock. +- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the + muxes clock, and "spi-clk" for the clock gate. Optional properties: - mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi @@ -44,8 +45,11 @@ spi: spi@1100a000 { #size-cells = <0>; reg = <0 0x1100a000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SYSPLL3_D2>; - clock-names = "spi-clk", "parent-clk"; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + mediatek,pad-select = <0>; status = "disabled"; }; |