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authorSascha Hauer <s.hauer@pengutronix.de>2020-06-23 12:14:59 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2020-07-05 20:49:06 +0200
commitabef60363d8ecac66e45853f328afa8eeb9e00fd (patch)
treec7d6f1dcf0ef5154b9182da86f1acad048cb7da1 /dts/Bindings/spi
parente307bc559a2830b7f695150212ea1b26cdca69fb (diff)
downloadbarebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.gz
barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.xz
dts: update to v5.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/spi')
-rw-r--r--dts/Bindings/spi/brcm,spi-bcm-qspi.txt10
-rw-r--r--dts/Bindings/spi/marvell,mmp2-ssp.yaml58
-rw-r--r--dts/Bindings/spi/mikrotik,rb4xx-spi.yaml36
-rw-r--r--dts/Bindings/spi/qcom,spi-qcom-qspi.yaml10
-rw-r--r--dts/Bindings/spi/renesas,hspi.yaml4
-rw-r--r--dts/Bindings/spi/renesas,rspi.yaml144
-rw-r--r--dts/Bindings/spi/renesas,sh-msiof.yaml44
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.txt41
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.yaml133
-rw-r--r--dts/Bindings/spi/socionext,uniphier-spi.yaml57
-rw-r--r--dts/Bindings/spi/spi-controller.yaml14
-rw-r--r--dts/Bindings/spi/spi-dw.txt24
-rw-r--r--dts/Bindings/spi/spi-pl022.yaml57
-rw-r--r--dts/Bindings/spi/spi-pxa2xx.txt27
-rw-r--r--dts/Bindings/spi/spi-rspi.txt73
-rw-r--r--dts/Bindings/spi/spi-sifive.yaml25
-rw-r--r--dts/Bindings/spi/spi-uniphier.txt28
-rw-r--r--dts/Bindings/spi/st,stm32-qspi.yaml4
-rw-r--r--dts/Bindings/spi/ti_qspi.txt2
19 files changed, 510 insertions, 281 deletions
diff --git a/dts/Bindings/spi/brcm,spi-bcm-qspi.txt b/dts/Bindings/spi/brcm,spi-bcm-qspi.txt
index ad7ac80a38..f5e518d099 100644
--- a/dts/Bindings/spi/brcm,spi-bcm-qspi.txt
+++ b/dts/Bindings/spi/brcm,spi-bcm-qspi.txt
@@ -26,6 +26,16 @@ Required properties:
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
BRCMSTB SoCs
+ "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
"brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP
"brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs
diff --git a/dts/Bindings/spi/marvell,mmp2-ssp.yaml b/dts/Bindings/spi/marvell,mmp2-ssp.yaml
new file mode 100644
index 0000000000..0abcac385e
--- /dev/null
+++ b/dts/Bindings/spi/marvell,mmp2-ssp.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/marvell,mmp2-ssp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PXA2xx SSP SPI Controller bindings
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ const: marvell,mmp2-ssp
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ ready-gpios:
+ description: |
+ GPIO used to signal a SPI master that the FIFO is filled and we're
+ ready to service a transfer. Only useful in slave mode.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+dependencies:
+ ready-gpios: [ spi-slave ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/marvell,mmp2.h>
+ spi@d4035000 {
+ compatible = "marvell,mmp2-ssp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xd4035000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP0>;
+ interrupts = <0>;
+ };
+
+...
diff --git a/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml b/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml
new file mode 100644
index 0000000000..4ddb42a4ae
--- /dev/null
+++ b/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/mikrotik,rb4xx-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MikroTik RB4xx series SPI master
+
+maintainers:
+ - Gabor Juhos <juhosg@openwrt.org>
+ - Bert Vermeulen <bert@biot.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ const: mikrotik,rb4xx-spi
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ spi: spi@1f000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mikrotik,rb4xx-spi";
+ reg = <0x1f000000 0x10>;
+ };
+
+... \ No newline at end of file
diff --git a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml
index 5c16cf59ca..0178831b06 100644
--- a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml
+++ b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml
@@ -8,12 +8,12 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Quad Serial Peripheral Interface (QSPI)
maintainers:
- - Mukesh Savaliya <msavaliy@codeaurora.org>
- - Akash Asthana <akashast@codeaurora.org>
+ - Mukesh Savaliya <msavaliy@codeaurora.org>
+ - Akash Asthana <akashast@codeaurora.org>
-description:
- The QSPI controller allows SPI protocol communication in single, dual, or quad
- wire transmission modes for read/write access to slaves such as NOR flash.
+description: The QSPI controller allows SPI protocol communication in single,
+ dual, or quad wire transmission modes for read/write access to slaves such
+ as NOR flash.
allOf:
- $ref: /spi/spi-controller.yaml#
diff --git a/dts/Bindings/spi/renesas,hspi.yaml b/dts/Bindings/spi/renesas,hspi.yaml
index c429cf4bea..f492cb9fea 100644
--- a/dts/Bindings/spi/renesas,hspi.yaml
+++ b/dts/Bindings/spi/renesas,hspi.yaml
@@ -16,8 +16,8 @@ properties:
compatible:
items:
- enum:
- - renesas,hspi-r8a7778 # R-Car M1A
- - renesas,hspi-r8a7779 # R-Car H1
+ - renesas,hspi-r8a7778 # R-Car M1A
+ - renesas,hspi-r8a7779 # R-Car H1
- const: renesas,hspi
reg:
diff --git a/dts/Bindings/spi/renesas,rspi.yaml b/dts/Bindings/spi/renesas,rspi.yaml
new file mode 100644
index 0000000000..c54ac05904
--- /dev/null
+++ b/dts/Bindings/spi/renesas,rspi.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/renesas,rspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,rspi-sh7757 # SH7757
+ - const: renesas,rspi # Legacy SH
+
+ - items:
+ - enum:
+ - renesas,rspi-r7s72100 # RZ/A1H
+ - renesas,rspi-r7s9210 # RZ/A2
+ - const: renesas,rspi-rz # RZ/A
+
+ - items:
+ - enum:
+ - renesas,qspi-r8a7743 # RZ/G1M
+ - renesas,qspi-r8a7744 # RZ/G1N
+ - renesas,qspi-r8a7745 # RZ/G1E
+ - renesas,qspi-r8a77470 # RZ/G1C
+ - renesas,qspi-r8a7790 # R-Car H2
+ - renesas,qspi-r8a7791 # R-Car M2-W
+ - renesas,qspi-r8a7792 # R-Car V2H
+ - renesas,qspi-r8a7793 # R-Car M2-N
+ - renesas,qspi-r8a7794 # R-Car E2
+ - const: renesas,qspi # R-Car Gen2 and RZ/G1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ oneOf:
+ - items:
+ - description: A combined interrupt
+ - items:
+ - description: Error interrupt (SPEI)
+ - description: Receive Interrupt (SPRI)
+ - description: Transmit Interrupt (SPTI)
+
+ interrupt-names:
+ oneOf:
+ - items:
+ - const: mux
+ - items:
+ - const: error
+ - const: rx
+ - const: tx
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+ num-cs:
+ description: |
+ Total number of native chip selects.
+ Hardware limitations related to chip selects:
+ - When using GPIO chip selects, at least one native chip select must
+ be left unused, as it will be driven anyway.
+ minimum: 1
+ maximum: 2
+ default: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rspi-rz
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ required:
+ - interrupt-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,qspi
+ then:
+ required:
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+ reg = <0xe6b10000 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/spi/renesas,sh-msiof.yaml b/dts/Bindings/spi/renesas,sh-msiof.yaml
index b6c1dd2a9c..e84edcf8b3 100644
--- a/dts/Bindings/spi/renesas,sh-msiof.yaml
+++ b/dts/Bindings/spi/renesas,sh-msiof.yaml
@@ -96,43 +96,39 @@ properties:
renesas,dtdl:
description: delay sync signal (setup) in transmit mode.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum:
- - 0 # no bit delay
- - 50 # 0.5-clock-cycle delay
- - 100 # 1-clock-cycle delay
- - 150 # 1.5-clock-cycle delay
- - 200 # 2-clock-cycle delay
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # no bit delay
+ - 50 # 0.5-clock-cycle delay
+ - 100 # 1-clock-cycle delay
+ - 150 # 1.5-clock-cycle delay
+ - 200 # 2-clock-cycle delay
renesas,syncdl:
description: delay sync signal (hold) in transmit mode
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum:
- - 0 # no bit delay
- - 50 # 0.5-clock-cycle delay
- - 100 # 1-clock-cycle delay
- - 150 # 1.5-clock-cycle delay
- - 200 # 2-clock-cycle delay
- - 300 # 3-clock-cycle delay
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # no bit delay
+ - 50 # 0.5-clock-cycle delay
+ - 100 # 1-clock-cycle delay
+ - 150 # 1.5-clock-cycle delay
+ - 200 # 2-clock-cycle delay
+ - 300 # 3-clock-cycle delay
renesas,tx-fifo-size:
# deprecated for soctype-specific bindings
description: |
Override the default TX fifo size. Unit is words. Ignored if 0.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
default: 64
renesas,rx-fifo-size:
# deprecated for soctype-specific bindings
description: |
Override the default RX fifo size. Unit is words. Ignored if 0.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
default: 64
required:
@@ -149,7 +145,7 @@ examples:
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
+ reg = <0xe6e20000 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.txt b/dts/Bindings/spi/snps,dw-apb-ssi.txt
deleted file mode 100644
index 3ed08ee9fe..0000000000
--- a/dts/Bindings/spi/snps,dw-apb-ssi.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
-
-Required properties:
-- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi"
-- reg : The register base for the controller. For "mscc,<soc>-spi", a second
- register set is required (named ICPU_CFG:SPI_MST)
-- interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
-- clocks : phandles for the clocks, see the description of clock-names below.
- The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
- is optional. If a single clock is specified but no clock-name, it is the
- "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
-
-Optional properties:
-- clock-names : Contains the names of the clocks:
- "ssi_clk", for the core clock used to generate the external SPI clock.
- "pclk", the interface clock, required for register access. If a clock domain
- used to enable this clock then it should be named "pclk_clkdomain".
-- cs-gpios : Specifies the gpio pins to be used for chipselects.
-- num-cs : The number of chipselects. If omitted, this will default to 4.
-- reg-io-width : The I/O register width (in bytes) implemented by this
- device. Supported values are 2 or 4 (the default).
-
-Child nodes as per the generic SPI binding.
-
-Example:
-
- spi@fff00000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0xfff00000 0x1000>;
- interrupts = <0 154 4>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&spi_m_clk>;
- num-cs = <2>;
- cs-gpios = <&gpio0 13 0>,
- <&gpio0 14 0>;
- };
-
diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/Bindings/spi/snps,dw-apb-ssi.yaml
new file mode 100644
index 0000000000..c62cbe79f0
--- /dev/null
+++ b/dts/Bindings/spi/snps,dw-apb-ssi.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
+
+maintainers:
+ - Mark Brown <broonie@kernel.org>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ then:
+ properties:
+ reg:
+ minItems: 2
+
+properties:
+ compatible:
+ oneOf:
+ - description: Generic DW SPI Controller
+ enum:
+ - snps,dw-apb-ssi
+ - snps,dwc-ssi-1.01a
+ - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
+ items:
+ - enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ - const: snps,dw-apb-ssi
+ - description: Amazon Alpine SPI Controller
+ const: amazon,alpine-dw-apb-ssi
+ - description: Renesas RZ/N1 SPI Controller
+ items:
+ - const: renesas,rzn1-spi
+ - const: snps,dw-apb-ssi
+ - description: Intel Keem Bay SPI Controller
+ const: intel,keembay-ssi
+
+ reg:
+ minItems: 1
+ items:
+ - description: DW APB SSI controller memory mapped registers
+ - description: SPI MST region map
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: SPI Controller reference clock source
+ - description: APB interface clock source
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ssi_clk
+ - const: pclk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: spi
+
+ reg-io-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: I/O register width (in bytes) implemented by this device
+ default: 4
+ enum: [ 2, 4 ]
+
+ num-cs:
+ default: 4
+ minimum: 1
+ maximum: 4
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 1
+
+ spi-tx-bus-width:
+ const: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ spi@fff00000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xfff00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 154 4>;
+ clocks = <&spi_m_clk>;
+ num-cs = <2>;
+ cs-gpios = <&gpio0 13 0>,
+ <&gpio0 14 0>;
+ };
+...
diff --git a/dts/Bindings/spi/socionext,uniphier-spi.yaml b/dts/Bindings/spi/socionext,uniphier-spi.yaml
new file mode 100644
index 0000000000..c25409298b
--- /dev/null
+++ b/dts/Bindings/spi/socionext,uniphier-spi.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/socionext,uniphier-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SPI controller
+
+description: |
+ UniPhier SoCs have SCSSI which supports SPI single channel.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ - Keiji Hayashibara <hayashibara.keiji@socionext.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ "#address-cells": true
+ "#size-cells": true
+
+ compatible:
+ const: socionext,uniphier-scssi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 39 4>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
diff --git a/dts/Bindings/spi/spi-controller.yaml b/dts/Bindings/spi/spi-controller.yaml
index d8e5509a70..c6a2f54364 100644
--- a/dts/Bindings/spi/spi-controller.yaml
+++ b/dts/Bindings/spi/spi-controller.yaml
@@ -115,24 +115,22 @@ patternProperties:
Maximum SPI clocking speed of the device in Hz.
spi-rx-bus-width:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [ 1, 2, 4, 8 ]
- - default: 1
description:
Bus width to the SPI bus used for read transfers.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8]
+ default: 1
spi-rx-delay-us:
description:
Delay, in microseconds, after a read transfer.
spi-tx-bus-width:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [ 1, 2, 4, 8 ]
- - default: 1
description:
Bus width to the SPI bus used for write transfers.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8]
+ default: 1
spi-tx-delay-us:
description:
diff --git a/dts/Bindings/spi/spi-dw.txt b/dts/Bindings/spi/spi-dw.txt
deleted file mode 100644
index 7b63ed6019..0000000000
--- a/dts/Bindings/spi/spi-dw.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Synopsys DesignWare SPI master
-
-Required properties:
-- compatible: should be "snps,designware-spi"
-- #address-cells: see spi-bus.txt
-- #size-cells: see spi-bus.txt
-- reg: address and length of the spi master registers
-- interrupts: should contain one interrupt
-- clocks: spi clock phandle
-- num-cs: see spi-bus.txt
-
-Optional properties:
-- cs-gpios: see spi-bus.txt
-
-Example:
-
-spi: spi@4020a000 {
- compatible = "snps,designware-spi";
- interrupts = <11 1>;
- reg = <0x4020a000 0x1000>;
- clocks = <&pclk>;
- num-cs = <2>;
- cs-gpios = <&banka 0 0>;
-};
diff --git a/dts/Bindings/spi/spi-pl022.yaml b/dts/Bindings/spi/spi-pl022.yaml
index dfb697c693..2299902447 100644
--- a/dts/Bindings/spi/spi-pl022.yaml
+++ b/dts/Bindings/spi/spi-pl022.yaml
@@ -51,7 +51,7 @@ properties:
pl022,rt:
description: indicates the controller should run the message pump with realtime
- priority to minimise the transfer latency on the bus (boolean)
+ priority to minimise the transfer latency on the bus (boolean)
type: boolean
dmas:
@@ -80,55 +80,48 @@ patternProperties:
properties:
pl022,interface:
description: SPI interface type
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - enum:
- - 0 # SPI
- - 1 # Texas Instruments Synchronous Serial Frame Format
- - 2 # Microwire (Half Duplex)
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum:
+ - 0 # SPI
+ - 1 # Texas Instruments Synchronous Serial Frame Format
+ - 2 # Microwire (Half Duplex)
pl022,com-mode:
description: Specifies the transfer mode
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - enum:
- - 0 # interrupt mode
- - 1 # polling mode
- - 2 # DMA mode
- default: 1
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum:
+ - 0 # interrupt mode
+ - 1 # polling mode
+ - 2 # DMA mode
+ default: 1
pl022,rx-level-trig:
description: Rx FIFO watermark level
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- maximum: 4
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 4
pl022,tx-level-trig:
description: Tx FIFO watermark level
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- maximum: 4
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 4
pl022,ctrl-len:
description: Microwire interface - Control length
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0x03
- maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0x03
+ maximum: 0x1f
pl022,wait-state:
description: Microwire interface - Wait state
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - enum: [ 0, 1 ]
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [0, 1]
pl022,duplex:
description: Microwire interface - Full/Half duplex
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - enum: [ 0, 1 ]
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [0, 1]
required:
- compatible
diff --git a/dts/Bindings/spi/spi-pxa2xx.txt b/dts/Bindings/spi/spi-pxa2xx.txt
deleted file mode 100644
index e30e0c2a4b..0000000000
--- a/dts/Bindings/spi/spi-pxa2xx.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-PXA2xx SSP SPI Controller
-
-Required properties:
-- compatible: Must be "marvell,mmp2-ssp".
-- reg: Offset and length of the device's register set.
-- interrupts: Should be the interrupt number.
-- clocks: Should contain a single entry describing the clock input.
-- #address-cells: Number of cells required to define a chip select address.
-- #size-cells: Should be zero.
-
-Optional properties:
-- cs-gpios: list of GPIO chip selects. See the SPI bus bindings,
- Documentation/devicetree/bindings/spi/spi-bus.txt
-- spi-slave: Empty property indicating the SPI controller is used in slave mode.
-- ready-gpios: GPIO used to signal a SPI master that the FIFO is filled
- and we're ready to service a transfer. Only useful in slave mode.
-
-Child nodes represent devices on the SPI bus
- See ../spi/spi-bus.txt
-
-Example:
- ssp1: spi@d4035000 {
- compatible = "marvell,mmp2-ssp";
- reg = <0xd4035000 0x1000>;
- clocks = <&soc_clocks MMP2_CLK_SSP0>;
- interrupts = <0>;
- };
diff --git a/dts/Bindings/spi/spi-rspi.txt b/dts/Bindings/spi/spi-rspi.txt
deleted file mode 100644
index 421722b939..0000000000
--- a/dts/Bindings/spi/spi-rspi.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-Device tree configuration for Renesas RSPI/QSPI driver
-
-Required properties:
-- compatible : For Renesas Serial Peripheral Interface on legacy SH:
- "renesas,rspi-<soctype>", "renesas,rspi" as fallback.
- For Renesas Serial Peripheral Interface on RZ/A:
- "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
- For Quad Serial Peripheral Interface on R-Car Gen2 and
- RZ/G1 devices:
- "renesas,qspi-<soctype>", "renesas,qspi" as fallback.
- Examples with soctypes are:
- - "renesas,rspi-sh7757" (SH)
- - "renesas,rspi-r7s72100" (RZ/A1H)
- - "renesas,rspi-r7s9210" (RZ/A2)
- - "renesas,qspi-r8a7743" (RZ/G1M)
- - "renesas,qspi-r8a7744" (RZ/G1N)
- - "renesas,qspi-r8a7745" (RZ/G1E)
- - "renesas,qspi-r8a77470" (RZ/G1C)
- - "renesas,qspi-r8a7790" (R-Car H2)
- - "renesas,qspi-r8a7791" (R-Car M2-W)
- - "renesas,qspi-r8a7792" (R-Car V2H)
- - "renesas,qspi-r8a7793" (R-Car M2-N)
- - "renesas,qspi-r8a7794" (R-Car E2)
-- reg : Address start and address range size of the device
-- interrupts : A list of interrupt-specifiers, one for each entry in
- interrupt-names.
- If interrupt-names is not present, an interrupt specifier
- for a single muxed interrupt.
-- interrupt-names : A list of interrupt names. Should contain (if present):
- - "error" for SPEI,
- - "rx" for SPRI,
- - "tx" to SPTI,
- - "mux" for a single muxed interrupt.
-- num-cs : Number of chip selects. Some RSPI cores have more than 1.
-- #address-cells : Must be <1>
-- #size-cells : Must be <0>
-
-Optional properties:
-- clocks : Must contain a reference to the functional clock.
-- dmas : Must contain a list of two references to DMA specifiers,
- one for transmission, and one for reception.
-- dma-names : Must contain a list of two DMA names, "tx" and "rx".
-
-Pinctrl properties might be needed, too. See
-Documentation/devicetree/bindings/pinctrl/renesas,*.
-
-Examples:
-
- spi0: spi@e800c800 {
- compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
- reg = <0xe800c800 0x24>;
- interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
- <0 239 IRQ_TYPE_LEVEL_HIGH>,
- <0 240 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error", "rx", "tx";
- interrupt-parent = <&gic>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7791", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupt-parent = <&gic>;
- interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>;
- dma-names = "tx", "rx";
- };
diff --git a/dts/Bindings/spi/spi-sifive.yaml b/dts/Bindings/spi/spi-sifive.yaml
index 140e4351a1..4932205d1c 100644
--- a/dts/Bindings/spi/spi-sifive.yaml
+++ b/dts/Bindings/spi/spi-sifive.yaml
@@ -32,11 +32,10 @@ properties:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
reg:
- maxItems: 1
-
- description:
- Physical base address and size of SPI registers map
- A second (optional) range can indicate memory mapped flash
+ minItems: 1
+ items:
+ - description: SPI registers region
+ - description: Memory mapped flash region
interrupts:
maxItems: 1
@@ -50,18 +49,16 @@ properties:
sifive,fifo-depth:
description:
Depth of hardware queues; defaults to 8
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - enum: [ 8 ]
- - default: 8
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [8]
+ default: 8
sifive,max-bits-per-word:
description:
Maximum bits per word; defaults to 8
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8 ]
- - default: 8
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
+ default: 8
required:
- compatible
@@ -73,7 +70,7 @@ examples:
- |
spi: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
+ reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
interrupt-parent = <&plic>;
interrupts = <51>;
clocks = <&tlclk>;
diff --git a/dts/Bindings/spi/spi-uniphier.txt b/dts/Bindings/spi/spi-uniphier.txt
deleted file mode 100644
index e1201573a2..0000000000
--- a/dts/Bindings/spi/spi-uniphier.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Socionext UniPhier SPI controller driver
-
-UniPhier SoCs have SCSSI which supports SPI single channel.
-
-Required properties:
- - compatible: should be "socionext,uniphier-scssi"
- - reg: address and length of the spi master registers
- - #address-cells: must be <1>, see spi-bus.txt
- - #size-cells: must be <0>, see spi-bus.txt
- - interrupts: a single interrupt specifier
- - pinctrl-names: should be "default"
- - pinctrl-0: pin control state for the default mode
- - clocks: a phandle to the clock for the device
- - resets: a phandle to the reset control for the device
-
-Example:
-
-spi0: spi@54006000 {
- compatible = "socionext,uniphier-scssi";
- reg = <0x54006000 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 39 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&peri_clk 11>;
- resets = <&peri_rst 11>;
-};
diff --git a/dts/Bindings/spi/st,stm32-qspi.yaml b/dts/Bindings/spi/st,stm32-qspi.yaml
index 3665a5fe6b..1a342ce1f7 100644
--- a/dts/Bindings/spi/st,stm32-qspi.yaml
+++ b/dts/Bindings/spi/st,stm32-qspi.yaml
@@ -24,8 +24,8 @@ properties:
reg-names:
items:
- - const: qspi
- - const: qspi_mm
+ - const: qspi
+ - const: qspi_mm
clocks:
maxItems: 1
diff --git a/dts/Bindings/spi/ti_qspi.txt b/dts/Bindings/spi/ti_qspi.txt
index e65fde4a73..47b184bce4 100644
--- a/dts/Bindings/spi/ti_qspi.txt
+++ b/dts/Bindings/spi/ti_qspi.txt
@@ -29,7 +29,7 @@ modification to bootloader.
Example:
For am4372:
-qspi: qspi@4b300000 {
+qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";