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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-02-03 10:25:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-02-04 08:40:36 +0100 |
commit | 0ff58575c9d66f660886387c2e68d8c5c724e87b (patch) | |
tree | 4a889d1478da83ae46db96f5c049872cdb90eeb6 /dts/Bindings/sram/rockchip-smp-sram.txt | |
parent | a0da52f83c36a81984e0fca4b75d522b955df267 (diff) | |
download | barebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.gz barebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.xz |
dts: update to v4.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/sram/rockchip-smp-sram.txt')
-rw-r--r-- | dts/Bindings/sram/rockchip-smp-sram.txt | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/dts/Bindings/sram/rockchip-smp-sram.txt b/dts/Bindings/sram/rockchip-smp-sram.txt new file mode 100644 index 0000000000..800701ecff --- /dev/null +++ b/dts/Bindings/sram/rockchip-smp-sram.txt @@ -0,0 +1,30 @@ +Rockchip SRAM for smp bringup: +------------------------------ + +Rockchip's smp-capable SoCs use the first part of the sram for the bringup +of the cores. Once the core gets powered up it executes the code that is +residing at the very beginning of the sram. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Required sub-node properties: +- compatible : should be "rockchip,rk3066-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in Documentation/devicetree/bindings/sram/sram.txt + +Example: + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smp-sram@10080000 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x10080000 0x50>; + }; + }; |