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authorSascha Hauer <s.hauer@pengutronix.de>2019-06-05 00:06:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-06-11 09:11:11 +0200
commit796af3473b8222bcd89aa63e9886c355a6baf95d (patch)
treead357b2756bda409b46747faaaf57a0ffd003c9c /dts/Bindings/timer/allwinner,sun4i-timer.txt
parent649b9ebcf53d697277bcdb01334dbcd563a33aa8 (diff)
downloadbarebox-796af3473b8222bcd89aa63e9886c355a6baf95d.tar.gz
barebox-796af3473b8222bcd89aa63e9886c355a6baf95d.tar.xz
dts: update to v5.2-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/timer/allwinner,sun4i-timer.txt')
-rw-r--r--dts/Bindings/timer/allwinner,sun4i-timer.txt4
1 files changed, 3 insertions, 1 deletions
diff --git a/dts/Bindings/timer/allwinner,sun4i-timer.txt b/dts/Bindings/timer/allwinner,sun4i-timer.txt
index 5c2e23574c..3da9d515c0 100644
--- a/dts/Bindings/timer/allwinner,sun4i-timer.txt
+++ b/dts/Bindings/timer/allwinner,sun4i-timer.txt
@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
Required properties:
-- compatible : should be "allwinner,sun4i-a10-timer"
+- compatible : should be one of the following:
+ "allwinner,sun4i-a10-timer"
+ "allwinner,suniv-f1c100s-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupt of the first timer
- clocks: phandle to the source clock (usually a 24 MHz fixed clock)