summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/timer/socionext,milbeaut-timer.txt
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2019-04-05 14:51:50 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-04-08 10:16:55 +0200
commit1dc748b3b202cadf9b799874d9af8d441ee556bc (patch)
tree58fd3c90a40e2d0128b0c7f36d63d7fc126bb20d /dts/Bindings/timer/socionext,milbeaut-timer.txt
parent9688b49cd3bc0b61a019e8e1311236c9975a0777 (diff)
downloadbarebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.gz
dts: update to v5.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/timer/socionext,milbeaut-timer.txt')
-rw-r--r--dts/Bindings/timer/socionext,milbeaut-timer.txt17
1 files changed, 17 insertions, 0 deletions
diff --git a/dts/Bindings/timer/socionext,milbeaut-timer.txt b/dts/Bindings/timer/socionext,milbeaut-timer.txt
new file mode 100644
index 0000000..ac44c4b
--- /dev/null
+++ b/dts/Bindings/timer/socionext,milbeaut-timer.txt
@@ -0,0 +1,17 @@
+Milbeaut SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "socionext,milbeaut-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer.
+- clocks: phandle to the input clk.
+
+Example:
+
+timer {
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e000050 0x20>
+ interrupts = <0 91 4>;
+ clocks = <&clk 4>;
+};