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authorSascha Hauer <s.hauer@pengutronix.de>2018-09-11 08:26:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-09-11 17:23:13 +0200
commit35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch)
treedd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/Bindings/timer
parent625eea2765d94aee016cf25d9cabecde8eae0775 (diff)
downloadbarebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/timer')
-rw-r--r--dts/Bindings/timer/altr,timer-1.0.txt1
-rw-r--r--dts/Bindings/timer/fsl,gtm.txt1
-rw-r--r--dts/Bindings/timer/marvell,orion-timer.txt1
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt34
-rw-r--r--dts/Bindings/timer/snps,arc-timer.txt4
-rw-r--r--dts/Bindings/timer/st,spear-timer.txt2
-rw-r--r--dts/Bindings/timer/ti,c64x+timer64.txt1
-rw-r--r--dts/Bindings/timer/ti,davinci-timer.txt37
8 files changed, 57 insertions, 24 deletions
diff --git a/dts/Bindings/timer/altr,timer-1.0.txt b/dts/Bindings/timer/altr,timer-1.0.txt
index 904a584..e698e34 100644
--- a/dts/Bindings/timer/altr,timer-1.0.txt
+++ b/dts/Bindings/timer/altr,timer-1.0.txt
@@ -4,7 +4,6 @@ Required properties:
- compatible : should be "altr,timer-1.0"
- reg : Specifies base physical address and size of the registers.
-- interrupt-parent: phandle of the interrupt controller
- interrupts : Should contain the timer interrupt number
- clock-frequency : The frequency of the clock that drives the counter, in Hz.
diff --git a/dts/Bindings/timer/fsl,gtm.txt b/dts/Bindings/timer/fsl,gtm.txt
index 9a33efd..fc1c571 100644
--- a/dts/Bindings/timer/fsl,gtm.txt
+++ b/dts/Bindings/timer/fsl,gtm.txt
@@ -7,7 +7,6 @@ Required properties:
"fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
- reg : should contain gtm registers location and length (0x40).
- interrupts : should contain four interrupts.
- - interrupt-parent : interrupt source phandle.
- clock-frequency : specifies the frequency driving the timer.
Example:
diff --git a/dts/Bindings/timer/marvell,orion-timer.txt b/dts/Bindings/timer/marvell,orion-timer.txt
index 62bb826..cd1a0c2 100644
--- a/dts/Bindings/timer/marvell,orion-timer.txt
+++ b/dts/Bindings/timer/marvell,orion-timer.txt
@@ -3,7 +3,6 @@ Marvell Orion SoC timer
Required properties:
- compatible: shall be "marvell,orion-timer"
- reg: base address of the timer register starting with TIMERS CONTROL register
-- interrupt-parent: phandle of the bridge interrupt controller
- interrupts: should contain the interrupts for Timer0 and Timer1
- clocks: phandle of timer reference clock (tclk)
diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt
index b1fe7e9..18d4d01 100644
--- a/dts/Bindings/timer/mediatek,mtk-timer.txt
+++ b/dts/Bindings/timer/mediatek,mtk-timer.txt
@@ -1,19 +1,25 @@
-Mediatek MT6577, MT6572 and MT6589 Timers
----------------------------------------
+Mediatek Timers
+---------------
+
+Mediatek SoCs have two different timers on different platforms,
+- GPT (General Purpose Timer)
+- SYST (System Timer)
+
+The proper timer will be selected automatically by driver.
Required properties:
- compatible should contain:
- * "mediatek,mt2701-timer" for MT2701 compatible timers
- * "mediatek,mt6580-timer" for MT6580 compatible timers
- * "mediatek,mt6589-timer" for MT6589 compatible timers
- * "mediatek,mt7623-timer" for MT7623 compatible timers
- * "mediatek,mt8127-timer" for MT8127 compatible timers
- * "mediatek,mt8135-timer" for MT8135 compatible timers
- * "mediatek,mt8173-timer" for MT8173 compatible timers
- * "mediatek,mt6577-timer" for MT6577 and all above compatible timers
-- reg: Should contain location and length for timers register.
-- clocks: Clocks driving the timer hardware. This list should include two
- clocks. The order is system clock and as second clock the RTC clock.
+ * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
+ * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
+ * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
+ * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
+ * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
+ * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
+ * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
+ * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
+ * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST)
+- reg: Should contain location and length for timer register.
+- clocks: Should contain system clock.
Examples:
@@ -21,5 +27,5 @@ Examples:
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&system_clk>, <&rtc_clk>;
+ clocks = <&system_clk>;
};
diff --git a/dts/Bindings/timer/snps,arc-timer.txt b/dts/Bindings/timer/snps,arc-timer.txt
index 4ef0246..147ef3e 100644
--- a/dts/Bindings/timer/snps,arc-timer.txt
+++ b/dts/Bindings/timer/snps,arc-timer.txt
@@ -12,10 +12,6 @@ Required properties:
(16 for ARCHS cores, 3 for ARC700 cores)
- clocks : phandle to the source clock
-Optional properties:
-
-- interrupt-parent : phandle to parent intc
-
Example:
timer0 {
diff --git a/dts/Bindings/timer/st,spear-timer.txt b/dts/Bindings/timer/st,spear-timer.txt
index c001722..b5238a0 100644
--- a/dts/Bindings/timer/st,spear-timer.txt
+++ b/dts/Bindings/timer/st,spear-timer.txt
@@ -5,8 +5,6 @@
- compatible : Should be:
"st,spear-timer"
- reg: Address range of the timer registers
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- interrupt: Should contain the timer interrupt number
Example:
diff --git a/dts/Bindings/timer/ti,c64x+timer64.txt b/dts/Bindings/timer/ti,c64x+timer64.txt
index 95911fe..d96c1e2 100644
--- a/dts/Bindings/timer/ti,c64x+timer64.txt
+++ b/dts/Bindings/timer/ti,c64x+timer64.txt
@@ -7,7 +7,6 @@ Required properties:
- compatible: must be "ti,c64x+timer64"
- reg: base address and size of register region
-- interrupt-parent: interrupt controller
- interrupts: interrupt id
Optional properties:
diff --git a/dts/Bindings/timer/ti,davinci-timer.txt b/dts/Bindings/timer/ti,davinci-timer.txt
new file mode 100644
index 0000000..29bf91c
--- /dev/null
+++ b/dts/Bindings/timer/ti,davinci-timer.txt
@@ -0,0 +1,37 @@
+* Device tree bindings for Texas Instruments DaVinci timer
+
+This document provides bindings for the 64-bit timer in the DaVinci
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+The timer is a free running up-counter and can generate interrupts when the
+counter reaches preset counter values.
+
+Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
+watchdog timers.
+
+Required properties:
+
+- compatible : should be "ti,da830-timer".
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupts generated by the timer.
+- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
+ "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
+ "cmpint7" ("cmpintX" may be omitted if not present in the
+ hardware).
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+ clocksource: timer@20000 {
+ compatible = "ti,da830-timer";
+ reg = <0x20000 0x1000>;
+ interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
+ <80>, <81>;
+ interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
+ "cmpint2", "cmpint3", "cmpint4", "cmpint5",
+ "cmpint6", "cmpint7";
+ clocks = <&pll0_auxclk>;
+ };