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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-28 08:52:27 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-28 08:52:27 +0200 |
commit | 3b5c343782dea7827694cafd53fed08645cb6abf (patch) | |
tree | 657125ff896c3e46e982b5d2a26363ed4bf8cc82 /dts/Bindings/timer | |
parent | bfbf18d991756858337f7700e8ff0a6f0dc31afc (diff) | |
download | barebox-3b5c343782dea7827694cafd53fed08645cb6abf.tar.gz barebox-3b5c343782dea7827694cafd53fed08645cb6abf.tar.xz |
dts: update to v4.9-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/timer')
-rw-r--r-- | dts/Bindings/timer/jcore,pit.txt | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/dts/Bindings/timer/jcore,pit.txt b/dts/Bindings/timer/jcore,pit.txt new file mode 100644 index 0000000000..af5dd35469 --- /dev/null +++ b/dts/Bindings/timer/jcore,pit.txt @@ -0,0 +1,24 @@ +J-Core Programmable Interval Timer and Clocksource + +Required properties: + +- compatible: Must be "jcore,pit". + +- reg: Memory region(s) for timer/clocksource registers. For SMP, + there should be one region per cpu, indexed by the sequential, + zero-based hardware cpu number. + +- interrupts: An interrupt to assign for the timer. The actual pit + core is integrated with the aic and allows the timer interrupt + assignment to be programmed by software, but this property is + required in order to reserve an interrupt number that doesn't + conflict with other devices. + + +Example: + +timer@200 { + compatible = "jcore,pit"; + reg = < 0x200 0x30 0x500 0x30 >; + interrupts = < 0x48 >; +}; |