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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 08:14:56 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 08:14:56 +0200 |
commit | 6b85c20d46812bdbc062b863261c3e5100e30556 (patch) | |
tree | e067c9889eaf55d5e793b05a14000276f2669e9f /dts/Bindings/x86/ce4100.txt | |
parent | 9d8c00bdf7c1e8b614a797f0a15fa45bf6387224 (diff) | |
download | barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.gz barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.xz |
dts: update to v4.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/x86/ce4100.txt')
-rw-r--r-- | dts/Bindings/x86/ce4100.txt | 37 |
1 files changed, 28 insertions, 9 deletions
diff --git a/dts/Bindings/x86/ce4100.txt b/dts/Bindings/x86/ce4100.txt index b49ae593a6..cd1221bfb5 100644 --- a/dts/Bindings/x86/ce4100.txt +++ b/dts/Bindings/x86/ce4100.txt @@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the ce4100 name in their compatible property because they first appeared in this SoC. -The CPU node ------------- - cpu@0 { - device_type = "cpu"; - compatible = "intel,ce4100"; - reg = <0>; - lapic = <&lapic0>; +The CPU nodes +------------- + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,ce4100"; + reg = <0x00>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,ce4100"; + reg = <0x02>; + }; }; -The reg property describes the CPU number. The lapic property points to -the local APIC timer. +A "cpu" node describes one logical processor (hardware thread). + +Required properties: + +- device_type + Device type, must be "cpu". + +- reg + Local APIC ID, the unique number assigned to each processor by + system hardware. The SoC node ------------ |