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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:32:09 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:38 +0100 |
commit | 52216ffe6fd7b641d3e0bc3c9b98bc790f0e06db (patch) | |
tree | 69fa27a996146aaa7a2e2db9209391c49c8fba60 /dts/Bindings | |
parent | a45d4bb23f49990a6b994bbaac5156ad6ebdc453 (diff) | |
download | barebox-52216ffe6fd7b641d3e0bc3c9b98bc790f0e06db.tar.gz barebox-52216ffe6fd7b641d3e0bc3c9b98bc790f0e06db.tar.xz |
dts: update to v4.2-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r-- | dts/Bindings/phy/ti-phy.txt | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/dts/Bindings/phy/ti-phy.txt b/dts/Bindings/phy/ti-phy.txt index 305e3df3d9..9cf9446eaf 100644 --- a/dts/Bindings/phy/ti-phy.txt +++ b/dts/Bindings/phy/ti-phy.txt @@ -82,6 +82,9 @@ Optional properties: - id: If there are multiple instance of the same type, in order to differentiate between each instance "id" can be used (e.g., multi-lane PCIe PHY). If "id" is not provided, it is set to default value of '1'. + - syscon-pllreset: Handle to system control region that contains the + CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 + register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. This is usually a subnode of ocp2scp to which it is connected. @@ -100,3 +103,16 @@ usb3phy@4a084400 { "sysclk", "refclk"; }; + +sata_phy: phy@4A096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_sata>; + clocks = <&sys_clkin1>, <&sata_ref_clk>; + clock-names = "sysclk", "refclk"; + syscon-pllreset = <&scm_conf 0x3fc>; + #phy-cells = <0>; +}; |