summaryrefslogtreecommitdiffstats
path: root/dts/Bindings
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2021-05-17 13:27:45 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2021-05-17 16:23:06 +0200
commita5a4c1d5a3c4f89059fb612b5786ec8b61b959f1 (patch)
treefe87198c6cc02e54d3131d087d2b9f7c3e96c689 /dts/Bindings
parentba9de18c5f211678f5d0f67a0758c632ab774cca (diff)
downloadbarebox-a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1.tar.gz
barebox-a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1.tar.xz
dts: update to v5.13-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/.gitignore4
-rw-r--r--dts/Bindings/Makefile7
-rw-r--r--dts/Bindings/arm/amlogic.yaml3
-rw-r--r--dts/Bindings/arm/apple.yaml64
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm4908.yaml1
-rw-r--r--dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml25
-rw-r--r--dts/Bindings/arm/cpus.yaml4
-rw-r--r--dts/Bindings/arm/ete.yaml75
-rw-r--r--dts/Bindings/arm/fsl.yaml16
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller.txt4
-rw-r--r--dts/Bindings/arm/mediatek.yaml36
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.yaml1
-rw-r--r--dts/Bindings/arm/mstar/mstar.yaml1
-rw-r--r--dts/Bindings/arm/npcm/npcm.txt6
-rw-r--r--dts/Bindings/arm/npcm/npcm.yaml29
-rw-r--r--dts/Bindings/arm/qcom.yaml20
-rw-r--r--dts/Bindings/arm/rockchip.yaml1
-rw-r--r--dts/Bindings/arm/stm32/stm32.yaml21
-rw-r--r--dts/Bindings/arm/sunxi.yaml5
-rw-r--r--dts/Bindings/arm/ti/k3.yaml9
-rw-r--r--dts/Bindings/arm/trbe.yaml49
-rw-r--r--dts/Bindings/ata/ahci-ceva.txt4
-rw-r--r--dts/Bindings/ata/nvidia,tegra-ahci.yaml176
-rw-r--r--dts/Bindings/ata/nvidia,tegra124-ahci.txt44
-rw-r--r--dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml2
-rw-r--r--dts/Bindings/clock/armada3700-tbg-clock.txt2
-rw-r--r--dts/Bindings/clock/imx8qxp-lpcg.yaml6
-rw-r--r--dts/Bindings/clock/mediatek,mt7621-sysc.yaml68
-rw-r--r--dts/Bindings/clock/milbeaut-clock.yaml12
-rw-r--r--dts/Bindings/clock/qcom,gcc-sdm845.yaml82
-rw-r--r--dts/Bindings/clock/qcom,gcc.yaml2
-rw-r--r--dts/Bindings/clock/rockchip,rk3568-cru.yaml60
-rw-r--r--dts/Bindings/connector/usb-connector.yaml10
-rw-r--r--dts/Bindings/counter/interrupt-counter.yaml62
-rw-r--r--dts/Bindings/crypto/ti,sa2ul.yaml24
-rw-r--r--dts/Bindings/ddr/lpddr3.txt5
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt75
-rw-r--r--dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml1
-rw-r--r--dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml4
-rw-r--r--dts/Bindings/display/brcm,bcm2835-dsi0.yaml6
-rw-r--r--dts/Bindings/display/bridge/analogix,anx7625.yaml15
-rw-r--r--dts/Bindings/display/bridge/chipone,icn6211.yaml99
-rw-r--r--dts/Bindings/display/bridge/dw_hdmi.txt33
-rw-r--r--dts/Bindings/display/bridge/lontium,lt8912b.yaml102
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.txt88
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.yaml125
-rw-r--r--dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml55
-rw-r--r--dts/Bindings/display/fsl,lcdif.yaml110
-rw-r--r--dts/Bindings/display/imx/fsl,imx6-hdmi.yaml126
-rw-r--r--dts/Bindings/display/imx/hdmi.txt65
-rw-r--r--dts/Bindings/display/mediatek/mediatek,disp.txt2
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.yaml12
-rw-r--r--dts/Bindings/display/msm/dpu.txt4
-rw-r--r--dts/Bindings/display/mxsfb.txt87
-rw-r--r--dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml1
-rw-r--r--dts/Bindings/display/panel/panel-dpi.yaml2
-rw-r--r--dts/Bindings/display/panel/panel-simple.yaml2
-rw-r--r--dts/Bindings/display/renesas,du.txt145
-rw-r--r--dts/Bindings/display/renesas,du.yaml834
-rw-r--r--dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt74
-rw-r--r--dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml156
-rw-r--r--dts/Bindings/display/simple-framebuffer.yaml5
-rw-r--r--dts/Bindings/dma/qcom,gpi.yaml3
-rw-r--r--dts/Bindings/extcon/qcom,pm8941-misc.txt41
-rw-r--r--dts/Bindings/extcon/qcom,pm8941-misc.yaml62
-rw-r--r--dts/Bindings/firmware/qcom,scm.txt2
-rw-r--r--dts/Bindings/fpga/fpga-region.txt187
-rw-r--r--dts/Bindings/fpga/xilinx-pr-decoupler.txt24
-rw-r--r--dts/Bindings/gpio/brcm,bcm6345-gpio.txt46
-rw-r--r--dts/Bindings/gpio/brcm,bcm6345-gpio.yaml86
-rw-r--r--dts/Bindings/gpio/fairchild,74hc595.yaml77
-rw-r--r--dts/Bindings/gpio/gpio-74x164.txt27
-rw-r--r--dts/Bindings/gpio/realtek,otto-gpio.yaml78
-rw-r--r--dts/Bindings/gpio/rockchip,gpio-bank.yaml82
-rw-r--r--dts/Bindings/gpio/socionext,uniphier-gpio.yaml3
-rw-r--r--dts/Bindings/gpu/arm,mali-bifrost.yaml2
-rw-r--r--dts/Bindings/hwlock/sirf,hwspinlock.txt28
-rw-r--r--dts/Bindings/i2c/i2c-mpc.txt62
-rw-r--r--dts/Bindings/i2c/i2c-mpc.yaml91
-rw-r--r--dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml2
-rw-r--r--dts/Bindings/i3c/cdns,i3c-master.txt6
-rw-r--r--dts/Bindings/i3c/i3c.yaml7
-rw-r--r--dts/Bindings/i3c/silvaco,i3c-master.yaml2
-rw-r--r--dts/Bindings/i3c/snps,dw-i3c-master.txt6
-rw-r--r--dts/Bindings/iio/accel/bosch,bmi088.yaml68
-rw-r--r--dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml5
-rw-r--r--dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml1
-rw-r--r--dts/Bindings/iio/adc/ti,ads131e08.yaml181
-rw-r--r--dts/Bindings/iio/cdc/adi,ad7150.yaml69
-rw-r--r--dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml2
-rw-r--r--dts/Bindings/iio/imu/adi,adis16475.yaml9
-rw-r--r--dts/Bindings/iio/light/capella,cm3605.yaml1
-rw-r--r--dts/Bindings/iio/light/upisemi,us5182.yaml4
-rw-r--r--dts/Bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml37
-rw-r--r--dts/Bindings/iio/st,st-sensors.yaml1
-rw-r--r--dts/Bindings/index.rst7
-rw-r--r--dts/Bindings/infiniband/hisilicon-hns-roce.txt2
-rw-r--r--dts/Bindings/input/atmel,maxtouch.yaml32
-rw-r--r--dts/Bindings/input/input.yaml6
-rw-r--r--dts/Bindings/input/iqs626a.yaml843
-rw-r--r--dts/Bindings/input/touchscreen/azoteq,iqs5xx.yaml75
-rw-r--r--dts/Bindings/input/touchscreen/hycon,hy46xx.yaml119
-rw-r--r--dts/Bindings/input/touchscreen/ilitek_ts_i2c.yaml73
-rw-r--r--dts/Bindings/input/touchscreen/iqs5xx.txt80
-rw-r--r--dts/Bindings/input/touchscreen/melfas,mms114.yaml87
-rw-r--r--dts/Bindings/input/touchscreen/mms114.txt42
-rw-r--r--dts/Bindings/input/touchscreen/mstar,msg2638.yaml69
-rw-r--r--dts/Bindings/interconnect/qcom,rpmh.yaml10
-rw-r--r--dts/Bindings/interconnect/qcom,sdm660.yaml147
-rw-r--r--dts/Bindings/interrupt-controller/apple,aic.yaml88
-rw-r--r--dts/Bindings/interrupt-controller/idt,32434-pic.yaml52
-rw-r--r--dts/Bindings/interrupt-controller/loongson,htpic.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/loongson,liointc.yaml36
-rw-r--r--dts/Bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml39
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt1
-rw-r--r--dts/Bindings/iommu/arm,smmu.yaml1
-rw-r--r--dts/Bindings/iommu/sprd,iommu.yaml57
-rw-r--r--dts/Bindings/leds/backlight/kinetic,ktd253.yaml9
-rw-r--r--dts/Bindings/leds/backlight/qcom-wled.yaml1
-rw-r--r--dts/Bindings/leds/leds-lgm.yaml26
-rw-r--r--dts/Bindings/leds/leds-rt4505.yaml57
-rw-r--r--dts/Bindings/mailbox/fsl,mu.yaml5
-rw-r--r--dts/Bindings/mailbox/qcom-ipcc.yaml2
-rw-r--r--dts/Bindings/mailbox/sprd-mailbox.yaml13
-rw-r--r--dts/Bindings/mailbox/ti,secure-proxy.txt50
-rw-r--r--dts/Bindings/mailbox/ti,secure-proxy.yaml79
-rw-r--r--dts/Bindings/media/allwinner,sun4i-a10-ir.yaml16
-rw-r--r--dts/Bindings/media/mediatek-jpeg-decoder.txt2
-rw-r--r--dts/Bindings/media/mediatek-jpeg-encoder.txt2
-rw-r--r--dts/Bindings/media/mediatek-mdp.txt2
-rw-r--r--dts/Bindings/media/mediatek-vcodec.txt57
-rw-r--r--dts/Bindings/media/nxp,imx7-mipi-csi2.yaml108
-rw-r--r--dts/Bindings/media/nxp,imx8-jpeg.yaml84
-rw-r--r--dts/Bindings/media/qcom,camss.txt236
-rw-r--r--dts/Bindings/media/qcom,msm8916-camss.yaml256
-rw-r--r--dts/Bindings/media/qcom,msm8996-camss.yaml387
-rw-r--r--dts/Bindings/media/qcom,sdm660-camss.yaml398
-rw-r--r--dts/Bindings/media/qcom,sdm845-camss.yaml371
-rw-r--r--dts/Bindings/media/qcom,sm8250-venus.yaml167
-rw-r--r--dts/Bindings/media/rc.yaml5
-rw-r--r--dts/Bindings/media/renesas,drif.txt177
-rw-r--r--dts/Bindings/media/renesas,drif.yaml279
-rw-r--r--dts/Bindings/media/renesas,vin.yaml46
-rw-r--r--dts/Bindings/media/video-interfaces.yaml127
-rw-r--r--dts/Bindings/media/video-mux.txt60
-rw-r--r--dts/Bindings/media/video-mux.yaml106
-rw-r--r--dts/Bindings/media/zx-irdec.txt14
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml7
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt4
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt40
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra20-mc.yaml79
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra210-emc.yaml2
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml7
-rw-r--r--dts/Bindings/mfd/actions,atc260x.yaml183
-rw-r--r--dts/Bindings/mfd/aspeed-lpc.txt100
-rw-r--r--dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml177
-rw-r--r--dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml194
-rw-r--r--dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml162
-rw-r--r--dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml130
-rw-r--r--dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml236
-rw-r--r--dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml246
-rw-r--r--dts/Bindings/mfd/google,cros-ec.yaml7
-rw-r--r--dts/Bindings/mfd/netronix,ntxec.yaml76
-rw-r--r--dts/Bindings/mfd/qcom-pm8xxx.txt99
-rw-r--r--dts/Bindings/mfd/qcom-pm8xxx.yaml54
-rw-r--r--dts/Bindings/mfd/ricoh,rn5t618.yaml111
-rw-r--r--dts/Bindings/mfd/rn5t618.txt52
-rw-r--r--dts/Bindings/mfd/rohm,bd71815-pmic.yaml201
-rw-r--r--dts/Bindings/mfd/rohm,bd71828-pmic.yaml6
-rw-r--r--dts/Bindings/mfd/rohm,bd9576-pmic.yaml123
-rw-r--r--dts/Bindings/mfd/ti,lp87524-q1.yaml4
-rw-r--r--dts/Bindings/mfd/ti,lp87561-q1.yaml4
-rw-r--r--dts/Bindings/mfd/ti,lp87565-q1.yaml4
-rw-r--r--dts/Bindings/mmc/brcm,iproc-sdhci.yaml63
-rw-r--r--dts/Bindings/mmc/brcm,sdhci-iproc.txt37
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.yaml20
-rw-r--r--dts/Bindings/mmc/mmc-spi-slot.txt6
-rw-r--r--dts/Bindings/mmc/mtk-sd.yaml1
-rw-r--r--dts/Bindings/mmc/sdhci-of-dwcmshc.txt20
-rw-r--r--dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml87
-rw-r--r--dts/Bindings/mtd/nand-controller.yaml7
-rw-r--r--dts/Bindings/mtd/partitions/linksys,ns-partitions.yaml74
-rw-r--r--dts/Bindings/mtd/partitions/nvmem-cells.yaml99
-rw-r--r--dts/Bindings/mtd/qcom,nandc.yaml196
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt142
-rw-r--r--dts/Bindings/mtd/tango-nand.txt38
-rw-r--r--dts/Bindings/net/actions,owl-emac.yaml92
-rw-r--r--dts/Bindings/net/brcm,bcm4908-enet.yaml17
-rw-r--r--dts/Bindings/net/brcm,bcm6368-mdio-mux.yaml76
-rw-r--r--dts/Bindings/net/broadcom-bluetooth.txt56
-rw-r--r--dts/Bindings/net/broadcom-bluetooth.yaml118
-rw-r--r--dts/Bindings/net/can/fsl,flexcan.yaml1
-rw-r--r--dts/Bindings/net/can/rcar_can.txt5
-rw-r--r--dts/Bindings/net/dsa/dsa.yaml9
-rw-r--r--dts/Bindings/net/dsa/lantiq-gswip.txt4
-rw-r--r--dts/Bindings/net/dsa/microchip,ksz.yaml2
-rw-r--r--dts/Bindings/net/fsl-enetc.txt15
-rw-r--r--dts/Bindings/net/idt,3243x-emac.yaml73
-rw-r--r--dts/Bindings/net/intel,ixp4xx-ethernet.yaml102
-rw-r--r--dts/Bindings/net/mdio-gpio.txt1
-rw-r--r--dts/Bindings/net/qcom,ipa.yaml26
-rw-r--r--dts/Bindings/net/renesas,etheravb.yaml11
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt76
-rw-r--r--dts/Bindings/net/rockchip-dwmac.yaml120
-rw-r--r--dts/Bindings/net/snps,dwmac.yaml13
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml109
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt38
-rw-r--r--dts/Bindings/net/wireless/ieee80211.txt24
-rw-r--r--dts/Bindings/net/wireless/ieee80211.yaml45
-rw-r--r--dts/Bindings/net/wireless/mediatek,mt76.txt78
-rw-r--r--dts/Bindings/net/wireless/mediatek,mt76.yaml228
-rw-r--r--dts/Bindings/net/xilinx_axienet.txt25
-rw-r--r--dts/Bindings/nvmem/brcm,nvram.yaml34
-rw-r--r--dts/Bindings/nvmem/mtk-efuse.txt2
-rw-r--r--dts/Bindings/nvmem/nvmem-consumer.yaml4
-rw-r--r--dts/Bindings/nvmem/nvmem.yaml3
-rw-r--r--dts/Bindings/nvmem/qcom,qfprom.yaml1
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt43
-rw-r--r--dts/Bindings/pci/mediatek-pcie-gen3.yaml181
-rw-r--r--dts/Bindings/pci/rcar-pci-host.yaml12
-rw-r--r--dts/Bindings/pci/sifive,fu740-pcie.yaml113
-rw-r--r--dts/Bindings/pci/tango-pcie.txt29
-rw-r--r--dts/Bindings/pci/ti,j721e-pci-ep.yaml9
-rw-r--r--dts/Bindings/pci/ti,j721e-pci-host.yaml20
-rw-r--r--dts/Bindings/pci/xilinx-nwl-pcie.txt2
-rw-r--r--dts/Bindings/phy/bcm-ns-usb2-phy.txt21
-rw-r--r--dts/Bindings/phy/bcm-ns-usb2-phy.yaml59
-rw-r--r--dts/Bindings/phy/bcm-ns-usb3-phy.txt34
-rw-r--r--dts/Bindings/phy/bcm-ns-usb3-phy.yaml62
-rw-r--r--dts/Bindings/phy/brcm,brcmstb-usb-phy.yaml3
-rw-r--r--dts/Bindings/phy/marvell,armada-3700-utmi-phy.yaml57
-rw-r--r--dts/Bindings/phy/marvell,armada-cp110-utmi-phy.yaml109
-rw-r--r--dts/Bindings/phy/mediatek,dsi-phy.yaml13
-rw-r--r--dts/Bindings/phy/mediatek,hdmi-phy.yaml11
-rw-r--r--dts/Bindings/phy/mediatek,tphy.yaml3
-rw-r--r--dts/Bindings/phy/mediatek,ufs-phy.yaml7
-rw-r--r--dts/Bindings/phy/microchip,sparx5-serdes.yaml100
-rw-r--r--dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt1
-rw-r--r--dts/Bindings/phy/phy-cadence-sierra.yaml17
-rw-r--r--dts/Bindings/phy/phy-cadence-torrent.yaml22
-rw-r--r--dts/Bindings/phy/phy-mvebu-utmi.txt38
-rw-r--r--dts/Bindings/phy/phy-stm32-usbphyc.yaml5
-rw-r--r--dts/Bindings/phy/qcom,qmp-phy.yaml2
-rw-r--r--dts/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml3
-rw-r--r--dts/Bindings/phy/qcom,usb-snps-femto-v2.yaml1
-rw-r--r--dts/Bindings/phy/ti,phy-j721e-wiz.yaml6
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm6318-pinctrl.yaml143
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm63268-pinctrl.yaml164
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm6328-pinctrl.yaml127
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm6358-pinctrl.yaml93
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm6362-pinctrl.yaml206
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm6368-pinctrl.yaml217
-rw-r--r--dts/Bindings/pinctrl/ingenic,pinctrl.yaml23
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt8195.yaml151
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-gpio.txt14
-rw-r--r--dts/Bindings/pinctrl/rockchip,pinctrl.txt59
-rw-r--r--dts/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml336
-rw-r--r--dts/Bindings/power/brcm,bcm-pmb.yaml1
-rw-r--r--dts/Bindings/power/qcom,rpmpd.yaml2
-rw-r--r--dts/Bindings/power/reset/ltc2952-poweroff.txt4
-rw-r--r--dts/Bindings/power/supply/ab8500/btemp.txt16
-rw-r--r--dts/Bindings/power/supply/ab8500/chargalg.txt16
-rw-r--r--dts/Bindings/power/supply/ab8500/charger.txt25
-rw-r--r--dts/Bindings/power/supply/act8945a-charger.txt44
-rw-r--r--dts/Bindings/power/supply/active-semi,act8945a-charger.yaml76
-rw-r--r--dts/Bindings/power/supply/axp20x_ac_power.txt25
-rw-r--r--dts/Bindings/power/supply/axp20x_battery.txt20
-rw-r--r--dts/Bindings/power/supply/axp20x_usb_power.txt41
-rw-r--r--dts/Bindings/power/supply/battery.txt3
-rw-r--r--dts/Bindings/power/supply/bq2415x.txt47
-rw-r--r--dts/Bindings/power/supply/bq2415x.yaml98
-rw-r--r--dts/Bindings/power/supply/bq24190.txt61
-rw-r--r--dts/Bindings/power/supply/bq24190.yaml92
-rw-r--r--dts/Bindings/power/supply/bq24257.txt62
-rw-r--r--dts/Bindings/power/supply/bq24257.yaml124
-rw-r--r--dts/Bindings/power/supply/bq24735.yaml89
-rw-r--r--dts/Bindings/power/supply/bq256xx.yaml1
-rw-r--r--dts/Bindings/power/supply/bq25890.txt60
-rw-r--r--dts/Bindings/power/supply/bq25890.yaml123
-rw-r--r--dts/Bindings/power/supply/bq27xxx.yaml3
-rw-r--r--dts/Bindings/power/supply/cpcap-battery.txt31
-rw-r--r--dts/Bindings/power/supply/cpcap-battery.yaml87
-rw-r--r--dts/Bindings/power/supply/cpcap-charger.txt40
-rw-r--r--dts/Bindings/power/supply/cpcap-charger.yaml106
-rw-r--r--dts/Bindings/power/supply/cw2015_battery.yaml2
-rw-r--r--dts/Bindings/power/supply/da9150-charger.txt26
-rw-r--r--dts/Bindings/power/supply/da9150-fg.txt23
-rw-r--r--dts/Bindings/power/supply/dlg,da9150-charger.yaml52
-rw-r--r--dts/Bindings/power/supply/dlg,da9150-fuel-gauge.yaml51
-rw-r--r--dts/Bindings/power/supply/isp1704.txt17
-rw-r--r--dts/Bindings/power/supply/isp1704.yaml42
-rw-r--r--dts/Bindings/power/supply/lego,ev3-battery.yaml55
-rw-r--r--dts/Bindings/power/supply/lego_ev3_battery.txt21
-rw-r--r--dts/Bindings/power/supply/lltc,lt3651-charger.yaml44
-rw-r--r--dts/Bindings/power/supply/lltc,ltc294x.yaml66
-rw-r--r--dts/Bindings/power/supply/lp8727_charger.txt43
-rw-r--r--dts/Bindings/power/supply/lt3651-charger.txt29
-rw-r--r--dts/Bindings/power/supply/ltc2941.txt28
-rw-r--r--dts/Bindings/power/supply/ltc4162-l.yaml2
-rw-r--r--dts/Bindings/power/supply/max17040_battery.txt52
-rw-r--r--dts/Bindings/power/supply/max17042_battery.txt35
-rw-r--r--dts/Bindings/power/supply/max8903-charger.txt24
-rw-r--r--dts/Bindings/power/supply/maxim,ds2760.txt26
-rw-r--r--dts/Bindings/power/supply/maxim,ds2760.yaml43
-rw-r--r--dts/Bindings/power/supply/maxim,max14656.txt23
-rw-r--r--dts/Bindings/power/supply/maxim,max14656.yaml45
-rw-r--r--dts/Bindings/power/supply/maxim,max17040.yaml95
-rw-r--r--dts/Bindings/power/supply/maxim,max17042.yaml78
-rw-r--r--dts/Bindings/power/supply/maxim,max8903.yaml67
-rw-r--r--dts/Bindings/power/supply/microchip,ucs1002.txt27
-rw-r--r--dts/Bindings/power/supply/microchip,ucs1002.yaml51
-rw-r--r--dts/Bindings/power/supply/nokia,n900-battery.yaml49
-rw-r--r--dts/Bindings/power/supply/olpc-battery.yaml27
-rw-r--r--dts/Bindings/power/supply/olpc_battery.txt5
-rw-r--r--dts/Bindings/power/supply/power-supply.yaml22
-rw-r--r--dts/Bindings/power/supply/power_supply.txt2
-rw-r--r--dts/Bindings/power/supply/qcom,coincell-charger.txt48
-rw-r--r--dts/Bindings/power/supply/qcom,pm8941-charger.yaml169
-rw-r--r--dts/Bindings/power/supply/qcom,pm8941-coincell.yaml57
-rw-r--r--dts/Bindings/power/supply/qcom_smbb.txt150
-rw-r--r--dts/Bindings/power/supply/richtek,rt9455.yaml90
-rw-r--r--dts/Bindings/power/supply/rohm,bd99954.yaml2
-rw-r--r--dts/Bindings/power/supply/rt9455_charger.txt46
-rw-r--r--dts/Bindings/power/supply/rx51-battery.txt25
-rw-r--r--dts/Bindings/power/supply/sbs,sbs-battery.yaml7
-rw-r--r--dts/Bindings/power/supply/sbs,sbs-charger.yaml55
-rw-r--r--dts/Bindings/power/supply/sbs,sbs-manager.txt66
-rw-r--r--dts/Bindings/power/supply/sbs,sbs-manager.yaml107
-rw-r--r--dts/Bindings/power/supply/sbs_sbs-charger.txt21
-rw-r--r--dts/Bindings/power/supply/sc2731-charger.yaml53
-rw-r--r--dts/Bindings/power/supply/sc2731_charger.txt40
-rw-r--r--dts/Bindings/power/supply/sc27xx-fg.txt59
-rw-r--r--dts/Bindings/power/supply/sc27xx-fg.yaml98
-rw-r--r--dts/Bindings/power/supply/stericsson,ab8500-battery.txt (renamed from dts/Bindings/power/supply/ab8500/fg.txt)32
-rw-r--r--dts/Bindings/power/supply/stericsson,ab8500-btemp.yaml73
-rw-r--r--dts/Bindings/power/supply/stericsson,ab8500-chargalg.yaml37
-rw-r--r--dts/Bindings/power/supply/stericsson,ab8500-charger.yaml123
-rw-r--r--dts/Bindings/power/supply/stericsson,ab8500-fg.yaml72
-rw-r--r--dts/Bindings/power/supply/ti,bq24735.txt39
-rw-r--r--dts/Bindings/power/supply/ti,lp8727.yaml90
-rw-r--r--dts/Bindings/power/supply/tps65090-charger.yaml36
-rw-r--r--dts/Bindings/power/supply/tps65090.txt17
-rw-r--r--dts/Bindings/power/supply/tps65217-charger.yaml43
-rw-r--r--dts/Bindings/power/supply/tps65217_charger.txt17
-rw-r--r--dts/Bindings/power/supply/twl-charger.txt30
-rw-r--r--dts/Bindings/power/supply/twl4030-charger.yaml68
-rw-r--r--dts/Bindings/power/supply/x-powers,axp20x-ac-power-supply.yaml32
-rw-r--r--dts/Bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml30
-rw-r--r--dts/Bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml33
-rw-r--r--dts/Bindings/pwm/pwm-rockchip.txt27
-rw-r--r--dts/Bindings/pwm/pwm-rockchip.yaml100
-rw-r--r--dts/Bindings/pwm/toshiba,pwm-visconti.yaml43
-rw-r--r--dts/Bindings/regulator/fan53555.txt4
-rw-r--r--dts/Bindings/regulator/qcom,rpmh-regulator.txt180
-rw-r--r--dts/Bindings/regulator/qcom,rpmh-regulator.yaml162
-rw-r--r--dts/Bindings/regulator/qcom-labibb-regulator.yaml1
-rw-r--r--dts/Bindings/regulator/rohm,bd71815-regulator.yaml116
-rw-r--r--dts/Bindings/remoteproc/fsl,imx-rproc.yaml90
-rw-r--r--dts/Bindings/remoteproc/imx-rproc.txt33
-rw-r--r--dts/Bindings/remoteproc/qcom,adsp.txt4
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt15
-rw-r--r--dts/Bindings/remoteproc/qcom,wcnss-pil.txt6
-rw-r--r--dts/Bindings/remoteproc/st,stm32-rproc.yaml11
-rw-r--r--dts/Bindings/remoteproc/ti,omap-remoteproc.yaml2
-rw-r--r--dts/Bindings/reserved-memory/ramoops.txt10
-rw-r--r--dts/Bindings/riscv/microchip.yaml27
-rw-r--r--dts/Bindings/rng/brcm,bcm2835.yaml21
-rw-r--r--dts/Bindings/rtc/qcom-pm8xxx-rtc.yaml62
-rw-r--r--dts/Bindings/serial/8250.yaml35
-rw-r--r--dts/Bindings/serial/brcm,bcm7271-uart.yaml95
-rw-r--r--dts/Bindings/serial/ingenic,uart.yaml2
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/samsung_uart.yaml18
-rw-r--r--dts/Bindings/serial/serial.yaml12
-rw-r--r--dts/Bindings/serial/st,stm32-uart.yaml59
-rw-r--r--dts/Bindings/soc/mediatek/pwrap.txt1
-rw-r--r--dts/Bindings/soc/qcom/qcom,aoss-qmp.txt1
-rw-r--r--dts/Bindings/soc/qcom/qcom,wcnss.txt7
-rw-r--r--dts/Bindings/sound/ak4642.yaml2
-rw-r--r--dts/Bindings/sound/ak5558.txt2
-rw-r--r--dts/Bindings/sound/audio-graph-port.yaml104
-rw-r--r--dts/Bindings/sound/fsl,rpmsg.yaml108
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt2
-rw-r--r--dts/Bindings/sound/google,cros-ec-codec.yaml2
-rw-r--r--dts/Bindings/sound/intel,keembay-i2s.yaml2
-rw-r--r--dts/Bindings/sound/marvell,mmp-sspa.yaml6
-rw-r--r--dts/Bindings/sound/mchp,i2s-mcc.yaml108
-rw-r--r--dts/Bindings/sound/mchp-i2s-mcc.txt43
-rw-r--r--dts/Bindings/sound/mt8183-mt6358-ts3a227-max98357.txt1
-rw-r--r--dts/Bindings/sound/nvidia,tegra186-dspk.yaml11
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-admaif.yaml11
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-ahub.yaml27
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-dmic.yaml11
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-i2s.yaml11
-rw-r--r--dts/Bindings/sound/renesas,rsnd.yaml6
-rw-r--r--dts/Bindings/sound/rt1019.yaml35
-rw-r--r--dts/Bindings/sound/rt5682.txt2
-rw-r--r--dts/Bindings/sound/socionext,uniphier-aio.yaml8
-rw-r--r--dts/Bindings/sound/socionext,uniphier-evea.yaml8
-rw-r--r--dts/Bindings/sound/tlv320aic3x.txt21
-rw-r--r--dts/Bindings/soundwire/qcom,sdw.txt20
-rw-r--r--dts/Bindings/spi/amlogic,meson-gx-spicc.yaml4
-rw-r--r--dts/Bindings/spi/brcm,spi-bcm-qspi.txt245
-rw-r--r--dts/Bindings/spi/brcm,spi-bcm-qspi.yaml198
-rw-r--r--dts/Bindings/spi/cadence-quadspi.txt68
-rw-r--r--dts/Bindings/spi/cdns,qspi-nor.yaml143
-rw-r--r--dts/Bindings/spi/fsl,spi-fsl-qspi.yaml96
-rw-r--r--dts/Bindings/spi/mediatek,spi-mtk-nor.yaml1
-rw-r--r--dts/Bindings/spi/spi-controller.yaml21
-rw-r--r--dts/Bindings/spi/spi-fsl-qspi.txt66
-rw-r--r--dts/Bindings/spi/spi-mt65xx.txt2
-rw-r--r--dts/Bindings/spi/spi-mux.yaml8
-rw-r--r--dts/Bindings/spi/spi-nxp-fspi.txt2
-rw-r--r--dts/Bindings/spi/spi-slave-mt27xx.txt1
-rw-r--r--dts/Bindings/spi/st,stm32-spi.yaml6
-rw-r--r--dts/Bindings/submitting-patches.rst10
-rw-r--r--dts/Bindings/thermal/brcm,ns-thermal.txt37
-rw-r--r--dts/Bindings/thermal/brcm,ns-thermal.yaml60
-rw-r--r--dts/Bindings/thermal/qcom-spmi-adc-tm5.yaml2
-rw-r--r--dts/Bindings/thermal/qcom-tsens.yaml59
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.yaml43
-rw-r--r--dts/Bindings/thermal/thermal-sensor.yaml3
-rw-r--r--dts/Bindings/timer/arm,arch_timer.yaml19
-rw-r--r--dts/Bindings/timer/ingenic,tcu.yaml30
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt1
-rw-r--r--dts/Bindings/timer/nuvoton,npcm7xx-timer.txt3
-rw-r--r--dts/Bindings/timer/renesas,cmt.yaml4
-rw-r--r--dts/Bindings/timer/renesas,tmu.yaml6
-rw-r--r--dts/Bindings/trivial-devices.yaml9
-rw-r--r--dts/Bindings/ufs/ufshcd-pltfrm.txt2
-rw-r--r--dts/Bindings/usb/dwc3-xilinx.txt28
-rw-r--r--dts/Bindings/usb/fsl,imx8mp-dwc3.yaml9
-rw-r--r--dts/Bindings/usb/generic-ehci.yaml6
-rw-r--r--dts/Bindings/usb/mediatek,mtk-xhci.yaml29
-rw-r--r--dts/Bindings/usb/mediatek,mtu3.yaml12
-rw-r--r--dts/Bindings/usb/qcom,dwc3.yaml1
-rw-r--r--dts/Bindings/usb/snps,dwc3.yaml8
-rw-r--r--dts/Bindings/usb/usb-device.yaml6
-rw-r--r--dts/Bindings/usb/usb-nop-xceiv.txt43
-rw-r--r--dts/Bindings/usb/usb-nop-xceiv.yaml64
-rw-r--r--dts/Bindings/usb/usb.yaml1
-rw-r--r--dts/Bindings/vendor-prefixes.yaml24
-rw-r--r--dts/Bindings/watchdog/nuvoton,npcm-wdt.txt3
-rw-r--r--dts/Bindings/writing-schema.rst183
445 files changed, 18695 insertions, 5404 deletions
diff --git a/dts/Bindings/.gitignore b/dts/Bindings/.gitignore
index 3a05b99bfa..a77719968a 100644
--- a/dts/Bindings/.gitignore
+++ b/dts/Bindings/.gitignore
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
*.example.dts
-processed-schema*.yaml
-processed-schema*.json
+/processed-schema*.yaml
+/processed-schema*.json
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile
index 780e5618ec..5ccfed90cc 100644
--- a/dts/Bindings/Makefile
+++ b/dts/Bindings/Makefile
@@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_SCHEMA_LINT = $(shell which yamllint)
-DT_SCHEMA_MIN_VERSION = 2020.8.1
+DT_SCHEMA_MIN_VERSION = 2021.2.1
PHONY += check_dtschema_version
check_dtschema_version:
@@ -48,13 +48,16 @@ define rule_chkdt
$(call cmd,mk_schema)
endef
-DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
+DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
-Wno-graph_child_address \
-Wno-interrupt_provider
+# Disable undocumented compatible checks until warning free
+override DT_CHECKER_FLAGS ?=
+
$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)
diff --git a/dts/Bindings/arm/amlogic.yaml b/dts/Bindings/arm/amlogic.yaml
index 5f6769bf45..97fb962663 100644
--- a/dts/Bindings/arm/amlogic.yaml
+++ b/dts/Bindings/arm/amlogic.yaml
@@ -109,6 +109,7 @@ properties:
- libretech,aml-s905d-pc
- phicomm,n1
- smartlabs,sml5442tw
+ - videostrong,gxl-kii-pro
- const: amlogic,s905d
- const: amlogic,meson-gxl
@@ -120,8 +121,10 @@ properties:
- khadas,vim2
- kingnovel,r-box-pro
- libretech,aml-s912-pc
+ - minix,neo-u9h
- nexbox,a1
- tronsmart,vega-s96
+ - videostrong,gxm-kiii-pro
- wetek,core2
- const: amlogic,s912
- const: amlogic,meson-gxm
diff --git a/dts/Bindings/arm/apple.yaml b/dts/Bindings/arm/apple.yaml
new file mode 100644
index 0000000000..1e772c8520
--- /dev/null
+++ b/dts/Bindings/arm/apple.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/apple.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple ARM Machine Device Tree Bindings
+
+maintainers:
+ - Hector Martin <marcan@marcan.st>
+
+description: |
+ ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
+
+ This currently includes devices based on the "M1" SoC, starting with the
+ three Mac models released in late 2020:
+
+ - Mac mini (M1, 2020)
+ - MacBook Pro (13-inch, M1, 2020)
+ - MacBook Air (M1, 2020)
+
+ The compatible property should follow this format:
+
+ compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform";
+
+ <targettype> represents the board/device and comes from the `target-type`
+ property of the root node of the Apple Device Tree, lowercased. It can be
+ queried on macOS using the following command:
+
+ $ ioreg -d2 -l | grep target-type
+
+ <socid> is the lowercased SoC ID. Apple uses at least *five* different
+ names for their SoCs:
+
+ - Marketing name ("M1")
+ - Internal name ("H13G")
+ - Codename ("Tonga")
+ - SoC ID ("T8103")
+ - Package/IC part number ("APL1102")
+
+ Devicetrees should use the lowercased SoC ID, to avoid confusion if
+ multiple SoCs share the same marketing name. This can be obtained from
+ the `compatible` property of the arm-io node of the Apple Device Tree,
+ which can be queried as follows on macOS:
+
+ $ ioreg -n arm-io | grep compatible
+
+properties:
+ $nodename:
+ const: "/"
+ compatible:
+ oneOf:
+ - description: Apple M1 SoC based platforms
+ items:
+ - enum:
+ - apple,j274 # Mac mini (M1, 2020)
+ - apple,j293 # MacBook Pro (13-inch, M1, 2020)
+ - apple,j313 # MacBook Air (M1, 2020)
+ - const: apple,t8103
+ - const: apple,arm-platform
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml
index e55731f43c..2cd4e4a322 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml
+++ b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml
@@ -21,6 +21,7 @@ properties:
items:
- enum:
- netgear,r8000p
+ - tplink,archer-c2300-v1
- const: brcm,bcm4906
- const: brcm,bcm4908
diff --git a/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
index a2c63c8b1d..b369b374fc 100644
--- a/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
+++ b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -26,10 +26,7 @@ properties:
- const: simple-mfd
mboxes:
- $ref: '/schemas/types.yaml#/definitions/phandle'
- description: |
- Phandle to the firmware device's Mailbox.
- (See: ../mailbox/mailbox.txt for more information)
+ maxItems: 1
clocks:
type: object
@@ -64,6 +61,21 @@ properties:
- compatible
- "#reset-cells"
+ pwm:
+ type: object
+
+ properties:
+ compatible:
+ const: raspberrypi,firmware-poe-pwm
+
+ "#pwm-cells":
+ # See pwm.yaml in this directory for a description of the cells format.
+ const: 2
+
+ required:
+ - compatible
+ - "#pwm-cells"
+
additionalProperties: false
required:
@@ -87,5 +99,10 @@ examples:
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
+
+ pwm: pwm {
+ compatible = "raspberrypi,firmware-poe-pwm";
+ #pwm-cells = <2>;
+ };
};
...
diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml
index 26b886b20b..f3c7249c73 100644
--- a/dts/Bindings/arm/cpus.yaml
+++ b/dts/Bindings/arm/cpus.yaml
@@ -85,6 +85,8 @@ properties:
compatible:
enum:
+ - apple,icestorm
+ - apple,firestorm
- arm,arm710t
- arm,arm720t
- arm,arm740t
@@ -256,13 +258,11 @@ properties:
where voltage is in V, frequency is in MHz.
power-domains:
- $ref: '/schemas/types.yaml#/definitions/phandle-array'
description:
List of phandles and PM domain specifiers, as defined by bindings of the
PM domain provider (see also ../power_domain.txt).
power-domain-names:
- $ref: '/schemas/types.yaml#/definitions/string-array'
description:
A list of power domain name strings sorted in the same order as the
power-domains property.
diff --git a/dts/Bindings/arm/ete.yaml b/dts/Bindings/arm/ete.yaml
new file mode 100644
index 0000000000..7f9b2d1e11
--- /dev/null
+++ b/dts/Bindings/arm/ete.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright 2021, Arm Ltd
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/ete.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ARM Embedded Trace Extensions
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+description: |
+ Arm Embedded Trace Extension(ETE) is a per CPU trace component that
+ allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
+ architecture and has extended support for future architecture changes.
+ The trace generated by the ETE could be stored via legacy CoreSight
+ components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
+ Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
+ legacy CoreSight components, a node must be listed per instance, along
+ with any optional connection graph as per the coresight bindings.
+ See bindings/arm/coresight.txt.
+
+properties:
+ $nodename:
+ pattern: "^ete([0-9a-f]+)$"
+ compatible:
+ items:
+ - const: arm,embedded-trace-extension
+
+ cpu:
+ description: |
+ Handle to the cpu this ETE is bound to.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ out-ports:
+ description: |
+ Output connections from the ETE to legacy CoreSight trace bus.
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port:
+ description: Output connection from the ETE to legacy CoreSight Trace bus.
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - cpu
+
+additionalProperties: false
+
+examples:
+
+# An ETE node without legacy CoreSight connections
+ - |
+ ete0 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu_0>;
+ };
+# An ETE node with legacy CoreSight connections
+ - |
+ ete1 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu_1>;
+
+ out-ports { /* legacy coresight connection */
+ port {
+ ete1_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
index 297c87f45d..e3c50f231d 100644
--- a/dts/Bindings/arm/fsl.yaml
+++ b/dts/Bindings/arm/fsl.yaml
@@ -617,6 +617,7 @@ properties:
- kam,imx7d-flex-concentrator # Kamstrup OMNIA Flex Concentrator
- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
+ - remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
@@ -688,6 +689,14 @@ properties:
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
+ - description: Engicam i.Core MX8M Mini SoM based boards
+ items:
+ - enum:
+ - engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core MX8M Mini C.TOUCH 2.0
+ - engicam,icore-mx8mm-edimm2.2 # i.MX8MM Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
+ - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core MX8M Mini SoM
+ - const: fsl,imx8mm
+
- description: Kontron BL i.MX8MM (N801X S) Board
items:
- const: kontron,imx8mm-n801x-s
@@ -733,6 +742,7 @@ properties:
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- google,imx8mq-phanbell # Google Coral Edge TPU
+ - kontron,pitx-imx8m # Kontron pITX-imx8m Board
- purism,librem5-devkit # Purism Librem5 devkit
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
@@ -755,6 +765,12 @@ properties:
- const: zii,imx8mq-ultra
- const: fsl,imx8mq
+ - description: i.MX8QM based Boards
+ items:
+ - enum:
+ - fsl,imx8qm-mek # i.MX8QM MEK Board
+ - const: fsl,imx8qm
+
- description: i.MX8QXP based Boards
items:
- enum:
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller.txt b/dts/Bindings/arm/marvell/cp110-system-controller.txt
index a21f770959..0705e765f4 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller.txt
@@ -142,8 +142,8 @@ mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(
mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
-mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)
-mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)
+mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)
+mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)
mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)
diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml
index 93b3bdf6ea..aff57a8c8c 100644
--- a/dts/Bindings/arm/mediatek.yaml
+++ b/dts/Bindings/arm/mediatek.yaml
@@ -118,6 +118,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8195-evb
+ - const: mediatek,mt8195
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
@@ -125,6 +129,38 @@ properties:
- google,krane-sku176
- const: google,krane
- const: mediatek,mt8183
+ - description: Google Damu (ASUS Chromebook Flip CM3)
+ items:
+ - const: google,damu
+ - const: mediatek,mt8183
+ - description: Google Juniper (Acer Chromebook Spin 311)
+ items:
+ - const: google,juniper-sku16
+ - const: google,juniper
+ - const: mediatek,mt8183
+ - description: Google Kakadu (ASUS Chromebook Detachable CM3)
+ items:
+ - const: google,kakadu-rev3
+ - const: google,kakadu-rev2
+ - const: google,kakadu
+ - const: mediatek,mt8183
+ - description: Google Kodama (Lenovo 10e Chromebook Tablet)
+ items:
+ - enum:
+ - google,kodama-sku16
+ - google,kodama-sku272
+ - google,kodama-sku288
+ - google,kodama-sku32
+ - const: google,kodama
+ - const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8183-pumpkin
+ - const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8516-pumpkin
+ - const: mediatek,mt8516
additionalProperties: true
diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
index d8c9108c3b..78c5073398 100644
--- a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
@@ -13,6 +13,7 @@ Required Properties:
- "mediatek,mt6779-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
+ - "mediatek,mt8167-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- "mediatek,mt8183-mmsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/msm/qcom,llcc.yaml b/dts/Bindings/arm/msm/qcom,llcc.yaml
index c299dc907f..62fcbd8833 100644
--- a/dts/Bindings/arm/msm/qcom,llcc.yaml
+++ b/dts/Bindings/arm/msm/qcom,llcc.yaml
@@ -22,6 +22,7 @@ properties:
compatible:
enum:
- qcom,sc7180-llcc
+ - qcom,sc7280-llcc
- qcom,sdm845-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
diff --git a/dts/Bindings/arm/mstar/mstar.yaml b/dts/Bindings/arm/mstar/mstar.yaml
index 61d08c473e..a316eef1b7 100644
--- a/dts/Bindings/arm/mstar/mstar.yaml
+++ b/dts/Bindings/arm/mstar/mstar.yaml
@@ -24,6 +24,7 @@ properties:
items:
- enum:
- honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
+ - m5stack,unitv2 # M5Stack UnitV2
- const: mstar,infinity2m
- description: infinity3 boards
diff --git a/dts/Bindings/arm/npcm/npcm.txt b/dts/Bindings/arm/npcm/npcm.txt
deleted file mode 100644
index 2d87d9ecea..0000000000
--- a/dts/Bindings/arm/npcm/npcm.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-NPCM Platforms Device Tree Bindings
------------------------------------
-NPCM750 SoC
-Required root node properties:
- - compatible = "nuvoton,npcm750";
-
diff --git a/dts/Bindings/arm/npcm/npcm.yaml b/dts/Bindings/arm/npcm/npcm.yaml
new file mode 100644
index 0000000000..95e5137808
--- /dev/null
+++ b/dts/Bindings/arm/npcm/npcm.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NPCM Platforms Device Tree Bindings
+
+maintainers:
+ - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: WPCM450 based boards
+ items:
+ - enum:
+ - supermicro,x9sci-ln4f-bmc # Supermicro X9SCI-LN4F server's BMC
+ - const: nuvoton,wpcm450
+
+ - description: NPCM750 based boards
+ items:
+ - enum:
+ - nuvoton,npcm750-evb # NPCM750 evaluation board
+ - const: nuvoton,npcm750
+
+additionalProperties: true
diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml
index 174134f920..9b27e991bd 100644
--- a/dts/Bindings/arm/qcom.yaml
+++ b/dts/Bindings/arm/qcom.yaml
@@ -37,6 +37,7 @@ description: |
msm8994
msm8996
sc7180
+ sc7280
sdm630
sdm660
sdm845
@@ -137,6 +138,16 @@ properties:
- const: qcom,msm8916
- items:
+ - enum:
+ - sony,karin_windy
+ - sony,karin-row
+ - sony,satsuki-row
+ - sony,sumire-row
+ - sony,suzuran-row
+ - qcom,msm8994
+ - const: qcom,apq8094
+
+ - items:
- const: qcom,msm8996-mtp
- items:
@@ -166,16 +177,24 @@ properties:
- items:
- enum:
+ - qcom,sc7280-idp
+ - const: qcom,sc7280
+
+ - items:
+ - enum:
- xiaomi,lavender
- const: qcom,sdm660
- items:
- enum:
- qcom,sdx55-mtp
+ - qcom,sdx55-telit-fn980-tlb
+ - qcom,sdx55-t55
- const: qcom,sdx55
- items:
- enum:
+ - qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
@@ -187,6 +206,7 @@ properties:
- items:
- enum:
+ - qcom,sm8350-hdk
- qcom,sm8350-mtp
- const: qcom,sm8350
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index c3036f95c7..4a6f772c10 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -134,6 +134,7 @@ properties:
- friendlyarm,nanopi-m4
- friendlyarm,nanopi-m4b
- friendlyarm,nanopi-neo4
+ - friendlyarm,nanopi-r4s
- const: rockchip,rk3399
- description: GeekBuying GeekBox
diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml
index e7525a3395..9a77ab74be 100644
--- a/dts/Bindings/arm/stm32/stm32.yaml
+++ b/dts/Bindings/arm/stm32/stm32.yaml
@@ -53,6 +53,10 @@ properties:
- const: st,stm32h743
- items:
- enum:
+ - st,stm32h750i-art-pi
+ - const: st,stm32h750
+ - items:
+ - enum:
- shiratech,stm32mp157a-iot-box # IoT Box
- shiratech,stm32mp157a-stinger96 # Stinger96
- st,stm32mp157c-ed1
@@ -64,6 +68,23 @@ properties:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
+
+ - description: Engicam i.Core STM32MP1 SoM based Boards
+ items:
+ - enum:
+ - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
+ - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
+ - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
+ - const: st,stm32mp157
+
+ - description: Engicam MicroGEA STM32MP1 SoM based Boards
+ items:
+ - enum:
+ - engicam,microgea-stm32mp1-microdev2.0
+ - engicam,microgea-stm32mp1-microdev2.0-of7
+ - const: engicam,microgea-stm32mp1
+ - const: st,stm32mp157
+
- description: Octavo OSD32MP15x System-in-Package based boards
items:
- enum:
diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml
index 08607c7ec1..ac750025a2 100644
--- a/dts/Bindings/arm/sunxi.yaml
+++ b/dts/Bindings/arm/sunxi.yaml
@@ -802,6 +802,11 @@ properties:
- const: tbs-biometrics,a711
- const: allwinner,sun8i-a83t
+ - description: Topwise A721 Tablet
+ items:
+ - const: topwise,a721
+ - const: allwinner,sun4i-a10
+
- description: Utoo P66
items:
- const: utoo,p66
diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml
index c6e1c1e63e..c5aa362e40 100644
--- a/dts/Bindings/arm/ti/k3.yaml
+++ b/dts/Bindings/arm/ti/k3.yaml
@@ -23,6 +23,8 @@ properties:
items:
- enum:
- ti,am654-evm
+ - siemens,iot2050-basic
+ - siemens,iot2050-advanced
- const: ti,am654
- description: K3 J721E SoC
@@ -33,6 +35,13 @@ properties:
items:
- const: ti,j7200
+ - description: K3 AM642 SoC
+ items:
+ - enum:
+ - ti,am642-evm
+ - ti,am642-sk
+ - const: ti,am642
+
additionalProperties: true
...
diff --git a/dts/Bindings/arm/trbe.yaml b/dts/Bindings/arm/trbe.yaml
new file mode 100644
index 0000000000..4402d7bfd1
--- /dev/null
+++ b/dts/Bindings/arm/trbe.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright 2021, Arm Ltd
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ARM Trace Buffer Extensions
+
+maintainers:
+ - Anshuman Khandual <anshuman.khandual@arm.com>
+
+description: |
+ Arm Trace Buffer Extension (TRBE) is a per CPU component
+ for storing trace generated on the CPU to memory. It is
+ accessed via CPU system registers. The software can verify
+ if it is permitted to use the component by checking the
+ TRBIDR register.
+
+properties:
+ $nodename:
+ const: "trbe"
+ compatible:
+ items:
+ - const: arm,trace-buffer-extension
+
+ interrupts:
+ description: |
+ Exactly 1 PPI must be listed. For heterogeneous systems where
+ TRBE is only supported on a subset of the CPUs, please consult
+ the arm,gic-v3 binding for details on describing a PPI partition.
+ maxItems: 1
+
+required:
+ - compatible
+ - interrupts
+
+additionalProperties: false
+
+examples:
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ trbe {
+ compatible = "arm,trace-buffer-extension";
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
diff --git a/dts/Bindings/ata/ahci-ceva.txt b/dts/Bindings/ata/ahci-ceva.txt
index 7561cc4de3..bfb6da0281 100644
--- a/dts/Bindings/ata/ahci-ceva.txt
+++ b/dts/Bindings/ata/ahci-ceva.txt
@@ -38,6 +38,8 @@ Required properties:
Optional properties:
- ceva,broken-gen2: limit to gen1 speed instead of gen2.
+ - phys: phandle for the PHY device
+ - resets: phandle to the reset controller for the SATA IP
Examples:
ahci@fd0c0000 {
@@ -56,4 +58,6 @@ Examples:
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
+ phys = <&psgtr 1 PHY_TYPE_SATA 1 1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
};
diff --git a/dts/Bindings/ata/nvidia,tegra-ahci.yaml b/dts/Bindings/ata/nvidia,tegra-ahci.yaml
new file mode 100644
index 0000000000..a75e9a8f53
--- /dev/null
+++ b/dts/Bindings/ata/nvidia,tegra-ahci.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra AHCI SATA Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra124-ahci
+ - nvidia,tegra132-ahci
+ - nvidia,tegra210-ahci
+ - nvidia,tegra186-ahci
+
+ reg:
+ minItems: 2
+ maxItems: 3
+ items:
+ - description: AHCI registers
+ - description: SATA configuration and IPFS registers
+ - description: SATA AUX registers
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: sata
+ - const: sata-oob
+
+ clocks:
+ maxItems: 2
+
+ reset-names:
+ minItems: 2
+ items:
+ - const: sata
+ - const: sata-cold
+ - const: sata-oob
+
+ resets:
+ minItems: 2
+ maxItems: 3
+
+ iommus:
+ maxItems: 1
+
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: write
+
+ interconnects:
+ maxItems: 2
+
+ power-domains:
+ items:
+ - description: SAX power-domain
+
+ phy-names:
+ items:
+ - const: sata-0
+
+ phys:
+ maxItems: 1
+
+ hvdd-supply:
+ description: SATA HVDD regulator supply.
+
+ vddio-supply:
+ description: SATA VDDIO regulator supply.
+
+ avdd-supply:
+ description: SATA AVDD regulator supply.
+
+ target-5v-supply:
+ description: SATA 5V power regulator supply.
+
+ target-12v-supply:
+ description: SATA 12V power regulator supply.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+ - reset-names
+ - resets
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra124-ahci
+ - nvidia,tegra132-ahci
+ then:
+ properties:
+ reg:
+ maxItems: 2
+ reset-names:
+ minItems: 3
+ resets:
+ minItems: 3
+ required:
+ - phys
+ - phy-names
+ - hvdd-supply
+ - vddio-supply
+ - avdd-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra210-ahci
+ then:
+ properties:
+ reg:
+ minItems: 3
+ reset-names:
+ minItems: 3
+ resets:
+ minItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra186-ahci
+ then:
+ properties:
+ reg:
+ minItems: 3
+ reset-names:
+ maxItems: 2
+ resets:
+ maxItems: 2
+ required:
+ - iommus
+ - interconnect-names
+ - interconnects
+ - power-domains
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/reset/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sata@70020000 {
+ compatible = "nvidia,tegra210-ahci";
+ reg = <0x70027000 0x00002000>, /* AHCI */
+ <0x70020000 0x00007000>, /* SATA */
+ <0x70001100 0x00010000>; /* SATA AUX */
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SATA>,
+ <&tegra_car TEGRA210_CLK_SATA_OOB>;
+ clock-names = "sata", "sata-oob";
+ resets = <&tegra_car 124>,
+ <&tegra_car 129>,
+ <&tegra_car 123>;
+ reset-names = "sata", "sata-cold", "sata-oob";
+ };
diff --git a/dts/Bindings/ata/nvidia,tegra124-ahci.txt b/dts/Bindings/ata/nvidia,tegra124-ahci.txt
deleted file mode 100644
index 12ab2f723e..0000000000
--- a/dts/Bindings/ata/nvidia,tegra124-ahci.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-Tegra SoC SATA AHCI controller
-
-Required properties :
-- compatible : Must be one of:
- - Tegra124 : "nvidia,tegra124-ahci"
- - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
- - Tegra210 : "nvidia,tegra210-ahci"
-- reg : Should contain 2 entries:
- - AHCI register set (SATA BAR5)
- - SATA register set
-- interrupts : Defines the interrupt used by SATA
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- - sata
- - sata-oob
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
- - sata
- - sata-oob
- - sata-cold
-- phys : Must contain an entry for each entry in phy-names.
- See ../phy/phy-bindings.txt for details.
-- phy-names : Must include the following entries:
- - For Tegra124 and Tegra132:
- - sata-phy : XUSB PADCTL SATA PHY
-- For Tegra124 and Tegra132:
- - hvdd-supply : Defines the SATA HVDD regulator
- - vddio-supply : Defines the SATA VDDIO regulator
- - avdd-supply : Defines the SATA AVDD regulator
- - target-5v-supply : Defines the SATA 5V power regulator
- - target-12v-supply : Defines the SATA 12V power regulator
-
-Optional properties:
-- reg :
- - AUX register set
-- clock-names :
- - cml1 :
- cml1 clock should be defined here if the PHY driver
- doesn't manage them. If it does, they should not be.
-- phy-names :
- - For T210:
- - sata-phy
diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
index e9c4cf834a..e5d9d45dab 100644
--- a/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
+++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
@@ -44,7 +44,7 @@ examples:
- |
clk@1c20000 {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1";
+ compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "osc24M";
diff --git a/dts/Bindings/clock/armada3700-tbg-clock.txt b/dts/Bindings/clock/armada3700-tbg-clock.txt
index 0ba1d83ff3..ed1df32c57 100644
--- a/dts/Bindings/clock/armada3700-tbg-clock.txt
+++ b/dts/Bindings/clock/armada3700-tbg-clock.txt
@@ -1,6 +1,6 @@
* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
-Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
+Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
used as parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the
diff --git a/dts/Bindings/clock/imx8qxp-lpcg.yaml b/dts/Bindings/clock/imx8qxp-lpcg.yaml
index 940486ef10..0f6fe365eb 100644
--- a/dts/Bindings/clock/imx8qxp-lpcg.yaml
+++ b/dts/Bindings/clock/imx8qxp-lpcg.yaml
@@ -107,8 +107,8 @@ examples:
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
- <&sdhc0_lpcg IMX_LPCG_CLK_0>,
- <&sdhc0_lpcg IMX_LPCG_CLK_5>;
- clock-names = "ipg", "per", "ahb";
+ <&sdhc0_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
diff --git a/dts/Bindings/clock/mediatek,mt7621-sysc.yaml b/dts/Bindings/clock/mediatek,mt7621-sysc.yaml
new file mode 100644
index 0000000000..915f84efd7
--- /dev/null
+++ b/dts/Bindings/clock/mediatek,mt7621-sysc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description: |
+ The MT7621 has a PLL controller from where the cpu clock is provided
+ as well as derived clocks for the bus and the peripherals. It also
+ can gate SoC device clocks.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in:
+ [1]: <include/dt-bindings/clock/mt7621-clk.h>.
+
+ The clocks are provided inside a system controller node.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt7621-sysc
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+ const: 1
+
+ ralink,memctl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle of syscon used to control memory registers
+
+ clock-output-names:
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - ralink,memctl
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7621-clk.h>
+
+ sysc: sysc@0 {
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
+ };
diff --git a/dts/Bindings/clock/milbeaut-clock.yaml b/dts/Bindings/clock/milbeaut-clock.yaml
index 0e8b077104..6d39344d2b 100644
--- a/dts/Bindings/clock/milbeaut-clock.yaml
+++ b/dts/Bindings/clock/milbeaut-clock.yaml
@@ -18,10 +18,12 @@ description: |
properties:
compatible:
- oneOf:
- - items:
- - enum:
- - socionext,milbeaut-m10v-ccu
+ enum:
+ - socionext,milbeaut-m10v-ccu
+
+ reg:
+ maxItems: 1
+
clocks:
maxItems: 1
description: external clock
@@ -41,7 +43,7 @@ examples:
# Clock controller node:
- |
m10v-clk-ctrl@1d021000 {
- compatible = "socionext,milbeaut-m10v-clk-ccu";
+ compatible = "socionext,milbeaut-m10v-ccu";
reg = <0x1d021000 0x4000>;
#clock-cells = <1>;
clocks = <&clki40mhz>;
diff --git a/dts/Bindings/clock/qcom,gcc-sdm845.yaml b/dts/Bindings/clock/qcom,gcc-sdm845.yaml
new file mode 100644
index 0000000000..d902f137ab
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-sdm845.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SDM845
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-sdm845.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sdm845
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board active XO source
+ - description: Sleep clock source
+ - description: PCIE 0 Pipe clock source
+ - description: PCIE 1 Pipe clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: sleep_clk
+ - const: pcie_0_pipe_clk
+ - const: pcie_1_pipe_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ # Example for GCC for SDM845:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sdm845";
+ reg = <0x100000 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_lane>,
+ <&pcie1_lane>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc.yaml b/dts/Bindings/clock/qcom,gcc.yaml
index ee0467fb5e..490edad258 100644
--- a/dts/Bindings/clock/qcom,gcc.yaml
+++ b/dts/Bindings/clock/qcom,gcc.yaml
@@ -32,7 +32,6 @@ description: |
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
- - dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:
@@ -52,7 +51,6 @@ properties:
- qcom,gcc-mdm9615
- qcom,gcc-sdm630
- qcom,gcc-sdm660
- - qcom,gcc-sdm845
'#clock-cells':
const: 1
diff --git a/dts/Bindings/clock/rockchip,rk3568-cru.yaml b/dts/Bindings/clock/rockchip,rk3568-cru.yaml
new file mode 100644
index 0000000000..b2c2609782
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3568-cru.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP rk3568 Family Clock Control Module Binding
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3568 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+ (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+ used in device tree sources.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-cru
+ - rockchip,rk3568-pmucru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ pmucru: clock-controller@fdd00000 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0xfdd00000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ cru: clock-controller@fdd20000 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0xfdd20000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/connector/usb-connector.yaml b/dts/Bindings/connector/usb-connector.yaml
index b6daedd625..32509b9814 100644
--- a/dts/Bindings/connector/usb-connector.yaml
+++ b/dts/Bindings/connector/usb-connector.yaml
@@ -197,6 +197,16 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
+ slow-charger-loop:
+ description: Allows PMIC charger loops which are slow(i.e. cannot meet the 15ms deadline) to
+ still comply to pSnkStby i.e Maximum power that can be consumed by sink while in Sink Standby
+ state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification
+ Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W -
+ 5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during
+ SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during
+ SNK_READY for non-pd link.
+ type: boolean
+
required:
- compatible
diff --git a/dts/Bindings/counter/interrupt-counter.yaml b/dts/Bindings/counter/interrupt-counter.yaml
new file mode 100644
index 0000000000..fd075d1046
--- /dev/null
+++ b/dts/Bindings/counter/interrupt-counter.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Interrupt counter
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+description: |
+ A generic interrupt counter to measure interrupt frequency. It was developed
+ and used for agricultural devices to measure rotation speed of wheels or
+ other tools. Since the direction of rotation is not important, only one
+ signal line is needed.
+ Interrupts or gpios are required. If both are defined, the interrupt will
+ take precedence for counting interrupts.
+
+properties:
+ compatible:
+ const: interrupt-counter
+
+ interrupts:
+ maxItems: 1
+
+ gpios:
+ maxItems: 1
+
+required:
+ - compatible
+
+anyOf:
+ - required: [ interrupts-extended ]
+ - required: [ interrupts ]
+ - required: [ gpios ]
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ counter-0 {
+ compatible = "interrupt-counter";
+ interrupts-extended = <&gpio 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ counter-1 {
+ compatible = "interrupt-counter";
+ gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ counter-2 {
+ compatible = "interrupt-counter";
+ interrupts-extended = <&gpio 2 IRQ_TYPE_EDGE_RISING>;
+ gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+ };
+
+...
diff --git a/dts/Bindings/crypto/ti,sa2ul.yaml b/dts/Bindings/crypto/ti,sa2ul.yaml
index 1d48ac712b..a410d2cedd 100644
--- a/dts/Bindings/crypto/ti,sa2ul.yaml
+++ b/dts/Bindings/crypto/ti,sa2ul.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- ti,j721e-sa2ul
- ti,am654-sa2ul
+ - ti,am64-sa2ul
reg:
maxItems: 1
@@ -45,6 +46,18 @@ properties:
description:
Address translation for the possible RNG child node for SA2UL
+ clocks:
+ items:
+ - description: Clock used by PKA
+ - description: Main Input Clock
+ - description: Clock used by rng
+
+ clock-names:
+ items:
+ - const: pka_in_clk
+ - const: x1_clk
+ - const: x2_clk
+
patternProperties:
"^rng@[a-f0-9]+$":
type: object
@@ -57,7 +70,16 @@ required:
- power-domains
- dmas
- dma-names
- - dma-coherent
+
+if:
+ properties:
+ compatible:
+ enum:
+ - ti,j721e-sa2ul
+ - ti,am654-sa2ul
+then:
+ required:
+ - dma-coherent
additionalProperties: false
diff --git a/dts/Bindings/ddr/lpddr3.txt b/dts/Bindings/ddr/lpddr3.txt
index a0eda35a86..b221e653d3 100644
--- a/dts/Bindings/ddr/lpddr3.txt
+++ b/dts/Bindings/ddr/lpddr3.txt
@@ -12,6 +12,9 @@ Required properties:
Optional properties:
+- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
+- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
+
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
@@ -49,6 +52,8 @@ samsung_K3QF2F20DB: lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
+ manufacturer-id = <1>;
+ revision-id = <123 234>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt
index a10d1f6d85..ac189dd82b 100644
--- a/dts/Bindings/devfreq/rk3399_dmc.txt
+++ b/dts/Bindings/devfreq/rk3399_dmc.txt
@@ -12,6 +12,8 @@ Required properties:
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
+- rockchip,pmu: Phandle to the syscon managing the "PMU general register
+ files".
Optional properties:
- interrupts: The CPU interrupt number. The interrupt specifier
@@ -77,24 +79,23 @@ Following properties relate to DDR timing:
- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
the DRAM side driver strength in ohms. Default
- value is DDR3_DS_40ohm.
+ value is 40.
- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
- is DDR3_ODT_120ohm.
+ is 120.
- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
the phy side CA line (incluing command line,
address line and clock line) driver strength.
- Default value is PHY_DRV_ODT_40.
+ Default value is 40.
- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is PHY_DRV_ODT_40.
+ driver strength. Default value is 40.
- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
- the PHY side ODT strength. Default value is
- PHY_DRV_ODT_240.
+ the PHY side ODT strength. Default value is 240.
- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
then ODT disable frequency in MHz (Mega Hz).
@@ -104,25 +105,23 @@ Following properties relate to DDR timing:
- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
the DRAM side driver strength in ohms. Default
- value is LP3_DS_34ohm.
+ value is 34.
- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
- is LP3_ODT_240ohm.
+ is 240.
- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side CA line (including command line,
address line and clock line) driver strength.
- Default value is PHY_DRV_ODT_40.
+ Default value is 40.
- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is
- PHY_DRV_ODT_40.
+ driver strength. Default value is 40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
- the phy side odt strength, default value is
- PHY_DRV_ODT_240.
+ the phy side odt strength, default value is 240.
- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
defines the ODT disable frequency in
@@ -132,32 +131,30 @@ Following properties relate to DDR timing:
- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
the DRAM side driver strength in ohms. Default
- value is LP4_PDDS_60ohm.
+ value is 60.
- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on DQS/DQ line strength in ohms.
- Default value is LP4_DQ_ODT_40ohm.
+ Default value is 40.
- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on CA line strength in ohms.
- Default value is LP4_CA_ODT_40ohm.
+ Default value is 40.
- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side CA line (including command address
- line) driver strength. Default value is
- PHY_DRV_ODT_40.
+ line) driver strength. Default value is 40.
- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side clock line and CS line driver
- strength. Default value is PHY_DRV_ODT_80.
+ strength. Default value is 80.
- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is PHY_DRV_ODT_80.
+ driver strength. Default value is 80.
- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
- the PHY side ODT strength. Default value is
- PHY_DRV_ODT_60.
+ the PHY side ODT strength. Default value is 60.
Example:
dmc_opp_table: dmc_opp_table {
@@ -193,23 +190,23 @@ Example:
rockchip,phy_dll_dis_freq = <125>;
rockchip,auto_pd_dis_freq = <666>;
rockchip,ddr3_odt_dis_freq = <333>;
- rockchip,ddr3_drv = <DDR3_DS_40ohm>;
- rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
- rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
+ rockchip,ddr3_drv = <40>;
+ rockchip,ddr3_odt = <120>;
+ rockchip,phy_ddr3_ca_drv = <40>;
+ rockchip,phy_ddr3_dq_drv = <40>;
+ rockchip,phy_ddr3_odt = <240>;
rockchip,lpddr3_odt_dis_freq = <333>;
- rockchip,lpddr3_drv = <LP3_DS_34ohm>;
- rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
- rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
+ rockchip,lpddr3_drv = <34>;
+ rockchip,lpddr3_odt = <240>;
+ rockchip,phy_lpddr3_ca_drv = <40>;
+ rockchip,phy_lpddr3_dq_drv = <40>;
+ rockchip,phy_lpddr3_odt = <240>;
rockchip,lpddr4_odt_dis_freq = <333>;
- rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
- rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
- rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
- rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
- rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
- rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
+ rockchip,lpddr4_drv = <60>;
+ rockchip,lpddr4_dq_odt = <40>;
+ rockchip,lpddr4_ca_odt = <40>;
+ rockchip,phy_lpddr4_ca_drv = <40>;
+ rockchip,phy_lpddr4_ck_cs_drv = <80>;
+ rockchip,phy_lpddr4_dq_drv = <80>;
+ rockchip,phy_lpddr4_odt = <60>;
};
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
index c13faf3e65..3a7d5d7317 100644
--- a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
+++ b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
@@ -73,7 +73,6 @@ properties:
clock-output-names:
description:
Name of the LCD pixel clock created.
- $ref: /schemas/types.yaml#/definitions/string-array
maxItems: 1
dmas:
diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
index b3e9992525..907fb47cc8 100644
--- a/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+++ b/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
@@ -12,8 +12,8 @@ description: |
and CEC.
These DT bindings follow the Synopsys DWC HDMI TX bindings defined
- in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
- the following device-specific properties.
+ in bridge/synopsys,dw-hdmi.yaml with the following device-specific
+ properties.
maintainers:
- Chen-Yu Tsai <wens@csie.org>
diff --git a/dts/Bindings/display/brcm,bcm2835-dsi0.yaml b/dts/Bindings/display/brcm,bcm2835-dsi0.yaml
index 55c6091999..32608578a3 100644
--- a/dts/Bindings/display/brcm,bcm2835-dsi0.yaml
+++ b/dts/Bindings/display/brcm,bcm2835-dsi0.yaml
@@ -77,12 +77,6 @@ examples:
clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
- pitouchscreen: panel@0 {
- compatible = "raspberrypi,touchscreen";
- reg = <0>;
-
- /* ... */
- };
};
...
diff --git a/dts/Bindings/display/bridge/analogix,anx7625.yaml b/dts/Bindings/display/bridge/analogix,anx7625.yaml
index c789784efe..ab48ab2f42 100644
--- a/dts/Bindings/display/bridge/analogix,anx7625.yaml
+++ b/dts/Bindings/display/bridge/analogix,anx7625.yaml
@@ -34,6 +34,15 @@ properties:
description: used for reset chip control, RESET_N pin B7.
maxItems: 1
+ vdd10-supply:
+ description: Regulator that provides the supply 1.0V power.
+
+ vdd18-supply:
+ description: Regulator that provides the supply 1.8V power.
+
+ vdd33-supply:
+ description: Regulator that provides the supply 3.3V power.
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -55,6 +64,9 @@ properties:
required:
- compatible
- reg
+ - vdd10-supply
+ - vdd18-supply
+ - vdd33-supply
- ports
additionalProperties: false
@@ -72,6 +84,9 @@ examples:
reg = <0x58>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
+ vdd10-supply = <&pp1000_mipibrdg>;
+ vdd18-supply = <&pp1800_mipibrdg>;
+ vdd33-supply = <&pp3300_mipibrdg>;
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/display/bridge/chipone,icn6211.yaml b/dts/Bindings/display/bridge/chipone,icn6211.yaml
new file mode 100644
index 0000000000..62c3bd4cb2
--- /dev/null
+++ b/dts/Bindings/display/bridge/chipone,icn6211.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
+
+maintainers:
+ - Jagan Teki <jagan@amarulasolutions.com>
+
+description: |
+ ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
+
+ It has a flexible configuration of MIPI DSI signal input and
+ produce RGB565, RGB666, RGB888 output format.
+
+properties:
+ compatible:
+ enum:
+ - chipone,icn6211
+
+ reg:
+ maxItems: 1
+ description: virtual channel number of a DSI peripheral
+
+ enable-gpios:
+ description: Bridge EN pin, chip is reset when EN is low.
+
+ vdd1-supply:
+ description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
+
+ vdd2-supply:
+ description: A 1.8V/2.5V/3.3V supply that power the PLL.
+
+ vdd3-supply:
+ description: A 1.8V/2.5V/3.3V supply that power the RGB output.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Video port for MIPI DSI input
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Video port for MIPI DPI output (panel or connector).
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@0 {
+ compatible = "chipone,icn6211";
+ reg = <0>;
+ enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_in_dsi: endpoint {
+ remote-endpoint = <&dsi_out_bridge>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_out_panel: endpoint {
+ remote-endpoint = <&panel_out_bridge>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/dw_hdmi.txt b/dts/Bindings/display/bridge/dw_hdmi.txt
deleted file mode 100644
index 33bf981fbe..0000000000
--- a/dts/Bindings/display/bridge/dw_hdmi.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Synopsys DesignWare HDMI TX Encoder
-===================================
-
-This document defines device tree properties for the Synopsys DesignWare HDMI
-TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
-specification by itself but is meant to be referenced by platform-specific
-device tree bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each property is required or optional.
-
-- reg: Memory mapped base address and length of the DWC HDMI TX registers.
-
-- reg-io-width: Width of the registers specified by the reg property. The
- value is expressed in bytes and must be equal to 1 or 4 if specified. The
- register width defaults to 1 if the property is not present.
-
-- interrupts: Reference to the DWC HDMI TX interrupt.
-
-- clocks: References to all the clocks specified in the clock-names property
- as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
-
-- clock-names: The DWC HDMI TX uses the following clocks.
-
- - "iahb" is the bus clock for either AHB and APB (mandatory).
- - "isfr" is the internal register configuration clock (mandatory).
- - "cec" is the HDMI CEC controller main clock (optional).
-
-- ports: The connectivity of the DWC HDMI TX with the rest of the system is
- expressed in using ports as specified in the device graph bindings defined
- in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
- is platform-specific.
diff --git a/dts/Bindings/display/bridge/lontium,lt8912b.yaml b/dts/Bindings/display/bridge/lontium,lt8912b.yaml
new file mode 100644
index 0000000000..735d0233a7
--- /dev/null
+++ b/dts/Bindings/display/bridge/lontium,lt8912b.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lontium LT8912B MIPI to HDMI Bridge
+
+maintainers:
+ - Adrien Grassein <adrien.grassein@gmail.com>
+
+description: |
+ The LT8912B is a bridge device which convert DSI to HDMI
+
+properties:
+ compatible:
+ enum:
+ - lontium,lt8912b
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to active high RESET pin.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Primary MIPI port for MIPI input
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes: true
+
+ required:
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ HDMI port, should be connected to a node compatible with the
+ hdmi-connector binding.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48>;
+ reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
deleted file mode 100644
index 3f60726511..0000000000
--- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Renesas Gen3 DWC HDMI TX Encoder
-================================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible : Shall contain one or more of
- - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
- - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
- - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
- - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
- - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
- - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
- HDMI TX
-
- When compatible with generic versions, nodes must list the SoC-specific
- version corresponding to the platform first, followed by the
- family-specific version.
-
-- reg: See dw_hdmi.txt.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
- corresponding to the video input of the controller and one port numbered 1
- corresponding to its HDMI output, and one port numbered 2 corresponding to
- sound input of the controller. Each port shall have a single endpoint.
-
-Optional properties:
-
-- power-domains: Shall reference the power domain that contains the DWC HDMI,
- if any.
-
-
-Example:
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- rcar_dw_hdmi0_sound_in: endpoint {
- remote-endpoint = <&hdmi_sound_out>;
- };
- };
- };
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- label = "HDMI0 OUT";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml b/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml
new file mode 100644
index 0000000000..0c9785c8db
--- /dev/null
+++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car DWC HDMI TX Encoder
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
+ - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
+ - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
+ - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
+ - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
+ - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
+ - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
+ - const: renesas,rcar-gen3-hdmi
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Parallel RGB input port
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: HDMI output port
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Sound input port
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ hdmi@fead0000 {
+ compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0xfead0000 0x10000>;
+ interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ rcar_dw_hdmi0_sound_in: endpoint {
+ remote-endpoint = <&hdmi_sound_out>;
+ };
+ };
+ };
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ label = "HDMI0 OUT";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml
new file mode 100644
index 0000000000..9be44a682e
--- /dev/null
+++ b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common Properties for Synopsys DesignWare HDMI TX Controller
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ This document defines device tree properties for the Synopsys DesignWare HDMI
+ TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
+ binding specification by itself but is meant to be referenced by device tree
+ bindings for the platform-specific integrations of the DWC HDMI TX.
+
+ When referenced from platform device tree bindings the properties defined in
+ this document are defined as follows. The platform device tree bindings are
+ responsible for defining whether each property is required or optional.
+
+properties:
+ reg:
+ maxItems: 1
+
+ reg-io-width:
+ description:
+ Width (in bytes) of the registers specified by the reg property.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 4]
+ default: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+ items:
+ - description: The bus clock for either AHB and APB
+ - description: The internal register configuration clock
+ additionalItems: true
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ - const: iahb
+ - const: isfr
+ additionalItems: true
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/display/fsl,lcdif.yaml b/dts/Bindings/display/fsl,lcdif.yaml
new file mode 100644
index 0000000000..a4c3064c77
--- /dev/null
+++ b/dts/Bindings/display/fsl,lcdif.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale/NXP i.MX LCD Interface (LCDIF)
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+ - Stefan Agner <stefan@agner.ch>
+
+description: |
+ (e)LCDIF display controller found in the Freescale/NXP i.MX SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,imx23-lcdif
+ - fsl,imx28-lcdif
+ - fsl,imx6sx-lcdif
+ - items:
+ - enum:
+ - fsl,imx6sl-lcdif
+ - fsl,imx6sll-lcdif
+ - fsl,imx6ul-lcdif
+ - fsl,imx7d-lcdif
+ - fsl,imx8mm-lcdif
+ - fsl,imx8mq-lcdif
+ - const: fsl,imx6sx-lcdif
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Pixel clock
+ - description: Bus clock
+ - description: Display AXI clock
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: pix
+ - const: axi
+ - const: disp_axi
+ minItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The LCDIF output port
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - port
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-lcdif
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 3
+ clock-names:
+ minItems: 2
+ maxItems: 3
+ required:
+ - clock-names
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6sx-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display-controller@2220000 {
+ compatible = "fsl,imx6sx-lcdif";
+ reg = <0x02220000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
+ <&clks IMX6SX_CLK_LCDIF_APB>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pix", "axi", "disp_axi";
+
+ port {
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml b/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml
new file mode 100644
index 0000000000..af7fe9c4d1
--- /dev/null
+++ b/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DWC HDMI TX Encoder
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6dl-hdmi
+ - fsl,imx6q-hdmi
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ gpr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the iomuxc-gpr region containing the HDMI multiplexer control
+ register.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ This device has four video ports, corresponding to the four inputs of the
+ HDMI multiplexer. Each port shall have a single endpoint.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: First input of the HDMI multiplexer
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Second input of the HDMI multiplexer
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Third input of the HDMI multiplexer
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Fourth input of the HDMI multiplexer
+
+ anyOf:
+ - required:
+ - port@0
+ - required:
+ - port@1
+ - required:
+ - port@2
+ - required:
+ - port@3
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpr
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+
+ hdmi: hdmi@120000 {
+ reg = <0x00120000 0x9000>;
+ interrupts = <0 115 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
+ <&clks IMX6QDL_CLK_HDMI_ISFR>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_hdmi>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/imx/hdmi.txt b/dts/Bindings/display/imx/hdmi.txt
deleted file mode 100644
index 6d021e71c9..0000000000
--- a/dts/Bindings/display/imx/hdmi.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Freescale i.MX6 DWC HDMI TX Encoder
-===================================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
-- reg: See dw_hdmi.txt.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
- numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
- Each port shall have a single endpoint.
-- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
- multiplexer control register.
-
-Optional properties
-
-- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
- or the functionally-reduced I2C master contained in the DWC HDMI. When
- connected to a system I2C master this property contains a phandle to that
- I2C master controller.
-
-
-Example:
-
- gpr: iomuxc-gpr@20e0000 {
- /* ... */
- };
-
- hdmi: hdmi@120000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-hdmi";
- reg = <0x00120000 0x9000>;
- interrupts = <0 115 0x04>;
- gpr = <&gpr>;
- clocks = <&clks 123>, <&clks 124>;
- clock-names = "iahb", "isfr";
- ddc-i2c-bus = <&i2c2>;
-
- port@0 {
- reg = <0>;
-
- hdmi_mux_0: endpoint {
- remote-endpoint = <&ipu1_di0_hdmi>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi_mux_1: endpoint {
- remote-endpoint = <&ipu1_di1_hdmi>;
- };
- };
- };
diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt
index 93b160df3e..fbb59c9ddd 100644
--- a/dts/Bindings/display/mediatek/mediatek,disp.txt
+++ b/dts/Bindings/display/mediatek/mediatek,disp.txt
@@ -64,7 +64,7 @@ Required properties (DMA function blocks):
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
- iommus: Should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
Optional properties (RDMA function blocks):
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.yaml b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
index 6cdb734c91..dd2896a40f 100644
--- a/dts/Bindings/display/mediatek/mediatek,dpi.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
@@ -22,6 +22,7 @@ properties:
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
+ - mediatek,mt8192-dpi
reg:
maxItems: 1
@@ -50,15 +51,10 @@ properties:
- const: sleep
port:
- type: object
+ $ref: /schemas/graph.yaml#/properties/port
description:
- Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached HDMI or LVDS encoder chip.
-
- properties:
- endpoint:
- type: object
+ Output port node. This port should be connected to the input port of an
+ attached HDMI or LVDS encoder chip.
required:
- compatible
diff --git a/dts/Bindings/display/msm/dpu.txt b/dts/Bindings/display/msm/dpu.txt
index 551ae26f60..586e6eac5b 100644
--- a/dts/Bindings/display/msm/dpu.txt
+++ b/dts/Bindings/display/msm/dpu.txt
@@ -2,14 +2,14 @@ Qualcomm Technologies, Inc. DPU KMS
Description:
-Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc.
The DPU display controller is found in SDM845 SoC.
MDSS:
Required properties:
- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
-- reg: physical base address and length of contoller's registers.
+- reg: physical base address and length of controller's registers.
- reg-names: register region names. The following region is required:
* "mdss"
- power-domains: a power domain consumer specifier according to
diff --git a/dts/Bindings/display/mxsfb.txt b/dts/Bindings/display/mxsfb.txt
deleted file mode 100644
index c985871c46..0000000000
--- a/dts/Bindings/display/mxsfb.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-* Freescale MXS LCD Interface (LCDIF)
-
-New bindings:
-=============
-Required properties:
-- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
- Should be "fsl,imx28-lcdif" for i.MX28.
- Should be "fsl,imx6sx-lcdif" for i.MX6SX.
- Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
-- reg: Address and length of the register set for LCDIF
-- interrupts: Should contain LCDIF interrupt
-- clocks: A list of phandle + clock-specifier pairs, one for each
- entry in 'clock-names'.
-- clock-names: A list of clock names. For MXSFB it should contain:
- - "pix" for the LCDIF block clock
- - (MX6SX-only) "axi", "disp_axi" for the bus interface clock
-
-Required sub-nodes:
- - port: The connection to an encoder chip.
-
-Example:
-
- lcdif1: display-controller@2220000 {
- compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
- reg = <0x02220000 0x4000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
- <&clks IMX6SX_CLK_LCDIF_APB>,
- <&clks IMX6SX_CLK_DISPLAY_AXI>;
- clock-names = "pix", "axi", "disp_axi";
-
- port {
- parallel_out: endpoint {
- remote-endpoint = <&panel_in_parallel>;
- };
- };
- };
-
-Deprecated bindings:
-====================
-Required properties:
-- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
- Should be "fsl,imx28-lcdif" for i.MX28.
-- reg: Address and length of the register set for LCDIF
-- interrupts: Should contain LCDIF interrupts
-- display: phandle to display node (see below for details)
-
-* display node
-
-Required properties:
-- bits-per-pixel: <16> for RGB565, <32> for RGB888/666.
-- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>.
-
-Required sub-node:
-- display-timings: Refer to binding doc display-timing.txt for details.
-
-Examples:
-
-lcdif@80030000 {
- compatible = "fsl,imx28-lcdif";
- reg = <0x80030000 2000>;
- interrupts = <38 86>;
-
- display: display {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33500000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <164>;
- hback-porch = <89>;
- hsync-len = <10>;
- vback-porch = <23>;
- vfront-porch = <10>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
-};
diff --git a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml
index 6960036975..c45c92a3d4 100644
--- a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml
+++ b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml
@@ -47,7 +47,6 @@ examples:
spi-max-frequency = <3125000>;
spi-3wire;
- spi-cs-high;
reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
diff --git a/dts/Bindings/display/panel/panel-dpi.yaml b/dts/Bindings/display/panel/panel-dpi.yaml
index 0cd74c8dab..dae0676b5c 100644
--- a/dts/Bindings/display/panel/panel-dpi.yaml
+++ b/dts/Bindings/display/panel/panel-dpi.yaml
@@ -40,7 +40,7 @@ additionalProperties: false
examples:
- |
panel {
- compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+ compatible = "startek,startek-kd050c", "panel-dpi";
label = "osddisplay";
power-supply = <&vcc_supply>;
backlight = <&backlight>;
diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml
index 62b0d54d87..b3797ba269 100644
--- a/dts/Bindings/display/panel/panel-simple.yaml
+++ b/dts/Bindings/display/panel/panel-simple.yaml
@@ -161,6 +161,8 @@ properties:
# Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel
- innolux,g121x1-l03
# Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
+ - innolux,n116bca-ea1
+ # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
- innolux,n116bge
# InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
- innolux,n125hce-gn1
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
deleted file mode 100644
index 7d65c24fcd..0000000000
--- a/dts/Bindings/display/renesas,du.txt
+++ /dev/null
@@ -1,145 +0,0 @@
-* Renesas R-Car Display Unit (DU)
-
-Required Properties:
-
- - compatible: must be one of the following.
- - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU
- - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
- - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
- - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
- - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
- - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
- - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU
- - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
- - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU
- - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
- - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
- - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
- - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
- - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
- - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
- - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU
- - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
- - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
- - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU
- - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU
- - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
-
- - reg: the memory-mapped I/O registers base address and length
-
- - interrupts: Interrupt specifiers for the DU interrupts.
-
- - clocks: A list of phandles + clock-specifier pairs, one for each entry in
- the clock-names property.
- - clock-names: Name of the clocks. This property is model-dependent.
- - R8A7779 uses a single functional clock. The clock doesn't need to be
- named.
- - All other DU instances use one functional clock per channel The
- functional clocks must be named "du.x" with "x" being the channel
- numerical index.
- - In addition to the functional clocks, all DU versions also support
- externally supplied pixel clocks. Those clocks are optional. When
- supplied they must be named "dclkin.x" with "x" being the input clock
- numerical index.
-
- - renesas,cmms: A list of phandles to the CMM instances present in the SoC,
- one for each available DU channel. The property shall not be specified for
- SoCs that do not provide any CMM (such as V3M and V3H).
-
- - renesas,vsps: A list of phandle and channel index tuples to the VSPs that
- handle the memory interfaces for the DU channels. The phandle identifies the
- VSP instance that serves the DU channel, and the channel index identifies
- the LIF instance in that VSP.
-
-Optional properties:
- - resets: A list of phandle + reset-specifier pairs, one for each entry in
- the reset-names property.
- - reset-names: Names of the resets. This property is model-dependent.
- - All but R8A7779 use one reset for a group of one or more successive
- channels. The resets must be named "du.x" with "x" being the numerical
- index of the lowest channel in the group.
-
-Required nodes:
-
-The connections to the DU output video ports are modeled using the OF graph
-bindings specified in Documentation/devicetree/bindings/graph.txt.
-
-The following table lists for each supported model the port number
-corresponding to each DU output.
-
- Port0 Port1 Port2 Port3
------------------------------------------------------------------------------
- R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 -
- R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
- R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
- R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
- R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
- R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
- R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 -
- R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
- R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 -
- R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
- R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
- R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
- R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
- R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
- R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
- R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
- R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
- R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 -
- R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
- R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
- R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - -
- R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 -
- R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
-
-
-Example: R8A7795 (R-Car H3) ES2.0 DU
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.2", "du.3";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.2";
- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_hdmi1: endpoint {
- remote-endpoint = <&dw_hdmi1_in>;
- };
- };
- port@3 {
- reg = <3>;
- du_out_lvds0: endpoint {
- };
- };
- };
- };
diff --git a/dts/Bindings/display/renesas,du.yaml b/dts/Bindings/display/renesas,du.yaml
new file mode 100644
index 0000000000..121596f106
--- /dev/null
+++ b/dts/Bindings/display/renesas,du.yaml
@@ -0,0 +1,834 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Display Unit (DU)
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ These DT bindings describe the Display Unit embedded in the Renesas R-Car
+ Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - renesas,du-r8a7742 # for RZ/G1H compatible DU
+ - renesas,du-r8a7743 # for RZ/G1M compatible DU
+ - renesas,du-r8a7744 # for RZ/G1N compatible DU
+ - renesas,du-r8a7745 # for RZ/G1E compatible DU
+ - renesas,du-r8a77470 # for RZ/G1C compatible DU
+ - renesas,du-r8a774a1 # for RZ/G2M compatible DU
+ - renesas,du-r8a774b1 # for RZ/G2N compatible DU
+ - renesas,du-r8a774c0 # for RZ/G2E compatible DU
+ - renesas,du-r8a774e1 # for RZ/G2H compatible DU
+ - renesas,du-r8a7779 # for R-Car H1 compatible DU
+ - renesas,du-r8a7790 # for R-Car H2 compatible DU
+ - renesas,du-r8a7791 # for R-Car M2-W compatible DU
+ - renesas,du-r8a7792 # for R-Car V2H compatible DU
+ - renesas,du-r8a7793 # for R-Car M2-N compatible DU
+ - renesas,du-r8a7794 # for R-Car E2 compatible DU
+ - renesas,du-r8a7795 # for R-Car H3 compatible DU
+ - renesas,du-r8a7796 # for R-Car M3-W compatible DU
+ - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
+ - renesas,du-r8a77965 # for R-Car M3-N compatible DU
+ - renesas,du-r8a77970 # for R-Car V3M compatible DU
+ - renesas,du-r8a77980 # for R-Car V3H compatible DU
+ - renesas,du-r8a77990 # for R-Car E3 compatible DU
+ - renesas,du-r8a77995 # for R-Car D3 compatible DU
+
+ reg:
+ maxItems: 1
+
+ # See compatible-specific constraints below.
+ clocks: true
+ clock-names: true
+ interrupts:
+ description: Interrupt specifiers, one per DU channel
+ resets: true
+ reset-names: true
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ The connections to the DU output video ports are modeled using the OF
+ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+ The number of ports and their assignment are model-dependent. Each port
+ shall have a single endpoint.
+
+ patternProperties:
+ "^port@[0-3]$":
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+
+ required:
+ - port@0
+ - port@1
+
+ unevaluatedProperties: false
+
+ renesas,cmms:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description:
+ A list of phandles to the CMM instances present in the SoC, one for each
+ available DU channel.
+
+ renesas,vsps:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description:
+ A list of phandle and channel index tuples to the VSPs that handle the
+ memory interfaces for the DU channels. The phandle identifies the VSP
+ instance that serves the DU channel, and the channel index identifies
+ the LIF instance in that VSP.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - resets
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,du-r8a7779
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: Functional clock
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ - const: du.0
+ - pattern: '^dclkin\.[01]$'
+ - pattern: '^dclkin\.[01]$'
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: DPAD 1
+ # port@2 is TCON, not supported yet
+ port@2: false
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+
+ required:
+ - interrupts
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a7743
+ - renesas,du-r8a7744
+ - renesas,du-r8a7791
+ - renesas,du-r8a7793
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: du.0
+ - const: du.1
+ - pattern: '^dclkin\.[01]$'
+ - pattern: '^dclkin\.[01]$'
+
+ interrupts:
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: LVDS 0
+ # port@2 is TCON, not supported yet
+ port@2: false
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a7745
+ - renesas,du-r8a7792
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: du.0
+ - const: du.1
+ - pattern: '^dclkin\.[01]$'
+ - pattern: '^dclkin\.[01]$'
+
+ interrupts:
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: DPAD 1
+ port@2: false
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a7794
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: du.0
+ - const: du.1
+ - pattern: '^dclkin\.[01]$'
+ - pattern: '^dclkin\.[01]$'
+
+ interrupts:
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: DPAD 1
+ # port@2 is TCON, not supported yet
+ port@2: false
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a77470
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: du.0
+ - const: du.1
+ - pattern: '^dclkin\.[01]$'
+ - pattern: '^dclkin\.[01]$'
+
+ interrupts:
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: DPAD 1
+ port@2:
+ description: LVDS 0
+ # port@3 is DVENC, not supported yet
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a7742
+ - renesas,du-r8a7790
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 6
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: Functional clock for DU2
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+ - description: DU_DOTCLKIN2 input clock
+
+ clock-names:
+ minItems: 3
+ maxItems: 6
+ items:
+ - const: du.0
+ - const: du.1
+ - const: du.2
+ - pattern: '^dclkin\.[012]$'
+ - pattern: '^dclkin\.[012]$'
+ - pattern: '^dclkin\.[012]$'
+
+ interrupts:
+ maxItems: 3
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: LVDS 0
+ port@2:
+ description: LVDS 1
+ # port@3 is TCON, not supported yet
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a7795
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 8
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: Functional clock for DU2
+ - description: Functional clock for DU4
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+ - description: DU_DOTCLKIN2 input clock
+ - description: DU_DOTCLKIN3 input clock
+
+ clock-names:
+ minItems: 4
+ maxItems: 8
+ items:
+ - const: du.0
+ - const: du.1
+ - const: du.2
+ - const: du.3
+ - pattern: '^dclkin\.[0123]$'
+ - pattern: '^dclkin\.[0123]$'
+ - pattern: '^dclkin\.[0123]$'
+ - pattern: '^dclkin\.[0123]$'
+
+ interrupts:
+ maxItems: 4
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: du.0
+ - const: du.2
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: HDMI 0
+ port@2:
+ description: HDMI 1
+ port@3:
+ description: LVDS 0
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+
+ renesas,cmms:
+ minItems: 4
+
+ renesas,vsps:
+ minItems: 4
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+ - renesas,vsps
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a774a1
+ - renesas,du-r8a7796
+ - renesas,du-r8a77961
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 6
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: Functional clock for DU2
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+ - description: DU_DOTCLKIN2 input clock
+
+ clock-names:
+ minItems: 3
+ maxItems: 6
+ items:
+ - const: du.0
+ - const: du.1
+ - const: du.2
+ - pattern: '^dclkin\.[012]$'
+ - pattern: '^dclkin\.[012]$'
+ - pattern: '^dclkin\.[012]$'
+
+ interrupts:
+ maxItems: 3
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: du.0
+ - const: du.2
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: HDMI 0
+ port@2:
+ description: LVDS 0
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ renesas,cmms:
+ minItems: 3
+
+ renesas,vsps:
+ minItems: 3
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+ - renesas,vsps
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a774b1
+ - renesas,du-r8a774e1
+ - renesas,du-r8a77965
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 6
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: Functional clock for DU3
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+ - description: DU_DOTCLKIN3 input clock
+
+ clock-names:
+ minItems: 3
+ maxItems: 6
+ items:
+ - const: du.0
+ - const: du.1
+ - const: du.3
+ - pattern: '^dclkin\.[013]$'
+ - pattern: '^dclkin\.[013]$'
+ - pattern: '^dclkin\.[013]$'
+
+ interrupts:
+ maxItems: 3
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: du.0
+ - const: du.3
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: HDMI 0
+ port@2:
+ description: LVDS 0
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ renesas,cmms:
+ minItems: 3
+
+ renesas,vsps:
+ minItems: 3
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+ - renesas,vsps
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a77970
+ - renesas,du-r8a77980
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Functional clock for DU0
+ - description: DU_DOTCLKIN0 input clock
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: du.0
+ - const: dclkin.0
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: LVDS 0
+ port@2: false
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+
+ renesas,vsps:
+ minItems: 1
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+ - renesas,vsps
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,du-r8a774c0
+ - renesas,du-r8a77990
+ - renesas,du-r8a77995
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Functional clock for DU0
+ - description: Functional clock for DU1
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: du.0
+ - const: du.1
+ - pattern: '^dclkin\.[01]$'
+ - pattern: '^dclkin\.[01]$'
+
+ interrupts:
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: du.0
+
+ ports:
+ properties:
+ port@0:
+ description: DPAD 0
+ port@1:
+ description: LVDS 0
+ port@2:
+ description: LVDS 1
+ # port@3 is TCON, not supported yet
+ port@3: false
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ renesas,cmms:
+ minItems: 2
+
+ renesas,vsps:
+ minItems: 2
+
+ required:
+ - clock-names
+ - interrupts
+ - resets
+ - reset-names
+ - renesas,vsps
+
+additionalProperties: false
+
+examples:
+ # R-Car H3 ES2.0 DU
+ - |
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display@feb00000 {
+ compatible = "renesas,du-r8a7795";
+ reg = <0xfeb00000 0x80000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.2", "du.3";
+ resets = <&cpg 724>, <&cpg 722>;
+ reset-names = "du.0", "du.2";
+
+ renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ endpoint {
+ remote-endpoint = <&dw_hdmi1_in>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
deleted file mode 100644
index 3d32ce137e..0000000000
--- a/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Rockchip DWC HDMI TX Encoder
-============================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible: should be one of the following:
- "rockchip,rk3228-dw-hdmi"
- "rockchip,rk3288-dw-hdmi"
- "rockchip,rk3328-dw-hdmi"
- "rockchip,rk3399-dw-hdmi"
-- reg: See dw_hdmi.txt.
-- reg-io-width: See dw_hdmi.txt. Shall be 4.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
- corresponding to the video input of the controller. The port shall have two
- endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
-- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
-
-Optional properties
-
-- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
- or the functionally-reduced I2C master contained in the DWC HDMI. When
- connected to a system I2C master this property contains a phandle to that
- I2C master controller.
-- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
-- clock-names: May contain "cec" as defined in dw_hdmi.txt.
-- clock-names: May contain "grf", power for grf io.
-- clock-names: May contain "vpll", external clock for some hdmi phy.
-- phys: from general PHY binding: the phandle for the PHY device.
-- phy-names: Should be "hdmi" if phys references an external phy.
-
-Optional pinctrl entry:
-- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
- will switch to the unwedge pinctrl state for 10ms if it ever gets an
- i2c timeout. It's intended that this unwedge pinctrl entry will
- cause the SDA line to be driven low to work around a hardware
- errata.
-
-Example:
-
-hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3288-dw-hdmi";
- reg = <0xff980000 0x20000>;
- reg-io-width = <4>;
- ddc-i2c-bus = <&i2c5>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
- clock-names = "iahb", "isfr";
- ports {
- hdmi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- hdmi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_hdmi>;
- };
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
- };
- };
-};
diff --git a/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml b/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
new file mode 100644
index 0000000000..75cd9c686e
--- /dev/null
+++ b/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip DWC HDMI TX Encoder
+
+maintainers:
+ - Mark Yao <markyao0591@gmail.com>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3228-dw-hdmi
+ - rockchip,rk3288-dw-hdmi
+ - rockchip,rk3328-dw-hdmi
+ - rockchip,rk3399-dw-hdmi
+
+ reg-io-width:
+ const: 4
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+ items:
+ - {}
+ - {}
+ # The next three clocks are all optional, but shall be specified in this
+ # order when present.
+ - description: The HDMI CEC controller main clock
+ - description: Power for GRF IO
+ - description: External clock for some HDMI PHY
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ - {}
+ - {}
+ - enum:
+ - cec
+ - grf
+ - vpll
+ - enum:
+ - grf
+ - vpll
+ - const: vpll
+
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ phys:
+ maxItems: 1
+ description: The HDMI PHY
+
+ phy-names:
+ const: hdmi
+
+ pinctrl-names:
+ description:
+ The unwedge pinctrl entry shall drive the DDC SDA line low. This is
+ intended to work around a hardware errata that can cause the DDC I2C
+ bus to be wedged.
+ items:
+ - const: default
+ - const: unwedge
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Input of the DWC HDMI TX
+
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Connection to the VOPB
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Connection to the VOPL
+
+ required:
+ - endpoint@0
+ - endpoint@1
+
+ required:
+ - port
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the GRF to mux vopl/vopb.
+
+required:
+ - compatible
+ - reg
+ - reg-io-width
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+ - rockchip,grf
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3288-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3288-dw-hdmi";
+ reg = <0xff980000 0x20000>;
+ reg-io-width = <4>;
+ ddc-i2c-bus = <&i2c5>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_hdmi>;
+ };
+ hdmi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_hdmi>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/simple-framebuffer.yaml b/dts/Bindings/display/simple-framebuffer.yaml
index eaf8c54fcf..c2499a7906 100644
--- a/dts/Bindings/display/simple-framebuffer.yaml
+++ b/dts/Bindings/display/simple-framebuffer.yaml
@@ -54,6 +54,7 @@ properties:
compatible:
items:
- enum:
+ - apple,simple-framebuffer
- allwinner,simple-framebuffer
- amlogic,simple-framebuffer
- const: simple-framebuffer
@@ -84,9 +85,13 @@ properties:
Format of the framebuffer:
* `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
* `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
+ * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
+ * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
enum:
- a8b8g8r8
- r5g6b5
+ - x2r10g10b10
+ - x8r8g8b8
display:
$ref: /schemas/types.yaml#/definitions/phandle
diff --git a/dts/Bindings/dma/qcom,gpi.yaml b/dts/Bindings/dma/qcom,gpi.yaml
index f8142adf9a..e302147e53 100644
--- a/dts/Bindings/dma/qcom,gpi.yaml
+++ b/dts/Bindings/dma/qcom,gpi.yaml
@@ -20,6 +20,7 @@ properties:
compatible:
enum:
- qcom,sdm845-gpi-dma
+ - qcom,sm8150-gpi-dma
reg:
maxItems: 1
@@ -64,7 +65,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/dma/qcom-gpi.h>
gpi_dma0: dma-controller@800000 {
- compatible = "qcom,gpi-dma";
+ compatible = "qcom,sdm845-gpi-dma";
#dma-cells = <3>;
reg = <0x00800000 0x60000>;
iommus = <&apps_smmu 0x0016 0x0>;
diff --git a/dts/Bindings/extcon/qcom,pm8941-misc.txt b/dts/Bindings/extcon/qcom,pm8941-misc.txt
deleted file mode 100644
index 35383adb10..0000000000
--- a/dts/Bindings/extcon/qcom,pm8941-misc.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Qualcomm's PM8941 USB ID Extcon device
-
-Some Qualcomm PMICs have a "misc" module that can be used to detect when
-the USB ID pin has been pulled low or high.
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Should contain "qcom,pm8941-misc";
-
-- reg:
- Usage: required
- Value type: <u32>
- Definition: Should contain the offset to the misc address space
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Should contain the usb id interrupt
-
-- interrupt-names:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain the string "usb_id" for the usb id interrupt
-
-Example:
-
- pmic {
- usb_id: misc@900 {
- compatible = "qcom,pm8941-misc";
- reg = <0x900>;
- interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "usb_id";
- };
- }
-
- usb-controller {
- extcon = <&usb_id>;
- };
diff --git a/dts/Bindings/extcon/qcom,pm8941-misc.yaml b/dts/Bindings/extcon/qcom,pm8941-misc.yaml
new file mode 100644
index 0000000000..6a9c96f035
--- /dev/null
+++ b/dts/Bindings/extcon/qcom,pm8941-misc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/qcom,pm8941-misc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PM8941 USB ID Extcon device
+
+maintainers:
+ - Guru Das Srinagesh <gurus@codeaurora.org>
+
+description: |
+ Some Qualcomm PMICs have a "misc" module that can be used to detect when
+ the USB ID pin has been pulled low or high.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,pm8941-misc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: usb_id
+ - const: usb_vbus
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ usb_id: misc@900 {
+ compatible = "qcom,pm8941-misc";
+ reg = <0x900>;
+ interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "usb_id";
+ };
+ };
+
+ usb-controller {
+ extcon = <&usb_id>;
+ };
diff --git a/dts/Bindings/firmware/qcom,scm.txt b/dts/Bindings/firmware/qcom,scm.txt
index a884955f86..e747d73687 100644
--- a/dts/Bindings/firmware/qcom,scm.txt
+++ b/dts/Bindings/firmware/qcom,scm.txt
@@ -20,7 +20,9 @@ Required properties:
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
* "qcom,scm-sc7180"
+ * "qcom,scm-sc7280"
* "qcom,scm-sdm845"
+ * "qcom,scm-sdx55"
* "qcom,scm-sm8150"
* "qcom,scm-sm8250"
* "qcom,scm-sm8350"
diff --git a/dts/Bindings/fpga/fpga-region.txt b/dts/Bindings/fpga/fpga-region.txt
index e811cf8250..d787d57491 100644
--- a/dts/Bindings/fpga/fpga-region.txt
+++ b/dts/Bindings/fpga/fpga-region.txt
@@ -245,36 +245,31 @@ Base tree contains:
Overlay contains:
-/dts-v1/ /plugin/;
-/ {
- fragment@0 {
- target = <&fpga_region0>;
- #address-cells = <1>;
- #size-cells = <1>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "soc_system.rbf";
- fpga-bridges = <&fpga_bridge1>;
- ranges = <0x20000 0xff200000 0x100000>,
- <0x0 0xc0000000 0x20000000>;
-
- gpio@10040 {
- compatible = "altr,pio-1.0";
- reg = <0x10040 0x20>;
- altr,ngpio = <4>;
- #gpio-cells = <2>;
- clocks = <2>;
- gpio-controller;
- };
-
- onchip-memory {
- device_type = "memory";
- compatible = "altr,onchipmem-15.1";
- reg = <0x0 0x10000>;
- };
- };
+/dts-v1/;
+/plugin/;
+
+&fpga_region0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ firmware-name = "soc_system.rbf";
+ fpga-bridges = <&fpga_bridge1>;
+ ranges = <0x20000 0xff200000 0x100000>,
+ <0x0 0xc0000000 0x20000000>;
+
+ gpio@10040 {
+ compatible = "altr,pio-1.0";
+ reg = <0x10040 0x20>;
+ altr,ngpio = <4>;
+ #gpio-cells = <2>;
+ clocks = <2>;
+ gpio-controller;
+ };
+
+ onchip-memory {
+ device_type = "memory";
+ compatible = "altr,onchipmem-15.1";
+ reg = <0x0 0x10000>;
};
};
@@ -371,25 +366,22 @@ Live Device Tree contains:
};
DT Overlay contains:
-/dts-v1/ /plugin/;
-/ {
-fragment@0 {
- target = <&fpga_region0>;
+
+/dts-v1/;
+/plugin/;
+
+&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <1>;
- firmware-name = "zynq-gpio.bin";
+ firmware-name = "zynq-gpio.bin";
- gpio1: gpio@40000000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = <0x40000000 0x10000>;
- gpio-controller;
- #gpio-cells = <0x2>;
- xlnx,gpio-width= <0x6>;
- };
+ gpio1: gpio@40000000 {
+ compatible = "xlnx,xps-gpio-1.00.a";
+ reg = <0x40000000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ xlnx,gpio-width= <0x6>;
};
};
@@ -402,41 +394,37 @@ This example programs the FPGA to have two regions that can later be partially
configured. Each region has its own bridge in the FPGA fabric.
DT Overlay contains:
-/dts-v1/ /plugin/;
-/ {
- fragment@0 {
- target = <&fpga_region0>;
- #address-cells = <1>;
- #size-cells = <1>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "base.rbf";
-
- fpga-bridge@4400 {
- compatible = "altr,freeze-bridge-controller";
- reg = <0x4400 0x10>;
-
- fpga_region1: fpga-region1 {
- compatible = "fpga-region";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
- };
- };
-
- fpga-bridge@4420 {
- compatible = "altr,freeze-bridge-controller";
- reg = <0x4420 0x10>;
-
- fpga_region2: fpga-region2 {
- compatible = "fpga-region";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
- };
- };
+
+/dts-v1/;
+/plugin/;
+
+&fpga_region0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ firmware-name = "base.rbf";
+
+ fpga-bridge@4400 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x4400 0x10>;
+
+ fpga_region1: fpga-region1 {
+ compatible = "fpga-region";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges;
+ };
+ };
+
+ fpga-bridge@4420 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x4420 0x10>;
+
+ fpga_region2: fpga-region2 {
+ compatible = "fpga-region";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges;
};
};
};
@@ -451,28 +439,23 @@ differences are that the FPGA is partially reconfigured due to the
"partial-fpga-config" boolean and the only bridge that is controlled during
programming is the FPGA based bridge of fpga_region1.
-/dts-v1/ /plugin/;
-/ {
- fragment@0 {
- target = <&fpga_region1>;
- #address-cells = <1>;
- #size-cells = <1>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "soc_image2.rbf";
- partial-fpga-config;
-
- gpio@10040 {
- compatible = "altr,pio-1.0";
- reg = <0x10040 0x20>;
- clocks = <0x2>;
- altr,ngpio = <0x4>;
- #gpio-cells = <0x2>;
- gpio-controller;
- };
- };
+/dts-v1/;
+/plugin/;
+
+&fpga_region1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ firmware-name = "soc_image2.rbf";
+ partial-fpga-config;
+
+ gpio@10040 {
+ compatible = "altr,pio-1.0";
+ reg = <0x10040 0x20>;
+ clocks = <0x2>;
+ altr,ngpio = <0x4>;
+ #gpio-cells = <0x2>;
+ gpio-controller;
};
};
diff --git a/dts/Bindings/fpga/xilinx-pr-decoupler.txt b/dts/Bindings/fpga/xilinx-pr-decoupler.txt
index 4284d293fa..0acdfa6d62 100644
--- a/dts/Bindings/fpga/xilinx-pr-decoupler.txt
+++ b/dts/Bindings/fpga/xilinx-pr-decoupler.txt
@@ -7,13 +7,24 @@ changes from passing through the bridge. The controller can also
couple / enable the bridges which allows traffic to pass through the
bridge normally.
+Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
+Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
+
+The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
+from passing through the bridge. The controller safely handles AXI4MM
+and AXI4-Lite interfaces on a Reconfigurable Partition when it is
+undergoing dynamic reconfiguration, preventing the system deadlock
+that can occur if AXI transactions are interrupted by DFX
+
The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.
Required properties:
- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
- "xlnx,pr-decoupler"
+ "xlnx,pr-decoupler" or
+ "xlnx,dfx-axi-shutdown-manager-1.00" followed by
+ "xlnx,dfx-axi-shutdown-manager"
- regs : base address and size for decoupler module
- clocks : input clock to IP
- clock-names : should contain "aclk"
@@ -22,6 +33,7 @@ See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
+Partial Reconfig Decoupler:
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00",
"xlnx-pr-decoupler";
@@ -30,3 +42,13 @@ Example:
clock-names = "aclk";
bridge-enable = <0>;
};
+
+Dynamic Function eXchange AXI shutdown manager:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
+ "xlnx,dfx-axi-shutdown-manager";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
diff --git a/dts/Bindings/gpio/brcm,bcm6345-gpio.txt b/dts/Bindings/gpio/brcm,bcm6345-gpio.txt
deleted file mode 100644
index e7853143fa..0000000000
--- a/dts/Bindings/gpio/brcm,bcm6345-gpio.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers.
-
-These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
-are the only ones which don't need a pinctrl driver.
-BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
-and/or written, and the direction changed from input to output.
-BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
-and/or written, and the direction changed from input to output.
-
-Required properties:
- - compatible: should be "brcm,bcm6345-gpio"
- - reg-names: must contain
- "dat" - data register
- "dirout" - direction (output) register
- - reg: address + size pairs describing the GPIO register sets;
- order must correspond with the order of entries in reg-names
- - #gpio-cells: must be set to 2. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = active high
- 1 = active low
- - gpio-controller: Marks the device node as a gpio controller.
-
-Optional properties:
- - native-endian: use native endian memory.
-
-Examples:
- - BCM6338:
- gpio: gpio-controller@fffe0407 {
- compatible = "brcm,bcm6345-gpio";
- reg-names = "dirout", "dat";
- reg = <0xfffe0407 1>, <0xfffe040f 1>;
-
- #gpio-cells = <2>;
- gpio-controller;
- };
-
- - BCM6345:
- gpio: gpio-controller@fffe0406 {
- compatible = "brcm,bcm6345-gpio";
- reg-names = "dirout", "dat";
- reg = <0xfffe0406 2>, <0xfffe040a 2>;
- native-endian;
-
- #gpio-cells = <2>;
- gpio-controller;
- };
diff --git a/dts/Bindings/gpio/brcm,bcm6345-gpio.yaml b/dts/Bindings/gpio/brcm,bcm6345-gpio.yaml
new file mode 100644
index 0000000000..4d69f79df8
--- /dev/null
+++ b/dts/Bindings/gpio/brcm,bcm6345-gpio.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6345 GPIO controller
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description: |+
+ Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
+
+ These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
+ are the only ones which don't need a pinctrl driver.
+
+ BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
+ and/or written, and the direction changed from input to output.
+ BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
+ and/or written, and the direction changed from input to output.
+ BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
+ and dirout registers, where GPIO state can be read and/or written, and the
+ direction changed from input to output.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm6318-gpio
+ - brcm,bcm6328-gpio
+ - brcm,bcm6345-gpio
+ - brcm,bcm6358-gpio
+ - brcm,bcm6362-gpio
+ - brcm,bcm6368-gpio
+ - brcm,bcm63268-gpio
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ native-endian: true
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: dirout
+ - const: dat
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@fffe0406 {
+ compatible = "brcm,bcm6345-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0xfffe0406 2>, <0xfffe040a 2>;
+ native-endian;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ - |
+ gpio@0 {
+ compatible = "brcm,bcm63268-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 52>;
+ #gpio-cells = <2>;
+ };
diff --git a/dts/Bindings/gpio/fairchild,74hc595.yaml b/dts/Bindings/gpio/fairchild,74hc595.yaml
new file mode 100644
index 0000000000..5fe19fa5f6
--- /dev/null
+++ b/dts/Bindings/gpio/fairchild,74hc595.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic 8-bit shift register
+
+maintainers:
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - fairchild,74hc595
+ - nxp,74lvc594
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description:
+ The second cell is only used to specify the GPIO polarity.
+ const: 2
+
+ registers-number:
+ description: Number of daisy-chained shift registers
+
+ enable-gpios:
+ description: GPIO connected to the OE (Output Enable) pin.
+ maxItems: 1
+
+ spi-max-frequency: true
+
+patternProperties:
+ "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
+ type: object
+
+ properties:
+ gpio-hog: true
+ gpios: true
+ output-high: true
+ output-low: true
+ line-name: true
+
+ required:
+ - gpio-hog
+ - gpios
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - registers-number
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio5: gpio5@0 {
+ compatible = "fairchild,74hc595";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ registers-number = <4>;
+ spi-max-frequency = <100000>;
+ };
+ };
diff --git a/dts/Bindings/gpio/gpio-74x164.txt b/dts/Bindings/gpio/gpio-74x164.txt
deleted file mode 100644
index 2a97553d8d..0000000000
--- a/dts/Bindings/gpio/gpio-74x164.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Generic 8-bits shift register GPIO driver
-
-Required properties:
-- compatible: Should contain one of the following:
- "fairchild,74hc595"
- "nxp,74lvc594"
-- reg : chip select number
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = active high
- 1 = active low
-- registers-number: Number of daisy-chained shift registers
-
-Optional properties:
-- enable-gpios: GPIO connected to the OE (Output Enable) pin.
-
-Example:
-
-gpio5: gpio5@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <4>;
- spi-max-frequency = <100000>;
-};
diff --git a/dts/Bindings/gpio/realtek,otto-gpio.yaml b/dts/Bindings/gpio/realtek,otto-gpio.yaml
new file mode 100644
index 0000000000..100f20cebd
--- /dev/null
+++ b/dts/Bindings/gpio/realtek,otto-gpio.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek Otto GPIO controller
+
+maintainers:
+ - Sander Vanheule <sander@svanheule.net>
+ - Bert Vermeulen <bert@biot.com>
+
+description: |
+ Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
+ of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
+ Each bank's interrupts are cascased into one interrupt line on the parent
+ interrupt controller, if provided.
+ This binding allows defining a single bank in the devicetree. The interrupt
+ controller is not supported on the fallback compatible name, which only
+ allows for GPIO port use.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - realtek,rtl8380-gpio
+ - realtek,rtl8390-gpio
+ - const: realtek,otto-gpio
+
+ reg:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ ngpios:
+ minimum: 1
+ maximum: 32
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
+
+dependencies:
+ interrupt-controller: [ interrupts ]
+
+examples:
+ - |
+ gpio@3500 {
+ compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
+ reg = <0x3500 0x1c>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <24>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&rtlintc>;
+ interrupts = <23>;
+ };
+
+...
diff --git a/dts/Bindings/gpio/rockchip,gpio-bank.yaml b/dts/Bindings/gpio/rockchip,gpio-bank.yaml
new file mode 100644
index 0000000000..d993e002ce
--- /dev/null
+++ b/dts/Bindings/gpio/rockchip,gpio-bank.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip GPIO bank
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,gpio-bank
+ - rockchip,rk3188-gpio-bank0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pinctrl: pinctrl {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio@2000a000 {
+ compatible = "rockchip,rk3188-gpio-bank0";
+ reg = <0x2000a000 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 9>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2003c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2003c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 10>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
diff --git a/dts/Bindings/gpio/socionext,uniphier-gpio.yaml b/dts/Bindings/gpio/socionext,uniphier-gpio.yaml
index 1a54db04f2..bcafa494ed 100644
--- a/dts/Bindings/gpio/socionext,uniphier-gpio.yaml
+++ b/dts/Bindings/gpio/socionext,uniphier-gpio.yaml
@@ -43,8 +43,7 @@ properties:
gpio-ranges: true
- gpio-ranges-group-names:
- $ref: /schemas/types.yaml#/definitions/string-array
+ gpio-ranges-group-names: true
socionext,interrupt-ranges:
description: |
diff --git a/dts/Bindings/gpu/arm,mali-bifrost.yaml b/dts/Bindings/gpu/arm,mali-bifrost.yaml
index 184492162e..894ba217ab 100644
--- a/dts/Bindings/gpu/arm,mali-bifrost.yaml
+++ b/dts/Bindings/gpu/arm,mali-bifrost.yaml
@@ -69,6 +69,8 @@ properties:
where voltage is in V, frequency is in MHz.
+ dma-coherent: true
+
required:
- compatible
- reg
diff --git a/dts/Bindings/hwlock/sirf,hwspinlock.txt b/dts/Bindings/hwlock/sirf,hwspinlock.txt
deleted file mode 100644
index 9bb1240a68..0000000000
--- a/dts/Bindings/hwlock/sirf,hwspinlock.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-SIRF Hardware spinlock device Binding
------------------------------------------------
-
-Required properties :
-- compatible : shall contain only one of the following:
- "sirf,hwspinlock"
-
-- reg : the register address of hwspinlock
-
-- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
- hwlock, so the number of cells should be <1> here.
-
-Please look at the generic hwlock binding for usage information for consumers,
-"Documentation/devicetree/bindings/hwlock/hwlock.txt"
-
-Example of hwlock provider:
- hwlock {
- compatible = "sirf,hwspinlock";
- reg = <0x13240000 0x00010000>;
- #hwlock-cells = <1>;
- };
-
-Example of hwlock users:
- node {
- ...
- hwlocks = <&hwlock 2>;
- ...
- };
diff --git a/dts/Bindings/i2c/i2c-mpc.txt b/dts/Bindings/i2c/i2c-mpc.txt
deleted file mode 100644
index 42a3905269..0000000000
--- a/dts/Bindings/i2c/i2c-mpc.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-* I2C
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
- compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
- mpc5200 or mpc5200b. For the mpc5121, an additional node
- "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
-
-Recommended properties :
-
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - fsl,preserve-clocking : boolean; if defined, the clock settings
- from the bootloader are preserved (not touched).
- - clock-frequency : desired I2C bus clock frequency in Hz.
- - fsl,timeout : I2C bus timeout in microseconds.
-
-Examples :
-
- /* MPC5121 based board */
- i2c@1740 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5121-i2c", "fsl-i2c";
- reg = <0x1740 0x20>;
- interrupts = <11 0x8>;
- interrupt-parent = <&ipic>;
- clock-frequency = <100000>;
- };
-
- i2ccontrol@1760 {
- compatible = "fsl,mpc5121-i2c-ctrl";
- reg = <0x1760 0x8>;
- };
-
- /* MPC5200B based board */
- i2c@3d00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d00 0x40>;
- interrupts = <2 15 0>;
- interrupt-parent = <&mpc5200_pic>;
- fsl,preserve-clocking;
- };
-
- /* MPC8544 base board */
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc8544-i2c", "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- clock-frequency = <400000>;
- fsl,timeout = <10000>;
- };
diff --git a/dts/Bindings/i2c/i2c-mpc.yaml b/dts/Bindings/i2c/i2c-mpc.yaml
new file mode 100644
index 0000000000..7b553d559c
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-mpc.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs
+
+maintainers:
+ - Chris Packham <chris.packham@alliedtelesis.co.nz>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mpc5200-i2c
+ - fsl,mpc5200-i2c
+ - fsl,mpc5121-i2c
+ - fsl,mpc8313-i2c
+ - fsl,mpc8543-i2c
+ - fsl,mpc8544-i2c
+ - const: fsl-i2c
+ - items:
+ - const: fsl,mpc5200b-i2c
+ - const: fsl,mpc5200-i2c
+ - const: fsl-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,preserve-clocking:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ if defined, the clock settings from the bootloader are
+ preserved (not touched)
+
+ fsl,timeout:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ I2C bus timeout in microseconds
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* MPC5121 based board */
+ i2c@1740 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+ reg = <0x1740 0x20>;
+ interrupts = <11 0x8>;
+ interrupt-parent = <&ipic>;
+ clock-frequency = <100000>;
+ };
+
+ /* MPC5200B based board */
+ i2c@3d00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5200b-i2c", "fsl,mpc5200-i2c", "fsl-i2c";
+ reg = <0x3d00 0x40>;
+ interrupts = <2 15 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ fsl,preserve-clocking;
+ };
+
+ /* MPC8544 base board */
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ clock-frequency = <400000>;
+ fsl,timeout = <10000>;
+ };
+...
diff --git a/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
index ffb2ed039a..715dcfa5a9 100644
--- a/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+++ b/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
@@ -4,7 +4,7 @@
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: ilinx IIC controller Device Tree Bindings
+title: Xilinx IIC controller Device Tree Bindings
maintainers:
- info@mocean-labs.com
diff --git a/dts/Bindings/i3c/cdns,i3c-master.txt b/dts/Bindings/i3c/cdns,i3c-master.txt
index 1cf6182f88..3716589d69 100644
--- a/dts/Bindings/i3c/cdns,i3c-master.txt
+++ b/dts/Bindings/i3c/cdns,i3c-master.txt
@@ -10,19 +10,19 @@ Required properties:
- reg: I3C master registers
Mandatory properties defined by the generic binding (see
-Documentation/devicetree/bindings/i3c/i3c.txt for more details):
+Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- #address-cells: shall be set to 1
- #size-cells: shall be set to 0
Optional properties defined by the generic binding (see
-Documentation/devicetree/bindings/i3c/i3c.txt for more details):
+Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- i2c-scl-hz
- i3c-scl-hz
I3C device connected on the bus follow the generic description (see
-Documentation/devicetree/bindings/i3c/i3c.txt for more details).
+Documentation/devicetree/bindings/i3c/i3c.yaml for more details).
Example:
diff --git a/dts/Bindings/i3c/i3c.yaml b/dts/Bindings/i3c/i3c.yaml
index 52042aa44d..1f82fc9237 100644
--- a/dts/Bindings/i3c/i3c.yaml
+++ b/dts/Bindings/i3c/i3c.yaml
@@ -157,9 +157,10 @@ examples:
i2c-scl-hz = <100000>;
/* I2C device. */
- nunchuk: nunchuk@52 {
- compatible = "nintendo,nunchuk";
- reg = <0x52 0x0 0x10>;
+ eeprom@57 {
+ compatible = "atmel,24c01";
+ reg = <0x57 0x0 0x10>;
+ pagesize = <0x8>;
};
/* I3C device with a static I2C address. */
diff --git a/dts/Bindings/i3c/silvaco,i3c-master.yaml b/dts/Bindings/i3c/silvaco,i3c-master.yaml
index adb5165505..62f3ca6627 100644
--- a/dts/Bindings/i3c/silvaco,i3c-master.yaml
+++ b/dts/Bindings/i3c/silvaco,i3c-master.yaml
@@ -49,7 +49,7 @@ additionalProperties: true
examples:
- |
i3c-master@a0000000 {
- compatible = "silvaco,i3c-master";
+ compatible = "silvaco,i3c-master-v1";
clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
clock-names = "pclk", "fast_clk", "slow_clk";
interrupt-parent = <&gic>;
diff --git a/dts/Bindings/i3c/snps,dw-i3c-master.txt b/dts/Bindings/i3c/snps,dw-i3c-master.txt
index 5020eb71eb..07f35f3608 100644
--- a/dts/Bindings/i3c/snps,dw-i3c-master.txt
+++ b/dts/Bindings/i3c/snps,dw-i3c-master.txt
@@ -9,19 +9,19 @@ Required properties:
- reg: Offset and length of I3C master registers
Mandatory properties defined by the generic binding (see
-Documentation/devicetree/bindings/i3c/i3c.txt for more details):
+Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- #address-cells: shall be set to 3
- #size-cells: shall be set to 0
Optional properties defined by the generic binding (see
-Documentation/devicetree/bindings/i3c/i3c.txt for more details):
+Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- i2c-scl-hz
- i3c-scl-hz
I3C device connected on the bus follow the generic description (see
-Documentation/devicetree/bindings/i3c/i3c.txt for more details).
+Documentation/devicetree/bindings/i3c/i3c.yaml for more details).
Example:
diff --git a/dts/Bindings/iio/accel/bosch,bmi088.yaml b/dts/Bindings/iio/accel/bosch,bmi088.yaml
new file mode 100644
index 0000000000..911a1ae9c8
--- /dev/null
+++ b/dts/Bindings/iio/accel/bosch,bmi088.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/bosch,bmi088.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMI088 IMU accelerometer part
+
+maintainers:
+ - Mike Looijmans <mike.looijmans@topic.nl>
+
+description: |
+ Acceleration part of the IMU sensor with an SPI interface
+ Specifications about the sensor can be found at:
+ https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmi088-ds001.pdf
+
+properties:
+ compatible:
+ enum:
+ - bosch,bmi088-accel
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vdd-supply: true
+
+ vddio-supply: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Type should be either IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_LEVEL_LOW.
+ Two configurable interrupt lines exist.
+
+ interrupt-names:
+ description: Specify which interrupt line is in use.
+ items:
+ enum:
+ - INT1
+ - INT2
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bmi088-accel@1 {
+ compatible = "bosch,bmi088-accel";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT2";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml b/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml
index c562d25bee..547697e8bc 100644
--- a/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml
+++ b/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml
@@ -53,11 +53,6 @@ examples:
#address-cells = <1>;
#size-cells = <1>;
- ts_adc_syscon: ts_adc_syscon@180a6000 {
- compatible = "brcm,iproc-ts-adc-syscon","syscon";
- reg = <0x180a6000 0xc30>;
- };
-
adc {
compatible = "brcm,iproc-static-adc";
adc-syscon = <&ts_adc_syscon>;
diff --git a/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
index 5b21a9fba5..b939f9652e 100644
--- a/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+++ b/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -34,6 +34,7 @@ properties:
- items:
- enum:
- mediatek,mt8183-auxadc
+ - mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
- const: mediatek,mt8173-auxadc
diff --git a/dts/Bindings/iio/adc/ti,ads131e08.yaml b/dts/Bindings/iio/adc/ti,ads131e08.yaml
new file mode 100644
index 0000000000..e0670e3fbb
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,ads131e08.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads131e08.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
+
+maintainers:
+ - Tomislav Denis <tomislav.denis@avl.com>
+
+description: |
+ The ADS131E0x are a family of multichannel, simultaneous sampling,
+ 24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
+ built-in programmable gain amplifier (PGA), internal reference
+ and an onboard oscillator.
+ The communication with ADC chip is via the SPI bus (mode 1).
+
+ https://www.ti.com/lit/ds/symlink/ads131e08.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,ads131e04
+ - ti,ads131e06
+ - ti,ads131e08
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ spi-cpha: true
+
+ clocks:
+ description: |
+ Device tree identifier to the clock source (2.048 MHz).
+ Note: clock source is selected using CLKSEL pin.
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: adc-clk
+
+ interrupts:
+ description: |
+ IRQ line for the ADC data ready.
+ maxItems: 1
+
+ vref-supply:
+ description: |
+ Optional external voltage reference. If not supplied, internal voltage
+ reference is used.
+
+ ti,vref-internal:
+ description: |
+ Select the internal voltage reference value.
+ 0: 2.4V
+ 1: 4.0V
+ If this field is left empty, 2.4V is selected.
+ Note: internal voltage reference is used only if vref-supply is not supplied.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ default: 0
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+ - clocks
+ - clock-names
+ - interrupts
+
+patternProperties:
+ "^channel@([0-7])$":
+ $ref: "adc.yaml"
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number.
+ Up to 4 channels, numbered from 0 to 3 for ti,ads131e04.
+ Up to 6 channels, numbered from 0 to 5 for ti,ads131e06.
+ Up to 8 channels, numbered from 0 to 7 for ti,ads131e08.
+ items:
+ minimum: 0
+ maximum: 7
+
+ ti,gain:
+ description: |
+ The PGA gain value for the channel.
+ If this field is left empty, PGA gain 1 is used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 12]
+ default: 1
+
+ ti,mux:
+ description: |
+ Channel input selection(muliplexer).
+ 0: Normal input.
+ 1: Input shorted to (VREFP + VREFN) / 2 (for offset or noise measurements).
+ 3: MVDD (for supply measurement)
+ 4: Temperature sensor
+ If this field is left empty, normal input is selected.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 3, 4]
+ default: 0
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads131e08";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ clocks = <&clk2048k>;
+ clock-names = "adc-clk";
+ interrupt-parent = <&gpio5>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ vref-supply = <&adc_vref>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ ti,gain = <2>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ };
+
+ channel@4 {
+ reg = <4>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ ti,mux = <4>;
+ };
+ };
+ };
diff --git a/dts/Bindings/iio/cdc/adi,ad7150.yaml b/dts/Bindings/iio/cdc/adi,ad7150.yaml
new file mode 100644
index 0000000000..2155d3f566
--- /dev/null
+++ b/dts/Bindings/iio/cdc/adi,ad7150.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/cdc/adi,ad7150.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog device AD7150 and similar capacitance to digital convertors.
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7150
+ - adi,ad7151
+ - adi,ad7156
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ interrupts: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7150
+ - adi,ad7156
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,ad7151
+ then:
+ properties:
+ interrupts:
+ minItems: 1
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cdc@48 {
+ compatible = "adi,ad7150";
+ reg = <0x48>;
+ interrupts = <25 2>, <26 2>;
+ interrupt-parent = <&gpio>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml b/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml
index d97ee774d6..3f57a1b813 100644
--- a/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml
+++ b/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml
@@ -83,7 +83,7 @@ examples:
#size-cells = <0>;
gyroscope@0 {
- compatible = "nxp,fxas2102c";
+ compatible = "nxp,fxas21002c";
reg = <0x0>;
spi-max-frequency = <2000000>;
diff --git a/dts/Bindings/iio/imu/adi,adis16475.yaml b/dts/Bindings/iio/imu/adi,adis16475.yaml
index 79fba1508e..a757421017 100644
--- a/dts/Bindings/iio/imu/adi,adis16475.yaml
+++ b/dts/Bindings/iio/imu/adi,adis16475.yaml
@@ -71,15 +71,6 @@ properties:
minimum: 0
maximum: 3
- adi,scaled-output-hz:
- description:
- This property must be present if the clock mode is scaled-sync through
- clock-names property. In this mode, the input clock can have a range
- of 1Hz to 128HZ which must be scaled to originate an allowable sample
- rate. This property specifies that rate.
- minimum: 1900
- maximum: 2100
-
required:
- compatible
- reg
diff --git a/dts/Bindings/iio/light/capella,cm3605.yaml b/dts/Bindings/iio/light/capella,cm3605.yaml
index 27972938b6..c63b79c335 100644
--- a/dts/Bindings/iio/light/capella,cm3605.yaml
+++ b/dts/Bindings/iio/light/capella,cm3605.yaml
@@ -48,7 +48,6 @@ properties:
vdd-supply: true
capella,aset-resistance-ohms:
- $ref: /schemas/types.yaml#/definitions/uint32
enum: [50000, 100000, 300000, 600000]
description: >
Sensitivity calibration resistance. Note that calibration curves
diff --git a/dts/Bindings/iio/light/upisemi,us5182.yaml b/dts/Bindings/iio/light/upisemi,us5182.yaml
index de5882cb33..dd78abe0ec 100644
--- a/dts/Bindings/iio/light/upisemi,us5182.yaml
+++ b/dts/Bindings/iio/light/upisemi,us5182.yaml
@@ -11,12 +11,12 @@ maintainers:
properties:
compatible:
- const: upisemi,asd5182
+ const: upisemi,usd5182
reg:
maxItems: 1
- upsemi,glass-coef:
+ upisemi,glass-coef:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
glass attenuation factor - compensation factor of resolution 1000
diff --git a/dts/Bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml b/dts/Bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml
new file mode 100644
index 0000000000..099b4be927
--- /dev/null
+++ b/dts/Bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ChromeOS EC MKBP Proximity Sensor
+
+maintainers:
+ - Stephen Boyd <swboyd@chromium.org>
+ - Benson Leung <bleung@chromium.org>
+ - Enric Balletbo i Serra <enric.balletbo@collabora.com>
+
+description: |
+ Google's ChromeOS EC sometimes has the ability to detect user proximity.
+ This is implemented on the EC as near/far logic and exposed to the OS
+ via an MKBP switch bit.
+
+properties:
+ compatible:
+ const: google,cros-ec-mkbp-proximity
+
+ label:
+ description: Name for proximity sensor
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ proximity {
+ compatible = "google,cros-ec-mkbp-proximity";
+ label = "proximity-wifi-lte";
+ };
diff --git a/dts/Bindings/iio/st,st-sensors.yaml b/dts/Bindings/iio/st,st-sensors.yaml
index db291a9390..7e98f47987 100644
--- a/dts/Bindings/iio/st,st-sensors.yaml
+++ b/dts/Bindings/iio/st,st-sensors.yaml
@@ -66,6 +66,7 @@ properties:
- st,lis3mdl-magn
- st,lis2mdl
- st,lsm9ds1-magn
+ - st,iis2mdc
# Pressure sensors
- st,lps001wp-press
- st,lps25h-press
diff --git a/dts/Bindings/index.rst b/dts/Bindings/index.rst
index 3837b17c23..d9002a3a0a 100644
--- a/dts/Bindings/index.rst
+++ b/dts/Bindings/index.rst
@@ -1,12 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0
-===========
-Device Tree
-===========
-
.. toctree::
:maxdepth: 1
ABI
- submitting-patches
writing-bindings
+ writing-schema
+ submitting-patches
diff --git a/dts/Bindings/infiniband/hisilicon-hns-roce.txt b/dts/Bindings/infiniband/hisilicon-hns-roce.txt
index 84f1a1b505..be31cf05cd 100644
--- a/dts/Bindings/infiniband/hisilicon-hns-roce.txt
+++ b/dts/Bindings/infiniband/hisilicon-hns-roce.txt
@@ -1,7 +1,7 @@
Hisilicon RoCE DT description
Hisilicon RoCE engine is a part of network subsystem.
-It works depending on other part of network wubsytem, such as, gmac and
+It works depending on other part of network subsystem, such as gmac and
dsa fabric.
Additional properties are described here:
diff --git a/dts/Bindings/input/atmel,maxtouch.yaml b/dts/Bindings/input/atmel,maxtouch.yaml
index 8c6418f76e..3ec579d635 100644
--- a/dts/Bindings/input/atmel,maxtouch.yaml
+++ b/dts/Bindings/input/atmel,maxtouch.yaml
@@ -39,6 +39,13 @@ properties:
(active low). The line must be flagged with
GPIO_ACTIVE_LOW.
+ wake-gpios:
+ maxItems: 1
+ description:
+ Optional GPIO specifier for the touchscreen's wake pin
+ (active low). The line must be flagged with
+ GPIO_ACTIVE_LOW.
+
linux,gpio-keymap:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
@@ -53,6 +60,29 @@ properties:
or experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
+ atmel,wakeup-method:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The WAKE line is an active-low input that is used to wake up the touch
+ controller from deep-sleep mode before communication with the controller
+ could be started. This optional feature used to minimize current
+ consumption when the controller is in deep sleep mode. This feature is
+ relevant only to some controller families, like mXT1386 controller for
+ example.
+
+ The WAKE pin can be connected in one of the following ways:
+ 1) left permanently low
+ 2) connected to the I2C-compatible SCL pin
+ 3) connected to a GPIO pin on the host
+ enum:
+ - 0 # ATMEL_MXT_WAKEUP_NONE
+ - 1 # ATMEL_MXT_WAKEUP_I2C_SCL
+ - 2 # ATMEL_MXT_WAKEUP_GPIO
+ default: 0
+
+ wakeup-source:
+ type: boolean
+
required:
- compatible
- reg
@@ -63,6 +93,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/input/atmel-maxtouch.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
@@ -75,6 +106,7 @@ examples:
reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
vdda-supply = <&ab8500_ldo_aux2_reg>;
vdd-supply = <&ab8500_ldo_aux5_reg>;
+ atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
};
};
diff --git a/dts/Bindings/input/input.yaml b/dts/Bindings/input/input.yaml
index ab407f266b..74244d21d2 100644
--- a/dts/Bindings/input/input.yaml
+++ b/dts/Bindings/input/input.yaml
@@ -32,6 +32,12 @@ properties:
Duration in seconds which the key should be kept pressed for device to
power off automatically. Device with key pressed shutdown feature can
specify this property.
+
+ reset-time-sec:
+ description:
+ Duration in seconds which the key should be kept pressed for device to
+ reset automatically. Device with key pressed reset feature can specify
+ this property.
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: true
diff --git a/dts/Bindings/input/iqs626a.yaml b/dts/Bindings/input/iqs626a.yaml
new file mode 100644
index 0000000000..0cb736c541
--- /dev/null
+++ b/dts/Bindings/input/iqs626a.yaml
@@ -0,0 +1,843 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/iqs626a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Azoteq IQS626A Capacitive Touch Controller
+
+maintainers:
+ - Jeff LaBundy <jeff@labundy.com>
+
+description: |
+ The Azoteq IQS626A is a 14-channel capacitive touch controller that features
+ additional Hall-effect and inductive sensing capabilities.
+
+ Link to datasheet: https://www.azoteq.com/
+
+allOf:
+ - $ref: touchscreen/touchscreen.yaml#
+
+properties:
+ compatible:
+ const: azoteq,iqs626a
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ azoteq,suspend-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the power mode during suspend as follows:
+ 0: Automatic (same as normal runtime, i.e. suspend/resume disabled)
+ 1: Low power (all sensing at a reduced reporting rate)
+ 2: Ultra-low power (ULP channel proximity sensing)
+ 3: Halt (no sensing)
+
+ azoteq,clk-div:
+ type: boolean
+ description: Divides the device's core clock by a factor of 4.
+
+ azoteq,ulp-enable:
+ type: boolean
+ description:
+ Permits the device to automatically enter ultra-low-power mode from low-
+ power mode.
+
+ azoteq,ulp-update:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ default: 3
+ description: |
+ Specifies the rate at which the trackpad, generic and Hall channels are
+ updated during ultra-low-power mode as follows:
+ 0: 8
+ 1: 13
+ 2: 28
+ 3: 54
+ 4: 89
+ 5: 135
+ 6: 190
+ 7: 256
+
+ azoteq,ati-band-disable:
+ type: boolean
+ description: Disables the ATI band check.
+
+ azoteq,ati-lp-only:
+ type: boolean
+ description: Limits automatic ATI to low-power mode.
+
+ azoteq,gpio3-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ default: 1
+ description: |
+ Selects the channel or group of channels for which the GPIO3 pin
+ represents touch state as follows:
+ 0: None
+ 1: ULP channel
+ 2: Trackpad
+ 3: Trackpad
+ 4: Generic channel 0
+ 5: Generic channel 1
+ 6: Generic channel 2
+ 7: Hall channel
+
+ azoteq,reseed-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the event(s) that prompt the device to reseed (i.e. reset the
+ long-term average) of an associated channel as follows:
+ 0: None
+ 1: Proximity
+ 2: Proximity or touch
+ 3: Proximity, touch or deep touch
+
+ azoteq,thresh-extend:
+ type: boolean
+ description: Multiplies all touch and deep-touch thresholds by 4.
+
+ azoteq,tracking-enable:
+ type: boolean
+ description:
+ Enables all associated channels to track their respective reference
+ channels.
+
+ azoteq,reseed-offset:
+ type: boolean
+ description:
+ Applies an 8-count offset to all long-term averages upon either ATI or
+ reseed events.
+
+ azoteq,rate-np-ms:
+ minimum: 0
+ maximum: 255
+ default: 150
+ description: Specifies the report rate (in ms) during normal-power mode.
+
+ azoteq,rate-lp-ms:
+ minimum: 0
+ maximum: 255
+ default: 150
+ description: Specifies the report rate (in ms) during low-power mode.
+
+ azoteq,rate-ulp-ms:
+ multipleOf: 16
+ minimum: 0
+ maximum: 4080
+ default: 0
+ description: Specifies the report rate (in ms) during ultra-low-power mode.
+
+ azoteq,timeout-pwr-ms:
+ multipleOf: 512
+ minimum: 0
+ maximum: 130560
+ default: 2560
+ description:
+ Specifies the length of time (in ms) to wait for an event before moving
+ from normal-power mode to low-power mode, or (if 'azoteq,ulp-enable' is
+ present) from low-power mode to ultra-low-power mode.
+
+ azoteq,timeout-lta-ms:
+ multipleOf: 512
+ minimum: 0
+ maximum: 130560
+ default: 40960
+ description:
+ Specifies the length of time (in ms) to wait before resetting the long-
+ term average of all channels. Specify the maximum timeout to disable it
+ altogether.
+
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+
+patternProperties:
+ "^ulp-0|generic-[0-2]|hall$":
+ type: object
+ description:
+ Represents a single sensing channel. A channel is active if defined and
+ inactive otherwise.
+
+ properties:
+ azoteq,ati-exclude:
+ type: boolean
+ description:
+ Prevents the channel from participating in an ATI event that is
+ manually triggered during initialization.
+
+ azoteq,reseed-disable:
+ type: boolean
+ description:
+ Prevents the channel from being reseeded if the long-term average
+ timeout (defined in 'azoteq,timeout-lta') expires.
+
+ azoteq,meas-cap-decrease:
+ type: boolean
+ description:
+ Decreases the internal measurement capacitance from 60 pF to 15 pF.
+
+ azoteq,rx-inactive:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ default: 0
+ description: |
+ Specifies how inactive CRX pins are to be terminated as follows:
+ 0: VSS
+ 1: Floating
+ 2: VREG (generic channels only)
+
+ azoteq,linearize:
+ type: boolean
+ description:
+ Enables linearization of the channel's counts (generic and Hall
+ channels) or inverts the polarity of the channel's proximity or
+ touch states (ULP channel).
+
+ azoteq,dual-direction:
+ type: boolean
+ description:
+ Specifies that the channel's long-term average is to freeze in the
+ presence of either increasing or decreasing counts, thereby permit-
+ ting events to be reported in either direction.
+
+ azoteq,filt-disable:
+ type: boolean
+ description: Disables raw count filtering for the channel.
+
+ azoteq,ati-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ description: |
+ Specifies the channel's ATI mode as follows:
+ 0: Disabled
+ 1: Semi-partial
+ 2: Partial
+ 3: Full
+
+ The default value is a function of the channel and the device's reset
+ user interface (RUI); reference the datasheet for further information
+ about the available RUI options.
+
+ azoteq,ati-base:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [75, 100, 150, 200]
+ description:
+ Specifies the channel's ATI base. The default value is a function
+ of the channel and the device's RUI.
+
+ azoteq,ati-target:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ multipleOf: 32
+ minimum: 0
+ maximum: 2016
+ description:
+ Specifies the channel's ATI target. The default value is a function
+ of the channel and the device's RUI.
+
+ azoteq,cct-increase:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 16
+ default: 0
+ description:
+ Specifies the degree to which the channel's charge cycle time is to
+ be increased, with 0 representing no increase. The maximum value is
+ limited to 4 in the case of the ULP channel, and the property is un-
+ available entirely in the case of the Hall channel.
+
+ azoteq,proj-bias:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the bias current applied during projected-capacitance
+ sensing as follows:
+ 0: 2.5 uA
+ 1: 5 uA
+ 2: 10 uA
+ 3: 20 uA
+
+ This property is unavailable in the case of the Hall channel.
+
+ azoteq,sense-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ description: |
+ Specifies the channel's sensing frequency as follows (parenthesized
+ numbers represent the frequency if 'azoteq,clk-div' is present):
+ 0: 4 MHz (1 MHz)
+ 1: 2 MHz (500 kHz)
+ 2: 1 MHz (250 kHz)
+ 3: 500 kHz (125 kHz)
+
+ This property is unavailable in the case of the Hall channel. The
+ default value is a function of the channel and the device's RUI.
+
+ azoteq,ati-band-tighten:
+ type: boolean
+ description:
+ Tightens the ATI band from 1/8 to 1/16 of the desired target (ULP and
+ generic channels only).
+
+ azoteq,proj-enable:
+ type: boolean
+ description: Enables projected-capacitance sensing (ULP channel only).
+
+ azoteq,filt-str-np-cnt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Specifies the raw count filter strength during normal-power mode (ULP
+ and generic channels only).
+
+ azoteq,filt-str-lp-cnt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Specifies the raw count filter strength during low-power mode (ULP and
+ generic channels only).
+
+ azoteq,filt-str-np-lta:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Specifies the long-term average filter strength during normal-power
+ mode (ULP and generic channels only).
+
+ azoteq,filt-str-lp-lta:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Specifies the long-term average filter strength during low-power mode
+ (ULP and generic channels only).
+
+ azoteq,rx-enable:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+ items:
+ minimum: 0
+ maximum: 7
+ description:
+ Specifies the CRX pin(s) associated with the channel.
+
+ This property is unavailable in the case of the Hall channel. The
+ default value is a function of the channel and the device's RUI.
+
+ azoteq,tx-enable:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+ items:
+ minimum: 0
+ maximum: 7
+ description:
+ Specifies the TX pin(s) associated with the channel.
+
+ This property is unavailable in the case of the Hall channel. The
+ default value is a function of the channel and the device's RUI.
+
+ azoteq,local-cap-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4]
+ default: 0
+ description: |
+ Specifies the capacitance to be added to the channel as follows:
+ 0: 0 pF
+ 1: 0.5 pF
+ 2: 1.0 pF
+ 3: 1.5 pF
+ 4: 2.0 pF
+
+ This property is unavailable in the case of the ULP or Hall channels.
+
+ azoteq,sense-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 8, 9, 12, 14, 15]
+ description: |
+ Specifies the channel's sensing mode as follows:
+ 0: Self capacitance
+ 1: Projected capacitance
+ 8: Self inductance
+ 9: Mutual inductance
+ 12: External
+ 14: Hall effect
+ 15: Temperature
+
+ This property is unavailable in the case of the ULP or Hall channels.
+ The default value is a function of the channel and the device's RUI.
+
+ azoteq,tx-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the inductive sensing excitation frequency as follows
+ (parenthesized numbers represent the frequency if 'azoteq,clk-div'
+ is present):
+ 0: 16 MHz (4 MHz)
+ 1: 8 MHz (2 MHz)
+ 2: 4 MHz (1 MHz)
+ 3: 2 MHz (500 kHz)
+
+ This property is unavailable in the case of the ULP or Hall channels.
+
+ azoteq,invert-enable:
+ type: boolean
+ description:
+ Inverts the polarity of the states reported for proximity, touch and
+ deep-touch events relative to their respective thresholds (generic
+ channels only).
+
+ azoteq,comp-disable:
+ type: boolean
+ description:
+ Disables compensation for the channel (generic channels only).
+
+ azoteq,static-enable:
+ type: boolean
+ description:
+ Enables the static front-end for the channel (generic channels only).
+
+ azoteq,assoc-select:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ minItems: 1
+ maxItems: 6
+ items:
+ enum:
+ - ulp-0
+ - trackpad-3x2
+ - trackpad-3x3
+ - generic-0
+ - generic-1
+ - generic-2
+ - hall
+ description:
+ Specifies the associated channels for which the channel serves as a
+ reference channel. By default, no channels are selected. This prop-
+ erty is only available for the generic channels.
+
+ azoteq,assoc-weight:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+ default: 0
+ description:
+ Specifies the channel's impact weight if it acts as an associated
+ channel (0 = 0% impact, 255 = 200% impact). This property is only
+ available for the generic channels.
+
+ patternProperties:
+ "^event-(prox|touch|deep)(-alt)?$":
+ type: object
+ description:
+ Represents a proximity, touch or deep-touch event reported by the
+ channel in response to a decrease in counts. Node names suffixed with
+ '-alt' instead correspond to an increase in counts.
+
+ By default, the long-term average tracks an increase in counts such
+ that only events corresponding to a decrease in counts are reported
+ (refer to the datasheet for more information).
+
+ Specify 'azoteq,dual-direction' to freeze the long-term average when
+ the counts increase or decrease such that events of either direction
+ can be reported. Alternatively, specify 'azoteq,invert-enable' to in-
+ vert the polarity of the states reported by the channel.
+
+ Complementary events (e.g. event-touch and event-touch-alt) can both
+ be present and specify different key or switch codes, but not differ-
+ ent thresholds or hysteresis (if applicable).
+
+ Proximity events are unavailable in the case of the Hall channel, and
+ deep-touch events are only available for the generic channels. Unless
+ otherwise specified, default values are a function of the channel and
+ the device's RUI.
+
+ properties:
+ azoteq,thresh:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+ description: Specifies the threshold for the event.
+
+ azoteq,hyst:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ description:
+ Specifies the hysteresis for the event (touch and deep-touch
+ events only).
+
+ linux,code:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Numeric key or switch code associated with the event.
+
+ linux,input-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 5]
+ description:
+ Specifies whether the event is to be interpreted as a key (1) or
+ a switch (5). By default, Hall-channel events are interpreted as
+ switches and all others are interpreted as keys.
+
+ dependencies:
+ linux,input-type: ["linux,code"]
+
+ additionalProperties: false
+
+ dependencies:
+ azoteq,assoc-weight: ["azoteq,assoc-select"]
+
+ additionalProperties: false
+
+ "^trackpad-3x[2-3]$":
+ type: object
+ description:
+ Represents all channels associated with the trackpad. The channels are
+ collectively active if the trackpad is defined and inactive otherwise.
+
+ properties:
+ azoteq,ati-exclude:
+ type: boolean
+ description:
+ Prevents the trackpad channels from participating in an ATI event
+ that is manually triggered during initialization.
+
+ azoteq,reseed-disable:
+ type: boolean
+ description:
+ Prevents the trackpad channels from being reseeded if the long-term
+ average timeout (defined in 'azoteq,timeout-lta') expires.
+
+ azoteq,meas-cap-decrease:
+ type: boolean
+ description:
+ Decreases the internal measurement capacitance from 60 pF to 15 pF.
+
+ azoteq,rx-inactive:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ default: 0
+ description: |
+ Specifies how inactive CRX pins are to be terminated as follows:
+ 0: VSS
+ 1: Floating
+
+ azoteq,linearize:
+ type: boolean
+ description: Inverts the polarity of the trackpad's touch state.
+
+ azoteq,dual-direction:
+ type: boolean
+ description:
+ Specifies that the trackpad's long-term averages are to freeze in
+ the presence of either increasing or decreasing counts, thereby
+ permitting events to be reported in either direction.
+
+ azoteq,filt-disable:
+ type: boolean
+ description: Disables raw count filtering for the trackpad channels.
+
+ azoteq,ati-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the trackpad's ATI mode as follows:
+ 0: Disabled
+ 1: Semi-partial
+ 2: Partial
+ 3: Full
+
+ azoteq,ati-base:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 6
+ maxItems: 9
+ items:
+ minimum: 45
+ maximum: 300
+ default: [45, 45, 45, 45, 45, 45, 45, 45, 45]
+ description: Specifies each individual trackpad channel's ATI base.
+
+ azoteq,ati-target:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ multipleOf: 32
+ minimum: 0
+ maximum: 2016
+ default: 0
+ description: Specifies the trackpad's ATI target.
+
+ azoteq,cct-increase:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 4
+ default: 0
+ description:
+ Specifies the degree to which the trackpad's charge cycle time is to
+ be increased, with 0 representing no increase.
+
+ azoteq,proj-bias:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the bias current applied during projected-capacitance
+ sensing as follows:
+ 0: 2.5 uA
+ 1: 5 uA
+ 2: 10 uA
+ 3: 20 uA
+
+ azoteq,sense-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Specifies the trackpad's sensing frequency as follows (parenthesized
+ numbers represent the frequency if 'azoteq,clk-div' is present):
+ 0: 4 MHz (1 MHz)
+ 1: 2 MHz (500 kHz)
+ 2: 1 MHz (250 kHz)
+ 3: 500 kHz (125 kHz)
+
+ azoteq,ati-band-tighten:
+ type: boolean
+ description:
+ Tightens the ATI band from 1/8 to 1/16 of the desired target.
+
+ azoteq,thresh:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 6
+ maxItems: 9
+ items:
+ minimum: 0
+ maximum: 255
+ default: [0, 0, 0, 0, 0, 0, 0, 0, 0]
+ description:
+ Specifies each individual trackpad channel's touch threshold.
+
+ azoteq,hyst:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ default: 0
+ description: Specifies the trackpad's touch hysteresis.
+
+ azoteq,lta-update:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ default: 0
+ description: |
+ Specifies the update rate of the trackpad's long-term average during
+ ultra-low-power mode as follows:
+ 0: 2
+ 1: 4
+ 2: 8
+ 3: 16
+ 4: 32
+ 5: 64
+ 6: 128
+ 7: 255
+
+ azoteq,filt-str-trackpad:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: Specifies the trackpad coordinate filter strength.
+
+ azoteq,filt-str-np-cnt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Specifies the raw count filter strength during normal-power mode.
+
+ azoteq,filt-str-lp-cnt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Specifies the raw count filter strength during low-power mode.
+
+ linux,keycodes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 6
+ description: |
+ Specifies the numeric keycodes associated with each available gesture
+ in the following order (enter 0 for unused gestures):
+ 0: Positive flick or swipe in X direction
+ 1: Negative flick or swipe in X direction
+ 2: Positive flick or swipe in Y direction
+ 3: Negative flick or swipe in Y direction
+ 4: Tap
+ 5: Hold
+
+ azoteq,gesture-swipe:
+ type: boolean
+ description:
+ Directs the device to interpret axial gestures as a swipe (finger
+ remains on trackpad) instead of a flick (finger leaves trackpad).
+
+ azoteq,timeout-tap-ms:
+ multipleOf: 16
+ minimum: 0
+ maximum: 4080
+ default: 0
+ description:
+ Specifies the length of time (in ms) within which a trackpad touch
+ must be released in order to be interpreted as a tap.
+
+ azoteq,timeout-swipe-ms:
+ multipleOf: 16
+ minimum: 0
+ maximum: 4080
+ default: 0
+ description:
+ Specifies the length of time (in ms) within which an axial gesture
+ must be completed in order to be interpreted as a flick or swipe.
+
+ azoteq,thresh-swipe:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+ default: 0
+ description:
+ Specifies the number of points across which an axial gesture must
+ travel in order to be interpreted as a flick or swipe.
+
+ dependencies:
+ azoteq,gesture-swipe: ["linux,keycodes"]
+ azoteq,timeout-tap-ms: ["linux,keycodes"]
+ azoteq,timeout-swipe-ms: ["linux,keycodes"]
+ azoteq,thresh-swipe: ["linux,keycodes"]
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ iqs626a@44 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "azoteq,iqs626a";
+ reg = <0x44>;
+ interrupt-parent = <&gpio>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+
+ azoteq,rate-np-ms = <16>;
+ azoteq,rate-lp-ms = <160>;
+
+ azoteq,timeout-pwr-ms = <2560>;
+ azoteq,timeout-lta-ms = <32768>;
+
+ ulp-0 {
+ azoteq,meas-cap-decrease;
+
+ azoteq,ati-base = <75>;
+ azoteq,ati-target = <1024>;
+
+ azoteq,rx-enable = <2>, <3>, <4>,
+ <5>, <6>, <7>;
+
+ event-prox {
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ trackpad-3x3 {
+ azoteq,filt-str-np-cnt = <1>;
+ azoteq,filt-str-lp-cnt = <1>;
+
+ azoteq,hyst = <4>;
+ azoteq,thresh = <35>, <40>, <40>,
+ <38>, <33>, <38>,
+ <35>, <35>, <35>;
+
+ azoteq,ati-mode = <3>;
+ azoteq,ati-base = <195>, <195>, <195>,
+ <195>, <195>, <195>,
+ <195>, <195>, <195>;
+ azoteq,ati-target = <512>;
+
+ azoteq,proj-bias = <1>;
+ azoteq,sense-freq = <2>;
+
+ linux,keycodes = <KEY_VOLUMEUP>,
+ <KEY_VOLUMEDOWN>,
+ <KEY_NEXTSONG>,
+ <KEY_PREVIOUSSONG>,
+ <KEY_PLAYPAUSE>,
+ <KEY_STOPCD>;
+
+ azoteq,gesture-swipe;
+ azoteq,timeout-swipe-ms = <800>;
+ azoteq,timeout-tap-ms = <400>;
+ azoteq,thresh-swipe = <40>;
+ };
+
+ /*
+ * Preserve the default register settings for
+ * the temperature-tracking channel leveraged
+ * by reset user interface (RUI) 1.
+ *
+ * Scalar properties (e.g. ATI mode) are left
+ * untouched by simply omitting them; boolean
+ * properties must be specified explicitly as
+ * needed.
+ */
+ generic-2 {
+ azoteq,reseed-disable;
+ azoteq,meas-cap-decrease;
+ azoteq,dual-direction;
+ azoteq,comp-disable;
+ azoteq,static-enable;
+ };
+
+ hall {
+ azoteq,reseed-disable;
+ azoteq,meas-cap-decrease;
+
+ event-touch {
+ linux,code = <SW_LID>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/input/touchscreen/azoteq,iqs5xx.yaml b/dts/Bindings/input/touchscreen/azoteq,iqs5xx.yaml
new file mode 100644
index 0000000000..b5f377215c
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/azoteq,iqs5xx.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/azoteq,iqs5xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Azoteq IQS550/572/525 Trackpad/Touchscreen Controller
+
+maintainers:
+ - Jeff LaBundy <jeff@labundy.com>
+
+description: |
+ The Azoteq IQS550, IQS572 and IQS525 trackpad and touchscreen controllers
+ employ projected-capacitance sensing and can track up to five independent
+ contacts.
+
+ Link to datasheet: https://www.azoteq.com/
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - azoteq,iqs550
+ - azoteq,iqs572
+ - azoteq,iqs525
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ wakeup-source: true
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@74 {
+ compatible = "azoteq,iqs550";
+ reg = <0x74>;
+ interrupt-parent = <&gpio>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio 22 (GPIO_ACTIVE_LOW |
+ GPIO_PUSH_PULL)>;
+
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/input/touchscreen/hycon,hy46xx.yaml b/dts/Bindings/input/touchscreen/hycon,hy46xx.yaml
new file mode 100644
index 0000000000..942562f1e4
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/hycon,hy46xx.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/hycon,hy46xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hycon HY46XX series touchscreen controller bindings
+
+description: |
+ There are 6 variants of the chip for various touch panel sizes and cover lens material
+ Glass: 0.3mm--4.0mm
+ PET/PMMA: 0.2mm--2.0mm
+ HY4613(B)-N048 < 6"
+ HY4614(B)-N068 7" .. 10.1"
+ HY4621-NS32 < 5"
+ HY4623-NS48 5.1" .. 7"
+ Glass: 0.3mm--8.0mm
+ PET/PMMA: 0.2mm--4.0mm
+ HY4633(B)-N048 < 6"
+ HY4635(B)-N048 < 7" .. 10.1"
+
+maintainers:
+ - Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - hycon,hy4613
+ - hycon,hy4614
+ - hycon,hy4621
+ - hycon,hy4623
+ - hycon,hy4633
+ - hycon,hy4635
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ vcc-supply: true
+
+ hycon,threshold:
+ description: Allows setting the sensitivity in the range from 0 to 255.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+
+ hycon,glove-enable:
+ type: boolean
+ description: Allows enabling glove setting.
+
+ hycon,report-speed-hz:
+ description: Allows setting the report speed in Hertz.
+ minimum: 1
+ maximum: 255
+
+ hycon,noise-filter-enable:
+ type: boolean
+ description: Allows enabling power noise filter.
+
+ hycon,filter-data:
+ description: Allows setting how many samples throw before reporting touch
+ in the range from 0 to 5.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+
+ hycon,gain:
+ description: Allows setting the sensitivity distance in the range from 0 to 5.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+
+ hycon,edge-offset:
+ description: Allows setting the edge compensation in the range from 0 to 16.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 16
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-fuzz-x: true
+ touchscreen-fuzz-y: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+ interrupt-controller: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touchscreen@1c {
+ compatible = "hycon,hy4633";
+ reg = <0x1c>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/input/touchscreen/ilitek_ts_i2c.yaml b/dts/Bindings/input/touchscreen/ilitek_ts_i2c.yaml
new file mode 100644
index 0000000000..a190e7baac
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/ilitek_ts_i2c.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/ilitek_ts_i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek I2C Touchscreen Controller
+
+maintainers:
+ - Dmitry Torokhov <dmitry.torokhov@gmail.com>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ilitek,ili2130
+ - ilitek,ili2131
+ - ilitek,ili2132
+ - ilitek,ili2316
+ - ilitek,ili2322
+ - ilitek,ili2323
+ - ilitek,ili2326
+ - ilitek,ili2520
+ - ilitek,ili2521
+
+ reg:
+ const: 0x41
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ wakeup-source:
+ type: boolean
+ description: touchscreen can be used as a wakeup source.
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - reset-gpios
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@41 {
+ compatible = "ilitek,ili2520";
+ reg = <0x41>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ touchscreen-inverted-y;
+ wakeup-source;
+ };
+ };
diff --git a/dts/Bindings/input/touchscreen/iqs5xx.txt b/dts/Bindings/input/touchscreen/iqs5xx.txt
deleted file mode 100644
index efa0820e24..0000000000
--- a/dts/Bindings/input/touchscreen/iqs5xx.txt
+++ /dev/null
@@ -1,80 +0,0 @@
-Azoteq IQS550/572/525 Trackpad/Touchscreen Controller
-
-Required properties:
-
-- compatible : Must be equal to one of the following:
- "azoteq,iqs550"
- "azoteq,iqs572"
- "azoteq,iqs525"
-
-- reg : I2C slave address for the device.
-
-- interrupts : GPIO to which the device's active-high RDY
- output is connected (see [0]).
-
-- reset-gpios : GPIO to which the device's active-low NRST
- input is connected (see [1]).
-
-Optional properties:
-
-- touchscreen-min-x : See [2].
-
-- touchscreen-min-y : See [2].
-
-- touchscreen-size-x : See [2]. If this property is omitted, the
- maximum x-coordinate is specified by the
- device's "X Resolution" register.
-
-- touchscreen-size-y : See [2]. If this property is omitted, the
- maximum y-coordinate is specified by the
- device's "Y Resolution" register.
-
-- touchscreen-max-pressure : See [2]. Pressure is expressed as the sum of
- the deltas across all channels impacted by a
- touch event. A channel's delta is calculated
- as its count value minus a reference, where
- the count value is inversely proportional to
- the channel's capacitance.
-
-- touchscreen-fuzz-x : See [2].
-
-- touchscreen-fuzz-y : See [2].
-
-- touchscreen-fuzz-pressure : See [2].
-
-- touchscreen-inverted-x : See [2]. Inversion is applied relative to that
- which may already be specified by the device's
- FLIP_X and FLIP_Y register fields.
-
-- touchscreen-inverted-y : See [2]. Inversion is applied relative to that
- which may already be specified by the device's
- FLIP_X and FLIP_Y register fields.
-
-- touchscreen-swapped-x-y : See [2]. Swapping is applied relative to that
- which may already be specified by the device's
- SWITCH_XY_AXIS register field.
-
-[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-[1]: Documentation/devicetree/bindings/gpio/gpio.txt
-[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
-
-Example:
-
- &i2c1 {
- /* ... */
-
- touchscreen@74 {
- compatible = "azoteq,iqs550";
- reg = <0x74>;
- interrupt-parent = <&gpio>;
- interrupts = <17 4>;
- reset-gpios = <&gpio 27 1>;
-
- touchscreen-size-x = <640>;
- touchscreen-size-y = <480>;
-
- touchscreen-max-pressure = <16000>;
- };
-
- /* ... */
- };
diff --git a/dts/Bindings/input/touchscreen/melfas,mms114.yaml b/dts/Bindings/input/touchscreen/melfas,mms114.yaml
new file mode 100644
index 0000000000..62366886fb
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/melfas,mms114.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/melfas,mms114.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Melfas MMS114 family touchscreen controller bindings
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ $nodename:
+ pattern: "^touchscreen(@.*)?$"
+
+ compatible:
+ items:
+ - enum:
+ - melfas,mms114
+ - melfas,mms134s
+ - melfas,mms136
+ - melfas,mms152
+ - melfas,mms345l
+
+ reg:
+ description: I2C address
+
+ clock-frequency:
+ description: I2C client clock frequency, defined for host
+ minimum: 100000
+ maximum: 400000
+
+ interrupts:
+ maxItems: 1
+
+ avdd-supply:
+ description: Analog power supply regulator on AVDD pin
+
+ vdd-supply:
+ description: Digital power supply regulator on VDD pin
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-fuzz-x: true
+ touchscreen-fuzz-y: true
+ touchscreen-fuzz-pressure: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+ touchscreen-max-pressure: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - touchscreen-size-x
+ - touchscreen-size-y
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touchscreen@48 {
+ compatible = "melfas,mms114";
+ reg = <0x48>;
+ interrupt-parent = <&gpio>;
+ interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ avdd-supply = <&ldo1_reg>;
+ vdd-supply = <&ldo2_reg>;
+ touchscreen-size-x = <720>;
+ touchscreen-size-y = <1280>;
+ touchscreen-fuzz-x = <10>;
+ touchscreen-fuzz-y = <10>;
+ touchscreen-fuzz-pressure = <10>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+ };
+
+...
diff --git a/dts/Bindings/input/touchscreen/mms114.txt b/dts/Bindings/input/touchscreen/mms114.txt
deleted file mode 100644
index 707234cfd7..0000000000
--- a/dts/Bindings/input/touchscreen/mms114.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* MELFAS MMS114/MMS152/MMS345L touchscreen controller
-
-Required properties:
-- compatible: should be one of:
- - "melfas,mms114"
- - "melfas,mms152"
- - "melfas,mms345l"
-- reg: I2C address of the chip
-- interrupts: interrupt to which the chip is connected
-- touchscreen-size-x: See [1]
-- touchscreen-size-y: See [1]
-
-Optional properties:
-- touchscreen-fuzz-x: See [1]
-- touchscreen-fuzz-y: See [1]
-- touchscreen-fuzz-pressure: See [1]
-- touchscreen-inverted-x: See [1]
-- touchscreen-inverted-y: See [1]
-- touchscreen-swapped-x-y: See [1]
-
-[1]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
-
-Example:
-
- i2c@00000000 {
- /* ... */
-
- touchscreen@48 {
- compatible = "melfas,mms114";
- reg = <0x48>;
- interrupts = <39 0>;
- touchscreen-size-x = <720>;
- touchscreen-size-y = <1280>;
- touchscreen-fuzz-x = <10>;
- touchscreen-fuzz-y = <10>;
- touchscreen-fuzz-pressure = <10>;
- touchscreen-inverted-x;
- touchscreen-inverted-y;
- };
-
- /* ... */
- };
diff --git a/dts/Bindings/input/touchscreen/mstar,msg2638.yaml b/dts/Bindings/input/touchscreen/mstar,msg2638.yaml
new file mode 100644
index 0000000000..3a42c23faf
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/mstar,msg2638.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/mstar,msg2638.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar msg2638 touchscreen controller Bindings
+
+maintainers:
+ - Vincent Knecht <vincent.knecht@mailoo.org>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ const: mstar,msg2638
+
+ reg:
+ const: 0x26
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ vdd-supply:
+ description: Power supply regulator for the chip
+
+ vddio-supply:
+ description: Power supply regulator for the I2C bus
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - reset-gpios
+ - touchscreen-size-x
+ - touchscreen-size-y
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touchscreen@26 {
+ compatible = "mstar,msg2638";
+ reg = <0x26>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_reset_default>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l5>;
+ touchscreen-size-x = <2048>;
+ touchscreen-size-y = <2048>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/interconnect/qcom,rpmh.yaml b/dts/Bindings/interconnect/qcom,rpmh.yaml
index 799e73cdb9..cb6498108b 100644
--- a/dts/Bindings/interconnect/qcom,rpmh.yaml
+++ b/dts/Bindings/interconnect/qcom,rpmh.yaml
@@ -71,6 +71,16 @@ properties:
- qcom,sm8250-mmss-noc
- qcom,sm8250-npu-noc
- qcom,sm8250-system-noc
+ - qcom,sm8350-aggre1-noc
+ - qcom,sm8350-aggre2-noc
+ - qcom,sm8350-config-noc
+ - qcom,sm8350-dc-noc
+ - qcom,sm8350-gem-noc
+ - qcom,sm8350-lpass-ag-noc
+ - qcom,sm8350-mc-virt
+ - qcom,sm8350-mmss-noc
+ - qcom,sm8350-compute-noc
+ - qcom,sm8350-system-noc
'#interconnect-cells':
enum: [ 1, 2 ]
diff --git a/dts/Bindings/interconnect/qcom,sdm660.yaml b/dts/Bindings/interconnect/qcom,sdm660.yaml
new file mode 100644
index 0000000000..29de7807df
--- /dev/null
+++ b/dts/Bindings/interconnect/qcom,sdm660.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM660 Network-On-Chip interconnect
+
+maintainers:
+ - AngeloGioacchino Del Regno <kholk11@gmail.com>
+
+description: |
+ The Qualcomm SDM660 interconnect providers support adjusting the
+ bandwidth requirements between the various NoC fabrics.
+
+properties:
+ reg:
+ maxItems: 1
+
+ compatible:
+ enum:
+ - qcom,sdm660-a2noc
+ - qcom,sdm660-bimc
+ - qcom,sdm660-cnoc
+ - qcom,sdm660-gnoc
+ - qcom,sdm660-mnoc
+ - qcom,sdm660-snoc
+
+ '#interconnect-cells':
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - '#interconnect-cells'
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm660-mnoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Bus Clock.
+ - description: Bus A Clock.
+ - description: CPU-NoC High-performance Bus Clock.
+ clock-names:
+ items:
+ - const: bus
+ - const: bus_a
+ - const: iface
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm660-a2noc
+ - qcom,sdm660-bimc
+ - qcom,sdm660-cnoc
+ - qcom,sdm660-gnoc
+ - qcom,sdm660-snoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Bus Clock.
+ - description: Bus A Clock.
+ clock-names:
+ items:
+ - const: bus
+ - const: bus_a
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+
+ bimc: interconnect@1008000 {
+ compatible = "qcom,sdm660-bimc";
+ reg = <0x01008000 0x78000>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
+ cnoc: interconnect@1500000 {
+ compatible = "qcom,sdm660-cnoc";
+ reg = <0x01500000 0x10000>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+ <&rpmcc RPM_SMD_CNOC_A_CLK>;
+ };
+
+ snoc: interconnect@1626000 {
+ compatible = "qcom,sdm660-snoc";
+ reg = <0x01626000 0x7090>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
+
+ a2noc: interconnect@1704000 {
+ compatible = "qcom,sdm660-a2noc";
+ reg = <0x01704000 0xc100>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
+ <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
+ };
+
+ mnoc: interconnect@1745000 {
+ compatible = "qcom,sdm660-mnoc";
+ reg = <0x01745000 0xa010>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a", "iface";
+ clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
+ <&mmcc AHB_CLK_SRC>;
+ };
+
+ gnoc: interconnect@17900000 {
+ compatible = "qcom,sdm660-gnoc";
+ reg = <0x17900000 0xe000>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&xo_board>, <&xo_board>;
+ };
diff --git a/dts/Bindings/interrupt-controller/apple,aic.yaml b/dts/Bindings/interrupt-controller/apple,aic.yaml
new file mode 100644
index 0000000000..cf6c091a07
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/apple,aic.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple Interrupt Controller
+
+maintainers:
+ - Hector Martin <marcan@marcan.st>
+
+description: |
+ The Apple Interrupt Controller is a simple interrupt controller present on
+ Apple ARM SoC platforms, including various iPhone and iPad devices and the
+ "Apple Silicon" Macs.
+
+ It provides the following features:
+
+ - Level-triggered hardware IRQs wired to SoC blocks
+ - Single mask bit per IRQ
+ - Per-IRQ affinity setting
+ - Automatic masking on event delivery (auto-ack)
+ - Software triggering (ORed with hw line)
+ - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
+ if not symmetric)
+ - Automatic prioritization (single event/ack register per CPU, lower IRQs =
+ higher priority)
+ - Automatic masking on ack
+ - Default "this CPU" register view and explicit per-CPU views
+
+ This device also represents the FIQ interrupt sources on platforms using AIC,
+ which do not go through a discrete interrupt controller.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: apple,t8103-aic
+ - const: apple,aic
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 3
+ description: |
+ The 1st cell contains the interrupt type:
+ - 0: Hardware IRQ
+ - 1: FIQ
+
+ The 2nd cell contains the interrupt number.
+ - HW IRQs: interrupt number
+ - FIQs:
+ - 0: physical HV timer
+ - 1: virtual HV timer
+ - 2: physical guest timer
+ - 3: virtual guest timer
+
+ The 3rd cell contains the interrupt flags. This is normally
+ IRQ_TYPE_LEVEL_HIGH (4).
+
+ reg:
+ description: |
+ Specifies base physical address and size of the AIC registers.
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aic: interrupt-controller@23b100000 {
+ compatible = "apple,t8103-aic", "apple,aic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x2 0x3b100000 0x0 0x8000>;
+ };
+ };
diff --git a/dts/Bindings/interrupt-controller/idt,32434-pic.yaml b/dts/Bindings/interrupt-controller/idt,32434-pic.yaml
new file mode 100644
index 0000000000..160ff4b07c
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/idt,32434-pic.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IDT 79RC32434 Interrupt Controller Device Tree Bindings
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ const: idt,32434-pic
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+required:
+ - "#interrupt-cells"
+ - compatible
+ - reg
+ - interrupt-controller
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ idtpic3: interrupt-controller@3800c {
+ compatible = "idt,32434-pic";
+ reg = <0x3800c 0x0c>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+...
diff --git a/dts/Bindings/interrupt-controller/loongson,htpic.yaml b/dts/Bindings/interrupt-controller/loongson,htpic.yaml
index d1d52d1db2..d6bc1a687f 100644
--- a/dts/Bindings/interrupt-controller/loongson,htpic.yaml
+++ b/dts/Bindings/interrupt-controller/loongson,htpic.yaml
@@ -47,7 +47,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
htintc: interrupt-controller@1fb000080 {
- compatible = "loongson,htintc-1.0";
+ compatible = "loongson,htpic-1.0";
reg = <0xfb000080 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
diff --git a/dts/Bindings/interrupt-controller/loongson,liointc.yaml b/dts/Bindings/interrupt-controller/loongson,liointc.yaml
index f38e0113f3..067165c4b8 100644
--- a/dts/Bindings/interrupt-controller/loongson,liointc.yaml
+++ b/dts/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -10,9 +10,9 @@ maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description: |
- This interrupt controller is found in the Loongson-3 family of chips as the primary
- package interrupt controller which can route local I/O interrupt to interrupt lines
- of cores.
+ This interrupt controller is found in the Loongson-3 family of chips and
+ Loongson-2K1000 chip, as the primary package interrupt controller which
+ can route local I/O interrupt to interrupt lines of cores.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
@@ -22,9 +22,17 @@ properties:
oneOf:
- const: loongson,liointc-1.0
- const: loongson,liointc-1.0a
+ - const: loongson,liointc-2.0
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: main
+ - const: isr0
+ - const: isr1
interrupt-controller: true
@@ -69,6 +77,26 @@ required:
unevaluatedProperties: false
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - loongson,liointc-2.0
+
+then:
+ properties:
+ reg:
+ minItems: 3
+
+ required:
+ - reg-names
+
+else:
+ properties:
+ reg:
+ maxItems: 1
+
examples:
- |
iointc: interrupt-controller@3ff01400 {
diff --git a/dts/Bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml b/dts/Bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
new file mode 100644
index 0000000000..9ce6804bdb
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/nuvoton,wpcm450-aic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton WPCM450 Advanced Interrupt Controller bindings
+
+maintainers:
+ - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+
+properties:
+ '#interrupt-cells':
+ const: 2
+
+ compatible:
+ const: nuvoton,wpcm450-aic
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - '#interrupt-cells'
+ - compatible
+ - reg
+ - interrupt-controller
+
+examples:
+ - |
+ aic: interrupt-controller@b8002000 {
+ compatible = "nuvoton,wpcm450-aic";
+ reg = <0xb8002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.txt b/dts/Bindings/interrupt-controller/qcom,pdc.txt
index e9afb48182..98d89e5301 100644
--- a/dts/Bindings/interrupt-controller/qcom,pdc.txt
+++ b/dts/Bindings/interrupt-controller/qcom,pdc.txt
@@ -19,6 +19,7 @@ Properties:
Value type: <string>
Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
- "qcom,sc7180-pdc": For SC7180
+ - "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350
diff --git a/dts/Bindings/iommu/arm,smmu.yaml b/dts/Bindings/iommu/arm,smmu.yaml
index 6ba161dea4..9d27aa5111 100644
--- a/dts/Bindings/iommu/arm,smmu.yaml
+++ b/dts/Bindings/iommu/arm,smmu.yaml
@@ -34,6 +34,7 @@ properties:
items:
- enum:
- qcom,sc7180-smmu-500
+ - qcom,sc7280-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sdm845-smmu-500
- qcom,sm8150-smmu-500
diff --git a/dts/Bindings/iommu/sprd,iommu.yaml b/dts/Bindings/iommu/sprd,iommu.yaml
new file mode 100644
index 0000000000..7003e12f55
--- /dev/null
+++ b/dts/Bindings/iommu/sprd,iommu.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2020 Unisoc Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc IOMMU and Multi-media MMU
+
+maintainers:
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - sprd,iommu-v1
+
+ "#iommu-cells":
+ const: 0
+ description:
+ Unisoc IOMMUs are all single-master IOMMU devices, therefore no
+ additional information needs to associate with its master device.
+ Please refer to the generic bindings document for more details,
+ Documentation/devicetree/bindings/iommu/iommu.txt
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ Reference to a gate clock phandle, since access to some of IOMMUs are
+ controlled by gate clock, but this is not required.
+
+required:
+ - compatible
+ - reg
+ - "#iommu-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ iommu_disp: iommu@63000800 {
+ compatible = "sprd,iommu-v1";
+ reg = <0x63000800 0x80>;
+ #iommu-cells = <0>;
+ };
+
+ - |
+ iommu_jpg: iommu@62300300 {
+ compatible = "sprd,iommu-v1";
+ reg = <0x62300300 0x80>;
+ #iommu-cells = <0>;
+ clocks = <&mm_gate 1>;
+ };
+
+...
diff --git a/dts/Bindings/leds/backlight/kinetic,ktd253.yaml b/dts/Bindings/leds/backlight/kinetic,ktd253.yaml
index 7a6ec1f8c0..73fa59e621 100644
--- a/dts/Bindings/leds/backlight/kinetic,ktd253.yaml
+++ b/dts/Bindings/leds/backlight/kinetic,ktd253.yaml
@@ -4,13 +4,13 @@
$id: http://devicetree.org/schemas/leds/backlight/kinetic,ktd253.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Kinetic Technologies KTD253 one-wire backlight
+title: Kinetic Technologies KTD253 and KTD259 one-wire backlight
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
- The Kinetic Technologies KTD253 is a white LED backlight that is
+ The Kinetic Technologies KTD253 and KTD259 are white LED backlights
controlled by a single GPIO line. If you just turn on the backlight
it goes to maximum backlight then you can set the level of backlight
using pulses on the enable wire. This is sometimes referred to as
@@ -21,7 +21,10 @@ allOf:
properties:
compatible:
- const: kinetic,ktd253
+ items:
+ - enum:
+ - kinetic,ktd253
+ - kinetic,ktd259
enable-gpios:
description: GPIO to use to enable/disable and dim the backlight.
diff --git a/dts/Bindings/leds/backlight/qcom-wled.yaml b/dts/Bindings/leds/backlight/qcom-wled.yaml
index 47938e3729..d839e75d97 100644
--- a/dts/Bindings/leds/backlight/qcom-wled.yaml
+++ b/dts/Bindings/leds/backlight/qcom-wled.yaml
@@ -19,6 +19,7 @@ properties:
compatible:
enum:
- qcom,pm8941-wled
+ - qcom,pmi8994-wled
- qcom,pmi8998-wled
- qcom,pm660l-wled
- qcom,pm8150l-wled
diff --git a/dts/Bindings/leds/leds-lgm.yaml b/dts/Bindings/leds/leds-lgm.yaml
index 32bbf146c0..f8d7963c3a 100644
--- a/dts/Bindings/leds/leds-lgm.yaml
+++ b/dts/Bindings/leds/leds-lgm.yaml
@@ -14,6 +14,17 @@ properties:
compatible:
const: intel,lgm-ssoled
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: sso
+ - const: fpid
+
gpio-controller: true
'#gpio-cells':
@@ -36,8 +47,15 @@ properties:
additionalProperties: false
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
patternProperties:
- "^led@[0-23]$":
+ "^led@[0-2]$":
type: object
properties:
@@ -81,7 +99,7 @@ examples:
#include <dt-bindings/leds/common.h>
ssogpio: ssogpio@e0d40000 {
- compatible = "intel,sso-led";
+ compatible = "intel,lgm-ssoled";
reg = <0xE0D40000 0x2E4>;
gpio-controller;
#gpio-cells = <2>;
@@ -103,8 +121,8 @@ examples:
led-gpio = <&ssogpio 0 0>;
};
- led@23 {
- reg = <23>;
+ led@2 {
+ reg = <2>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
led-gpio = <&ssogpio 23 0>;
diff --git a/dts/Bindings/leds/leds-rt4505.yaml b/dts/Bindings/leds/leds-rt4505.yaml
new file mode 100644
index 0000000000..5b0c74aa67
--- /dev/null
+++ b/dts/Bindings/leds/leds-rt4505.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/leds-rt4505.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Richtek RT4505 Single Channel LED Driver
+
+maintainers:
+ - ChiYuan Huang <cy_huang@richtek.com>
+
+description: |
+ The RT4505 is a flash LED driver that can support up to 375mA and 1.5A for
+ torch and flash mode, respectively.
+
+ The data sheet can be found at:
+ https://www.richtek.com/assets/product_file/RT4505/DS4505-02.pdf
+
+properties:
+ compatible:
+ const: richtek,rt4505
+
+ reg:
+ description: I2C slave address of the controller.
+ maxItems: 1
+
+ led:
+ type: object
+ $ref: common.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@63 {
+ compatible = "richtek,rt4505";
+ reg = <0x63>;
+
+ rt4505_flash: led {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-max-microamp = <375000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <800000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/mailbox/fsl,mu.yaml b/dts/Bindings/mailbox/fsl,mu.yaml
index 15cef82cd3..1a3dff277e 100644
--- a/dts/Bindings/mailbox/fsl,mu.yaml
+++ b/dts/Bindings/mailbox/fsl,mu.yaml
@@ -34,12 +34,15 @@ properties:
- fsl,imx8mm-mu
- fsl,imx8mn-mu
- fsl,imx8mp-mu
+ - fsl,imx8qm-mu
- fsl,imx8qxp-mu
- const: fsl,imx6sx-mu
- description: To communicate with i.MX8 SCU with fast IPC
items:
- const: fsl,imx8-mu-scu
- - const: fsl,imx8qxp-mu
+ - enum:
+ - fsl,imx8qm-mu
+ - fsl,imx8qxp-mu
- const: fsl,imx6sx-mu
reg:
diff --git a/dts/Bindings/mailbox/qcom-ipcc.yaml b/dts/Bindings/mailbox/qcom-ipcc.yaml
index 168beeb7e9..b222f993b2 100644
--- a/dts/Bindings/mailbox/qcom-ipcc.yaml
+++ b/dts/Bindings/mailbox/qcom-ipcc.yaml
@@ -25,6 +25,8 @@ properties:
items:
- enum:
- qcom,sm8250-ipcc
+ - qcom,sm8350-ipcc
+ - qcom,sc7280-ipcc
- const: qcom,ipcc
reg:
diff --git a/dts/Bindings/mailbox/sprd-mailbox.yaml b/dts/Bindings/mailbox/sprd-mailbox.yaml
index 26a5cca3f8..80feba82cb 100644
--- a/dts/Bindings/mailbox/sprd-mailbox.yaml
+++ b/dts/Bindings/mailbox/sprd-mailbox.yaml
@@ -15,6 +15,7 @@ properties:
compatible:
enum:
- sprd,sc9860-mailbox
+ - sprd,sc9863a-mailbox
reg:
items:
@@ -22,9 +23,15 @@ properties:
- description: outbox registers' base address
interrupts:
+ minItems: 2
+ maxItems: 3
+
+ interrupt-names:
+ minItems: 2
items:
- - description: inbox interrupt
- - description: outbox interrupt
+ - const: inbox
+ - const: outbox
+ - const: supp-outbox
clocks:
maxItems: 1
@@ -40,6 +47,7 @@ required:
- compatible
- reg
- interrupts
+ - interrupt-names
- "#mbox-cells"
- clocks
- clock-names
@@ -56,5 +64,6 @@ examples:
clock-names = "enable";
clocks = <&aon_gate 53>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "inbox", "outbox";
};
...
diff --git a/dts/Bindings/mailbox/ti,secure-proxy.txt b/dts/Bindings/mailbox/ti,secure-proxy.txt
deleted file mode 100644
index 6c9c7daf0f..0000000000
--- a/dts/Bindings/mailbox/ti,secure-proxy.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Texas Instruments' Secure Proxy
-========================================
-
-The Texas Instruments' secure proxy is a mailbox controller that has
-configurable queues selectable at SoC(System on Chip) integration. The
-Message manager is broken up into different address regions that are
-called "threads" or "proxies" - each instance is unidirectional and is
-instantiated at SoC integration level by system controller to indicate
-receive or transmit path.
-
-Message Manager Device Node:
-===========================
-Required properties:
---------------------
-- compatible: Shall be "ti,am654-secure-proxy"
-- reg-names target_data - Map the proxy data region
- rt - Map the realtime status region
- scfg - Map the configuration region
-- reg: Contains the register map per reg-names.
-- #mbox-cells Shall be 1 and shall refer to the transfer path
- called thread.
-- interrupt-names: Contains interrupt names matching the rx transfer path
- for a given SoC. Receive interrupts shall be of the
- format: "rx_<PID>".
-- interrupts: Contains the interrupt information corresponding to
- interrupt-names property.
-
-Example(AM654):
-------------
-
- secure_proxy: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x0 0x32c00000 0x0 0x100000>,
- <0x0 0x32400000 0x0 0x100000>,
- <0x0 0x32800000 0x0 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- dmsc: dmsc {
- [...]
- mbox-names = "rx", "tx";
- # RX Thread ID is 11
- # TX Thread ID is 13
- mboxes= <&secure_proxy 11>,
- <&secure_proxy 13>;
- [...]
- };
diff --git a/dts/Bindings/mailbox/ti,secure-proxy.yaml b/dts/Bindings/mailbox/ti,secure-proxy.yaml
new file mode 100644
index 0000000000..eea8228618
--- /dev/null
+++ b/dts/Bindings/mailbox/ti,secure-proxy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' Secure Proxy
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ The Texas Instruments' secure proxy is a mailbox controller that has
+ configurable queues selectable at SoC(System on Chip) integration. The
+ Message manager is broken up into different address regions that are
+ called "threads" or "proxies" - each instance is unidirectional and is
+ instantiated at SoC integration level by system controller to indicate
+ receive or transmit path.
+
+properties:
+ $nodename:
+ pattern: "^mailbox@[0-9a-f]+$"
+
+ compatible:
+ const: ti,am654-secure-proxy
+
+ "#mbox-cells":
+ const: 1
+ description:
+ Contains the secure proxy thread ID used for the specific transfer path.
+
+ reg-names:
+ items:
+ - const: target_data
+ - const: rt
+ - const: scfg
+
+ reg:
+ minItems: 3
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 100
+ items:
+ pattern: "^rx_[0-9]{3}$"
+ description:
+ Contains the interrupt name information for the Rx interrupt path for
+ secure proxy thread in the form 'rx_<PID>'.
+
+ interrupts:
+ minItems: 1
+ maxItems: 100
+ description:
+ Contains the interrupt information for the Rx interrupt path for secure
+ proxy.
+
+required:
+ - compatible
+ - reg-names
+ - reg
+ - interrupt-names
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ secure_proxy: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x32c00000 0x100000>,
+ <0x32400000 0x100000>,
+ <0x32800000 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml b/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml
index 5fa19d4aea..6d8395d6bc 100644
--- a/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml
+++ b/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml
@@ -20,16 +20,12 @@ properties:
- const: allwinner,sun5i-a13-ir
- const: allwinner,sun6i-a31-ir
- items:
- - const: allwinner,sun8i-a83t-ir
- - const: allwinner,sun6i-a31-ir
- - items:
- - const: allwinner,sun8i-r40-ir
- - const: allwinner,sun6i-a31-ir
- - items:
- - const: allwinner,sun50i-a64-ir
- - const: allwinner,sun6i-a31-ir
- - items:
- - const: allwinner,sun50i-h6-ir
+ - enum:
+ - allwinner,sun8i-a83t-ir
+ - allwinner,sun8i-r40-ir
+ - allwinner,sun50i-a64-ir
+ - allwinner,sun50i-h6-ir
+ - allwinner,sun50i-h616-ir
- const: allwinner,sun6i-a31-ir
reg:
diff --git a/dts/Bindings/media/mediatek-jpeg-decoder.txt b/dts/Bindings/media/mediatek-jpeg-decoder.txt
index cf60c5acc0..39c1028b2d 100644
--- a/dts/Bindings/media/mediatek-jpeg-decoder.txt
+++ b/dts/Bindings/media/mediatek-jpeg-decoder.txt
@@ -19,7 +19,7 @@ Required properties:
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
- iommus: should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
Example:
diff --git a/dts/Bindings/media/mediatek-jpeg-encoder.txt b/dts/Bindings/media/mediatek-jpeg-encoder.txt
index acfb50375b..5e53c6ab52 100644
--- a/dts/Bindings/media/mediatek-jpeg-encoder.txt
+++ b/dts/Bindings/media/mediatek-jpeg-encoder.txt
@@ -17,7 +17,7 @@ Required properties:
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
- iommus: should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
Example:
diff --git a/dts/Bindings/media/mediatek-mdp.txt b/dts/Bindings/media/mediatek-mdp.txt
index f4798d04e9..caa24943da 100644
--- a/dts/Bindings/media/mediatek-mdp.txt
+++ b/dts/Bindings/media/mediatek-mdp.txt
@@ -25,7 +25,7 @@ Required properties (DMA function blocks, child node):
"mediatek,mt8173-mdp-wdma"
"mediatek,mt8173-mdp-wrot"
- iommus: should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
- mediatek,larb: must contain the local arbiters in the current Socs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
diff --git a/dts/Bindings/media/mediatek-vcodec.txt b/dts/Bindings/media/mediatek-vcodec.txt
index 8217424fd4..06db6837ce 100644
--- a/dts/Bindings/media/mediatek-vcodec.txt
+++ b/dts/Bindings/media/mediatek-vcodec.txt
@@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
supports high resolution encoding and decoding functionalities.
Required properties:
-- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
+- compatible : must be one of the following string:
+ "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
+ "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
"mediatek,mt8183-vcodec-enc" for MT8183 encoder.
"mediatek,mt8173-vcodec-dec" for MT8173 decoder.
- reg : Physical base address of the video codec registers and length of
@@ -13,12 +15,12 @@ Required properties:
- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property.
-- clock-names: encoder must contain "venc_sel_src", "venc_sel",,
- "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
- "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
- "venc_lt_sel", "vdec_bus_clk_src".
+- clock-names: avc encoder must contain "venc_sel", vp8 encoder must
+ contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
+ "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
+ "vdec_bus_clk_src".
- iommus : should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
One of the two following nodes:
- mediatek,vpu : the node of the video processor unit, if using VPU.
@@ -80,14 +82,10 @@ vcodec_dec: vcodec@16000000 {
assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
};
- vcodec_enc: vcodec@18002000 {
+vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
- <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
+ reg = <0 0x18002000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -98,8 +96,20 @@ vcodec_dec: vcodec@16000000 {
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_NBM_WDMA>;
+ mediatek,larb = <&larb3>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ };
+
+vcodec_enc_vp8: vcodec@19002000 {
+ compatible = "mediatek,mt8173-vcodec-enc-vp8";
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
@@ -108,17 +118,10 @@ vcodec_dec: vcodec@16000000 {
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_lt_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
};
diff --git a/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml b/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml
index be47a7b62c..d8ed480482 100644
--- a/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml
+++ b/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml
@@ -4,14 +4,19 @@
$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: NXP i.MX7 Mipi CSI2
+title: NXP i.MX7 MIPI CSI-2 receiver
maintainers:
- Rui Miguel Silva <rmfrfs@gmail.com>
-description: |
- This is the device node for the MIPI CSI-2 receiver core in i.MX7 soc. It is
- compatible with previous version of samsung d-phy.
+description: |-
+ The NXP i.MX7 SoC family includes a MIPI CSI-2 receiver IP core, documented
+ as "CSIS V3.3". The IP core seems to originate from Samsung, and may be
+ compatible with some of the Exynos4 ad S5P SoCs.
+
+ While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
+ completely wrapped by the CSIS and doesn't expose a control interface of its
+ own. This binding thus covers both IP cores.
properties:
compatible:
@@ -24,8 +29,10 @@ properties:
maxItems: 1
clocks:
- minItems: 3
- maxItems: 3
+ items:
+ - description: The peripheral clock (a.k.a. APB clock)
+ - description: The external clock (optionally used as the pixel clock)
+ - description: The MIPI D-PHY clock
clock-names:
items:
@@ -37,26 +44,16 @@ properties:
maxItems: 1
phy-supply:
- description:
- Phandle to a regulator that provides power to the PHY. This
- regulator will be managed during the PHY power on/off sequence.
+ description: The MIPI D-PHY digital power supply
resets:
- maxItems: 1
-
- reset-names:
- const: mrst
+ items:
+ - description: MIPI D-PHY slave reset
clock-frequency:
- description:
- The IP main (system bus) clock frequency in Hertz
+ description: The desired external clock ("wrap") frequency, in Hz
default: 166000000
- fsl,csis-hs-settle:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Differential receiver (HS-RX) settle time
-
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -98,7 +95,6 @@ required:
- power-domains
- phy-supply
- resets
- - reset-names
- ports
additionalProperties: false
@@ -111,43 +107,41 @@ examples:
#include <dt-bindings/reset/imx7-reset.h>
mipi_csi: mipi-csi@30750000 {
- compatible = "fsl,imx7-mipi-csi2";
- reg = <0x30750000 0x10000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&clks IMX7D_IPG_ROOT_CLK>,
- <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
- <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
- clock-names = "pclk", "wrap", "phy";
- clock-frequency = <166000000>;
-
- power-domains = <&pgc_mipi_phy>;
- phy-supply = <&reg_1p0d>;
- resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
- reset-names = "mrst";
- fsl,csis-hs-settle = <3>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mipi_from_sensor: endpoint {
- remote-endpoint = <&ov2680_to_mipi>;
- data-lanes = <1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- mipi_vc0_to_csi_mux: endpoint {
- remote-endpoint = <&csi_mux_from_mipi_vc0>;
- };
- };
+ compatible = "fsl,imx7-mipi-csi2";
+ reg = <0x30750000 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+ clock-names = "pclk", "wrap", "phy";
+ clock-frequency = <166000000>;
+
+ power-domains = <&pgc_mipi_phy>;
+ phy-supply = <&reg_1p0d>;
+ resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_from_sensor: endpoint {
+ remote-endpoint = <&ov2680_to_mipi>;
+ data-lanes = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_vc0_to_csi_mux: endpoint {
+ remote-endpoint = <&csi_mux_from_mipi_vc0>;
+ };
};
+ };
};
...
diff --git a/dts/Bindings/media/nxp,imx8-jpeg.yaml b/dts/Bindings/media/nxp,imx8-jpeg.yaml
new file mode 100644
index 0000000000..5d13cbb525
--- /dev/null
+++ b/dts/Bindings/media/nxp,imx8-jpeg.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings
+
+maintainers:
+ - Mirela Rabulea <mirela.rabulea@nxp.com>
+
+description: |-
+ The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
+ ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
+ and Extended Sequential DCT modes.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ # JPEG decoder
+ - nxp,imx8qxp-jpgdec
+ # JPEG encoder
+ - nxp,imx8qxp-jpgenc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ There are 4 slots available in the IP, which the driver may use
+ If a certain slot is used, it should have an associated interrupt
+ The interrupt with index i is assumed to be for slot i
+ minItems: 1 # At least one slot is needed by the driver
+ maxItems: 4 # The IP has 4 slots available for use
+
+ power-domains:
+ description:
+ List of phandle and PM domain specifier as documented in
+ Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 2 # Wrapper and 1 slot
+ maxItems: 5 # Wrapper and 4 slots
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ jpegdec: jpegdec@58400000 {
+ compatible = "nxp,imx8qxp-jpgdec";
+ reg = <0x58400000 0x00050000 >;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
+ <&pd IMX_SC_R_MJPEG_DEC_S0>,
+ <&pd IMX_SC_R_MJPEG_DEC_S1>,
+ <&pd IMX_SC_R_MJPEG_DEC_S2>,
+ <&pd IMX_SC_R_MJPEG_DEC_S3>;
+ };
+
+ jpegenc: jpegenc@58450000 {
+ compatible = "nxp,imx8qxp-jpgenc";
+ reg = <0x58450000 0x00050000 >;
+ interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
+ <&pd IMX_SC_R_MJPEG_ENC_S0>,
+ <&pd IMX_SC_R_MJPEG_ENC_S1>,
+ <&pd IMX_SC_R_MJPEG_ENC_S2>,
+ <&pd IMX_SC_R_MJPEG_ENC_S3>;
+ };
+...
diff --git a/dts/Bindings/media/qcom,camss.txt b/dts/Bindings/media/qcom,camss.txt
deleted file mode 100644
index 498234629e..0000000000
--- a/dts/Bindings/media/qcom,camss.txt
+++ /dev/null
@@ -1,236 +0,0 @@
-Qualcomm Camera Subsystem
-
-* Properties
-
-- compatible:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain one of:
- - "qcom,msm8916-camss"
- - "qcom,msm8996-camss"
- - "qcom,sdm660-camss"
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Register ranges as listed in the reg-names property.
-- reg-names:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain the following entries:
- - "csiphy0"
- - "csiphy0_clk_mux"
- - "csiphy1"
- - "csiphy1_clk_mux"
- - "csiphy2" (8996 only)
- - "csiphy2_clk_mux" (8996 only)
- - "csid0"
- - "csid1"
- - "csid2" (8996 only)
- - "csid3" (8996 only)
- - "ispif"
- - "csi_clk_mux"
- - "vfe0"
- - "vfe1" (8996 only)
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Interrupts as listed in the interrupt-names property.
-- interrupt-names:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain the following entries:
- - "csiphy0"
- - "csiphy1"
- - "csiphy2" (8996 only)
- - "csid0"
- - "csid1"
- - "csid2" (8996 only)
- - "csid3" (8996 only)
- - "ispif"
- - "vfe0"
- - "vfe1" (8996 only)
-- power-domains:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A phandle and power domain specifier pairs to the
- power domain which is responsible for collapsing
- and restoring power to the peripheral.
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A list of phandle and clock specifier pairs as listed
- in clock-names property.
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain the following entries:
- - "top_ahb"
- - "throttle_axi" (660 only)
- - "ispif_ahb"
- - "csiphy0_timer"
- - "csiphy1_timer"
- - "csiphy2_timer" (8996 only)
- - "csiphy_ahb2crif" (660 only)
- - "csi0_ahb"
- - "csi0"
- - "csi0_phy"
- - "csi0_pix"
- - "csi0_rdi"
- - "cphy_csid0" (660 only)
- - "csi1_ahb"
- - "csi1"
- - "csi1_phy"
- - "csi1_pix"
- - "csi1_rdi"
- - "cphy_csid1" (660 only)
- - "csi2_ahb" (8996 only)
- - "csi2" (8996 only)
- - "csi2_phy" (8996 only)
- - "csi2_pix" (8996 only)
- - "csi2_rdi" (8996 only)
- - "cphy_csid2" (660 only)
- - "csi3_ahb" (8996 only)
- - "csi3" (8996 only)
- - "csi3_phy" (8996 only)
- - "csi3_pix" (8996 only)
- - "csi3_rdi" (8996 only)
- - "cphy_csid3" (660 only)
- - "ahb"
- - "vfe0"
- - "csi_vfe0"
- - "vfe0_ahb", (8996 only)
- - "vfe0_stream", (8996 only)
- - "vfe1", (8996 only)
- - "csi_vfe1", (8996 only)
- - "vfe1_ahb", (8996 only)
- - "vfe1_stream", (8996 only)
- - "vfe_ahb"
- - "vfe_axi"
-- vdda-supply:
- Usage: required
- Value type: <phandle>
- Definition: A phandle to voltage supply for CSI2.
-- iommus:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A list of phandle and IOMMU specifier pairs.
-
-* Nodes
-
-- ports:
- Usage: required
- Definition: As described in video-interfaces.txt in same directory.
- Properties:
- - reg:
- Usage: required
- Value type: <u32>
- Definition: Selects CSI2 PHY interface - PHY0, PHY1
- or PHY2 (8996 only)
- Endpoint node properties:
- - clock-lanes:
- Usage: required
- Value type: <u32>
- Definition: The physical clock lane index. On 8916
- the value must always be <1> as the physical
- clock lane is lane 1. On 8996 the value must
- always be <7> as the hardware supports D-PHY
- and C-PHY, indexes are in a common set and
- D-PHY physical clock lane is labeled as 7.
- - data-lanes:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: An array of physical data lanes indexes.
- Position of an entry determines the logical
- lane number, while the value of an entry
- indicates physical lane index. Lane swapping
- is supported. Physical lane indexes for
- 8916: 0, 2, 3, 4; for 8996: 0, 1, 2, 3.
-
-* An Example
-
- camss: camss@1b00000 {
- compatible = "qcom,msm8916-camss";
- reg = <0x1b0ac00 0x200>,
- <0x1b00030 0x4>,
- <0x1b0b000 0x200>,
- <0x1b00038 0x4>,
- <0x1b08000 0x100>,
- <0x1b08400 0x100>,
- <0x1b0a000 0x500>,
- <0x1b00020 0x10>,
- <0x1b10000 0x1000>;
- reg-names = "csiphy0",
- "csiphy0_clk_mux",
- "csiphy1",
- "csiphy1_clk_mux",
- "csid0",
- "csid1",
- "ispif",
- "csi_clk_mux",
- "vfe0";
- interrupts = <GIC_SPI 78 0>,
- <GIC_SPI 79 0>,
- <GIC_SPI 51 0>,
- <GIC_SPI 52 0>,
- <GIC_SPI 55 0>,
- <GIC_SPI 57 0>;
- interrupt-names = "csiphy0",
- "csiphy1",
- "csid0",
- "csid1",
- "ispif",
- "vfe0";
- power-domains = <&gcc VFE_GDSC>;
- clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
- <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
- <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
- <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
- <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
- <&gcc GCC_CAMSS_CSI0_CLK>,
- <&gcc GCC_CAMSS_CSI0PHY_CLK>,
- <&gcc GCC_CAMSS_CSI0PIX_CLK>,
- <&gcc GCC_CAMSS_CSI0RDI_CLK>,
- <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
- <&gcc GCC_CAMSS_CSI1_CLK>,
- <&gcc GCC_CAMSS_CSI1PHY_CLK>,
- <&gcc GCC_CAMSS_CSI1PIX_CLK>,
- <&gcc GCC_CAMSS_CSI1RDI_CLK>,
- <&gcc GCC_CAMSS_AHB_CLK>,
- <&gcc GCC_CAMSS_VFE0_CLK>,
- <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
- <&gcc GCC_CAMSS_VFE_AHB_CLK>,
- <&gcc GCC_CAMSS_VFE_AXI_CLK>;
- clock-names = "top_ahb",
- "ispif_ahb",
- "csiphy0_timer",
- "csiphy1_timer",
- "csi0_ahb",
- "csi0",
- "csi0_phy",
- "csi0_pix",
- "csi0_rdi",
- "csi1_ahb",
- "csi1",
- "csi1_phy",
- "csi1_pix",
- "csi1_rdi",
- "ahb",
- "vfe0",
- "csi_vfe0",
- "vfe_ahb",
- "vfe_axi";
- vdda-supply = <&pm8916_l2>;
- iommus = <&apps_iommu 3>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- csiphy0_ep: endpoint {
- clock-lanes = <1>;
- data-lanes = <0 2>;
- remote-endpoint = <&ov5645_ep>;
- };
- };
- };
- };
diff --git a/dts/Bindings/media/qcom,msm8916-camss.yaml b/dts/Bindings/media/qcom,msm8916-camss.yaml
new file mode 100644
index 0000000000..304908072d
--- /dev/null
+++ b/dts/Bindings/media/qcom,msm8916-camss.yaml
@@ -0,0 +1,256 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm CAMSS ISP
+
+maintainers:
+ - Robert Foss <robert.foss@linaro.org>
+ - Todor Tomov <todor.too@gmail.com>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
+
+properties:
+ compatible:
+ const: qcom,msm8916-camss
+
+ clocks:
+ minItems: 19
+ maxItems: 19
+
+ clock-names:
+ items:
+ - const: top_ahb
+ - const: ispif_ahb
+ - const: csiphy0_timer
+ - const: csiphy1_timer
+ - const: csi0_ahb
+ - const: csi0
+ - const: csi0_phy
+ - const: csi0_pix
+ - const: csi0_rdi
+ - const: csi1_ahb
+ - const: csi1
+ - const: csi1_phy
+ - const: csi1_pix
+ - const: csi1_rdi
+ - const: ahb
+ - const: vfe0
+ - const: csi_vfe0
+ - const: vfe_ahb
+ - const: vfe_axi
+
+ interrupts:
+ minItems: 6
+ maxItems: 6
+
+ interrupt-names:
+ items:
+ - const: csiphy0
+ - const: csiphy1
+ - const: csid0
+ - const: csid1
+ - const: ispif
+ - const: vfe0
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: VFE GDSC - Video Front End, Global Distributed Switch Controller.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 1
+
+ data-lanes:
+ description:
+ An array of physical data lanes indexes.
+ Position of an entry determines the logical
+ lane number, while the value of an entry
+ indicates physical lane index. Lane swapping
+ is supported. Physical lane indexes;
+ 0, 2, 3, 4.
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ minItems: 9
+ maxItems: 9
+
+ reg-names:
+ items:
+ - const: csiphy0
+ - const: csiphy0_clk_mux
+ - const: csiphy1
+ - const: csiphy1_clk_mux
+ - const: csid0
+ - const: csid1
+ - const: ispif
+ - const: csi_clk_mux
+ - const: vfe0
+
+ vdda-supply:
+ description:
+ Definition of the regulator used as analog power supply.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interrupt-names
+ - interrupts
+ - iommus
+ - power-domains
+ - reg
+ - reg-names
+ - vdda-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-msm8916.h>
+
+ camss: camss@1b00000 {
+ compatible = "qcom,msm8916-camss";
+
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>;
+
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe_ahb",
+ "vfe_axi";
+
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csid0",
+ "csid1",
+ "ispif",
+ "vfe0";
+
+ iommus = <&apps_iommu 3>;
+
+ power-domains = <&gcc VFE_GDSC>;
+
+ reg = <0x01b0ac00 0x200>,
+ <0x01b00030 0x4>,
+ <0x01b0b000 0x200>,
+ <0x01b00038 0x4>,
+ <0x01b08000 0x100>,
+ <0x01b08400 0x100>,
+ <0x01b0a000 0x500>,
+ <0x01b00020 0x10>,
+ <0x01b10000 0x1000>;
+
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csid0",
+ "csid1",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0";
+
+ vdda-supply = <&reg_2v8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ };
diff --git a/dts/Bindings/media/qcom,msm8996-camss.yaml b/dts/Bindings/media/qcom,msm8996-camss.yaml
new file mode 100644
index 0000000000..38be41e932
--- /dev/null
+++ b/dts/Bindings/media/qcom,msm8996-camss.yaml
@@ -0,0 +1,387 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm CAMSS ISP
+
+maintainers:
+ - Robert Foss <robert.foss@linaro.org>
+ - Todor Tomov <todor.too@gmail.com>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
+
+properties:
+ compatible:
+ const: qcom,msm8996-camss
+
+ clocks:
+ minItems: 36
+ maxItems: 36
+
+ clock-names:
+ items:
+ - const: top_ahb
+ - const: ispif_ahb
+ - const: csiphy0_timer
+ - const: csiphy1_timer
+ - const: csiphy2_timer
+ - const: csi0_ahb
+ - const: csi0
+ - const: csi0_phy
+ - const: csi0_pix
+ - const: csi0_rdi
+ - const: csi1_ahb
+ - const: csi1
+ - const: csi1_phy
+ - const: csi1_pix
+ - const: csi1_rdi
+ - const: csi2_ahb
+ - const: csi2
+ - const: csi2_phy
+ - const: csi2_pix
+ - const: csi2_rdi
+ - const: csi3_ahb
+ - const: csi3
+ - const: csi3_phy
+ - const: csi3_pix
+ - const: csi3_rdi
+ - const: ahb
+ - const: vfe0
+ - const: csi_vfe0
+ - const: vfe0_ahb
+ - const: vfe0_stream
+ - const: vfe1
+ - const: csi_vfe1
+ - const: vfe1_ahb
+ - const: vfe1_stream
+ - const: vfe_ahb
+ - const: vfe_axi
+
+ interrupts:
+ minItems: 10
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid3
+ - const: ispif
+ - const: vfe0
+ - const: vfe1
+
+ iommus:
+ maxItems: 4
+
+ power-domains:
+ items:
+ - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
+ - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ description:
+ An array of physical data lanes indexes.
+ Position of an entry determines the logical
+ lane number, while the value of an entry
+ indicates physical lane index. Lane swapping
+ is supported. Physical lane indexes are;
+ 0, 1, 2, 3
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ minItems: 14
+ maxItems: 14
+
+ reg-names:
+ items:
+ - const: csiphy0
+ - const: csiphy0_clk_mux
+ - const: csiphy1
+ - const: csiphy1_clk_mux
+ - const: csiphy2
+ - const: csiphy2_clk_mux
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid3
+ - const: ispif
+ - const: csi_clk_mux
+ - const: vfe0
+ - const: vfe1
+
+ vdda-supply:
+ description:
+ Definition of the regulator used as analog power supply.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interrupt-names
+ - interrupts
+ - iommus
+ - power-domains
+ - reg
+ - reg-names
+ - vdda-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+ #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+
+ camss: camss@a00000 {
+ compatible = "qcom,msm8996-camss";
+
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_ISPIF_AHB_CLK>,
+ <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI0_AHB_CLK>,
+ <&mmcc CAMSS_CSI0_CLK>,
+ <&mmcc CAMSS_CSI0PHY_CLK>,
+ <&mmcc CAMSS_CSI0PIX_CLK>,
+ <&mmcc CAMSS_CSI0RDI_CLK>,
+ <&mmcc CAMSS_CSI1_AHB_CLK>,
+ <&mmcc CAMSS_CSI1_CLK>,
+ <&mmcc CAMSS_CSI1PHY_CLK>,
+ <&mmcc CAMSS_CSI1PIX_CLK>,
+ <&mmcc CAMSS_CSI1RDI_CLK>,
+ <&mmcc CAMSS_CSI2_AHB_CLK>,
+ <&mmcc CAMSS_CSI2_CLK>,
+ <&mmcc CAMSS_CSI2PHY_CLK>,
+ <&mmcc CAMSS_CSI2PIX_CLK>,
+ <&mmcc CAMSS_CSI2RDI_CLK>,
+ <&mmcc CAMSS_CSI3_AHB_CLK>,
+ <&mmcc CAMSS_CSI3_CLK>,
+ <&mmcc CAMSS_CSI3PHY_CLK>,
+ <&mmcc CAMSS_CSI3PIX_CLK>,
+ <&mmcc CAMSS_CSI3RDI_CLK>,
+ <&mmcc CAMSS_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_CLK>,
+ <&mmcc CAMSS_CSI_VFE0_CLK>,
+ <&mmcc CAMSS_VFE0_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_STREAM_CLK>,
+ <&mmcc CAMSS_VFE1_CLK>,
+ <&mmcc CAMSS_CSI_VFE1_CLK>,
+ <&mmcc CAMSS_VFE1_AHB_CLK>,
+ <&mmcc CAMSS_VFE1_STREAM_CLK>,
+ <&mmcc CAMSS_VFE_AHB_CLK>,
+ <&mmcc CAMSS_VFE_AXI_CLK>;
+
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csiphy2_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "csi2_ahb",
+ "csi2",
+ "csi2_phy",
+ "csi2_pix",
+ "csi2_rdi",
+ "csi3_ahb",
+ "csi3",
+ "csi3_phy",
+ "csi3_pix",
+ "csi3_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe0_ahb",
+ "vfe0_stream",
+ "vfe1",
+ "csi_vfe1",
+ "vfe1_ahb",
+ "vfe1_stream",
+ "vfe_ahb",
+ "vfe_axi";
+
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "ispif",
+ "vfe0",
+ "vfe1";
+
+ iommus = <&vfe_smmu 0>,
+ <&vfe_smmu 1>,
+ <&vfe_smmu 2>,
+ <&vfe_smmu 3>;
+
+ power-domains = <&mmcc VFE0_GDSC>,
+ <&mmcc VFE1_GDSC>;
+
+ reg = <0x00a34000 0x1000>,
+ <0x00a00030 0x4>,
+ <0x00a35000 0x1000>,
+ <0x00a00038 0x4>,
+ <0x00a36000 0x1000>,
+ <0x00a00040 0x4>,
+ <0x00a30000 0x100>,
+ <0x00a30400 0x100>,
+ <0x00a30800 0x100>,
+ <0x00a30c00 0x100>,
+ <0x00a31000 0x500>,
+ <0x00a00020 0x10>,
+ <0x00a10000 0x1000>,
+ <0x00a14000 0x1000>;
+
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csiphy2",
+ "csiphy2_clk_mux",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0",
+ "vfe1";
+
+ vdda-supply = <&reg_2v8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
diff --git a/dts/Bindings/media/qcom,sdm660-camss.yaml b/dts/Bindings/media/qcom,sdm660-camss.yaml
new file mode 100644
index 0000000000..841a1aafdd
--- /dev/null
+++ b/dts/Bindings/media/qcom,sdm660-camss.yaml
@@ -0,0 +1,398 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm CAMSS ISP
+
+maintainers:
+ - Robert Foss <robert.foss@linaro.org>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
+
+properties:
+ compatible:
+ const: qcom,sdm660-camss
+
+ clocks:
+ minItems: 42
+ maxItems: 42
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: cphy_csid0
+ - const: cphy_csid1
+ - const: cphy_csid2
+ - const: cphy_csid3
+ - const: csi0_ahb
+ - const: csi0
+ - const: csi0_phy
+ - const: csi0_pix
+ - const: csi0_rdi
+ - const: csi1_ahb
+ - const: csi1
+ - const: csi1_phy
+ - const: csi1_pix
+ - const: csi1_rdi
+ - const: csi2_ahb
+ - const: csi2
+ - const: csi2_phy
+ - const: csi2_pix
+ - const: csi2_rdi
+ - const: csi3_ahb
+ - const: csi3
+ - const: csi3_phy
+ - const: csi3_pix
+ - const: csi3_rdi
+ - const: csiphy0_timer
+ - const: csiphy1_timer
+ - const: csiphy2_timer
+ - const: csiphy_ahb2crif
+ - const: csi_vfe0
+ - const: csi_vfe1
+ - const: ispif_ahb
+ - const: throttle_axi
+ - const: top_ahb
+ - const: vfe0_ahb
+ - const: vfe0
+ - const: vfe0_stream
+ - const: vfe1_ahb
+ - const: vfe1
+ - const: vfe1_stream
+ - const: vfe_ahb
+ - const: vfe_axi
+
+ interrupts:
+ minItems: 10
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid3
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: ispif
+ - const: vfe0
+ - const: vfe1
+
+ iommus:
+ maxItems: 4
+
+ power-domains:
+ items:
+ - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
+ - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ minItems: 14
+ maxItems: 14
+
+ reg-names:
+ items:
+ - const: csi_clk_mux
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid3
+ - const: csiphy0
+ - const: csiphy0_clk_mux
+ - const: csiphy1
+ - const: csiphy1_clk_mux
+ - const: csiphy2
+ - const: csiphy2_clk_mux
+ - const: ispif
+ - const: vfe0
+ - const: vfe1
+
+ vdda-supply:
+ description:
+ Definition of the regulator used as analog power supply.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interrupt-names
+ - interrupts
+ - iommus
+ - power-domains
+ - reg
+ - reg-names
+ - vdda-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm660.h>
+ #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+
+ camss: camss@ca00000 {
+ compatible = "qcom,sdm660-camss";
+
+ clocks = <&mmcc CAMSS_AHB_CLK>,
+ <&mmcc CAMSS_CPHY_CSID0_CLK>,
+ <&mmcc CAMSS_CPHY_CSID1_CLK>,
+ <&mmcc CAMSS_CPHY_CSID2_CLK>,
+ <&mmcc CAMSS_CPHY_CSID3_CLK>,
+ <&mmcc CAMSS_CSI0_AHB_CLK>,
+ <&mmcc CAMSS_CSI0_CLK>,
+ <&mmcc CAMSS_CPHY_CSID0_CLK>,
+ <&mmcc CAMSS_CSI0PIX_CLK>,
+ <&mmcc CAMSS_CSI0RDI_CLK>,
+ <&mmcc CAMSS_CSI1_AHB_CLK>,
+ <&mmcc CAMSS_CSI1_CLK>,
+ <&mmcc CAMSS_CPHY_CSID1_CLK>,
+ <&mmcc CAMSS_CSI1PIX_CLK>,
+ <&mmcc CAMSS_CSI1RDI_CLK>,
+ <&mmcc CAMSS_CSI2_AHB_CLK>,
+ <&mmcc CAMSS_CSI2_CLK>,
+ <&mmcc CAMSS_CPHY_CSID2_CLK>,
+ <&mmcc CAMSS_CSI2PIX_CLK>,
+ <&mmcc CAMSS_CSI2RDI_CLK>,
+ <&mmcc CAMSS_CSI3_AHB_CLK>,
+ <&mmcc CAMSS_CSI3_CLK>,
+ <&mmcc CAMSS_CPHY_CSID3_CLK>,
+ <&mmcc CAMSS_CSI3PIX_CLK>,
+ <&mmcc CAMSS_CSI3RDI_CLK>,
+ <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
+ <&mmcc CSIPHY_AHB2CRIF_CLK>,
+ <&mmcc CAMSS_CSI_VFE0_CLK>,
+ <&mmcc CAMSS_CSI_VFE1_CLK>,
+ <&mmcc CAMSS_ISPIF_AHB_CLK>,
+ <&mmcc THROTTLE_CAMSS_AXI_CLK>,
+ <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_CLK>,
+ <&mmcc CAMSS_VFE0_STREAM_CLK>,
+ <&mmcc CAMSS_VFE1_AHB_CLK>,
+ <&mmcc CAMSS_VFE1_CLK>,
+ <&mmcc CAMSS_VFE1_STREAM_CLK>,
+ <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
+ <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
+
+ clock-names = "ahb",
+ "cphy_csid0",
+ "cphy_csid1",
+ "cphy_csid2",
+ "cphy_csid3",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "csi2_ahb",
+ "csi2",
+ "csi2_phy",
+ "csi2_pix",
+ "csi2_rdi",
+ "csi3_ahb",
+ "csi3",
+ "csi3_phy",
+ "csi3_pix",
+ "csi3_rdi",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csiphy2_timer",
+ "csiphy_ahb2crif",
+ "csi_vfe0",
+ "csi_vfe1",
+ "ispif_ahb",
+ "throttle_axi",
+ "top_ahb",
+ "vfe0_ahb",
+ "vfe0",
+ "vfe0_stream",
+ "vfe1_ahb",
+ "vfe1",
+ "vfe1_stream",
+ "vfe_ahb",
+ "vfe_axi";
+
+ interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "ispif",
+ "vfe0",
+ "vfe1";
+
+ iommus = <&mmss_smmu 0xc00>,
+ <&mmss_smmu 0xc01>,
+ <&mmss_smmu 0xc02>,
+ <&mmss_smmu 0xc03>;
+
+ power-domains = <&mmcc CAMSS_VFE0_GDSC>,
+ <&mmcc CAMSS_VFE1_GDSC>;
+
+ reg = <0x0ca00020 0x10>,
+ <0x0ca30000 0x100>,
+ <0x0ca30400 0x100>,
+ <0x0ca30800 0x100>,
+ <0x0ca30c00 0x100>,
+ <0x0c824000 0x1000>,
+ <0x0ca00120 0x4>,
+ <0x0c825000 0x1000>,
+ <0x0ca00124 0x4>,
+ <0x0c826000 0x1000>,
+ <0x0ca00128 0x4>,
+ <0x0ca31000 0x500>,
+ <0x0ca10000 0x1000>,
+ <0x0ca14000 0x1000>;
+
+ reg-names = "csi_clk_mux",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csiphy2",
+ "csiphy2_clk_mux",
+ "ispif",
+ "vfe0",
+ "vfe1";
+
+ vdda-supply = <&reg_2v8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
diff --git a/dts/Bindings/media/qcom,sdm845-camss.yaml b/dts/Bindings/media/qcom,sdm845-camss.yaml
new file mode 100644
index 0000000000..9ca5dfa7f2
--- /dev/null
+++ b/dts/Bindings/media/qcom,sdm845-camss.yaml
@@ -0,0 +1,371 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm CAMSS ISP
+
+maintainers:
+ - Robert Foss <robert.foss@linaro.org>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
+
+properties:
+ compatible:
+ const: qcom,sdm845-camss
+
+ clocks:
+ minItems: 36
+ maxItems: 36
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: cphy_rx_src
+ - const: csi0
+ - const: csi0_src
+ - const: csi1
+ - const: csi1_src
+ - const: csi2
+ - const: csi2_src
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy0_timer_src
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy1_timer_src
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy2_timer_src
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy3_timer_src
+ - const: gcc_camera_ahb
+ - const: gcc_camera_axi
+ - const: slow_ahb_src
+ - const: soc_ahb
+ - const: vfe0_axi
+ - const: vfe0
+ - const: vfe0_cphy_rx
+ - const: vfe0_src
+ - const: vfe1_axi
+ - const: vfe1
+ - const: vfe1_cphy_rx
+ - const: vfe1_src
+ - const: vfe_lite
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_src
+
+ interrupts:
+ minItems: 10
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+
+ iommus:
+ maxItems: 4
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ items:
+ - const: 7
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ minItems: 10
+ maxItems: 10
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+
+ vdda-supply:
+ description:
+ Definition of the regulator used as analog power supply.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interrupt-names
+ - interrupts
+ - iommus
+ - power-domains
+ - reg
+ - reg-names
+ - vdda-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,camcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: camss@a00000 {
+ compatible = "qcom,sdm845-camss";
+
+ clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY0_CLK>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY1_CLK>,
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY2_CLK>,
+ <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY3_CLK>,
+ <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_AXI_CLK>,
+ <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_SOC_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
+
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cphy_rx_src",
+ "csi0",
+ "csi0_src",
+ "csi1",
+ "csi1_src",
+ "csi2",
+ "csi2_src",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy0_timer_src",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy1_timer_src",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy2_timer_src",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy3_timer_src",
+ "gcc_camera_ahb",
+ "gcc_camera_axi",
+ "slow_ahb_src",
+ "soc_ahb",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe0_src",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe1_src",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_src";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "vfe1",
+ "vfe_lite";
+
+ iommus = <&apps_smmu 0x0808 0x0>,
+ <&apps_smmu 0x0810 0x8>,
+ <&apps_smmu 0x0c08 0x0>,
+ <&apps_smmu 0x0c10 0x8>;
+
+ power-domains = <&clock_camcc IFE_0_GDSC>,
+ <&clock_camcc IFE_1_GDSC>,
+ <&clock_camcc TITAN_TOP_GDSC>;
+
+ reg = <0 0xacb3000 0 0x1000>,
+ <0 0xacba000 0 0x1000>,
+ <0 0xacc8000 0 0x1000>,
+ <0 0xac65000 0 0x1000>,
+ <0 0xac66000 0 0x1000>,
+ <0 0xac67000 0 0x1000>,
+ <0 0xac68000 0 0x1000>,
+ <0 0xacaf000 0 0x4000>,
+ <0 0xacb6000 0 0x4000>,
+ <0 0xacc4000 0 0x4000>;
+
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "vfe1",
+ "vfe_lite";
+
+ vdda-supply = <&reg_2v8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/qcom,sm8250-venus.yaml b/dts/Bindings/media/qcom,sm8250-venus.yaml
new file mode 100644
index 0000000000..7b81bd7f23
--- /dev/null
+++ b/dts/Bindings/media/qcom,sm8250-venus.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Venus video encode and decode accelerators
+
+maintainers:
+ - Stanimir Varbanov <stanimir.varbanov@linaro.org>
+
+description: |
+ The Venus IP is a video encode and decode accelerator present
+ on Qualcomm platforms
+
+properties:
+ compatible:
+ const: qcom,sm8250-venus
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ minItems: 2
+ maxItems: 3
+
+ power-domain-names:
+ minItems: 2
+ maxItems: 3
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mx
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+
+ iommus:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: bus
+ - const: core
+
+ video-decoder:
+ type: object
+
+ properties:
+ compatible:
+ const: venus-decoder
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+ video-encoder:
+ type: object
+
+ properties:
+ compatible:
+ const: venus-encoder
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+ video-firmware:
+ type: object
+
+ description: |
+ Firmware subnode is needed when the platform does not
+ have TrustZone.
+
+ properties:
+ iommus:
+ maxItems: 1
+
+ required:
+ - iommus
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - memory-region
+ - resets
+ - reset-names
+ - video-decoder
+ - video-encoder
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,videocc-sm8250.h>
+ #include <dt-bindings/interconnect/qcom,sm8250.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8250.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ venus: video-codec@aa00000 {
+ compatible = "qcom,sm8250-venus";
+ reg = <0x0aa00000 0xff000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&videocc MVS0C_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd SM8250_MX>;
+ power-domain-names = "venus", "vcodec0", "mx";
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface", "core", "vcodec0_core";
+
+ interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
+ <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "cpu-cfg", "video-mem";
+
+ iommus = <&apps_smmu 0x2100 0x0400>;
+ memory-region = <&video_mem>;
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+ reset-names = "bus", "core";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+ };
diff --git a/dts/Bindings/media/rc.yaml b/dts/Bindings/media/rc.yaml
index 946441b4e1..af9e7e59e5 100644
--- a/dts/Bindings/media/rc.yaml
+++ b/dts/Bindings/media/rc.yaml
@@ -90,9 +90,12 @@ properties:
- rc-leadtek-y04g0051
- rc-lme2510
- rc-manli
+ - rc-mecool-kii-pro
+ - rc-mecool-kiii-pro
- rc-medion-x10
- rc-medion-x10-digitainer
- rc-medion-x10-or2x
+ - rc-minix-neo
- rc-msi-digivox-ii
- rc-msi-digivox-iii
- rc-msi-tvanywhere
@@ -145,11 +148,13 @@ properties:
- rc-videomate-s350
- rc-videomate-tv-pvr
- rc-videostrong-kii-pro
+ - rc-vega-s9x
- rc-wetek-hub
- rc-wetek-play2
- rc-winfast
- rc-winfast-usbii-deluxe
- rc-x96max
+ - rc-xbox-360
- rc-xbox-dvd
- rc-zx-irdec
diff --git a/dts/Bindings/media/renesas,drif.txt b/dts/Bindings/media/renesas,drif.txt
deleted file mode 100644
index 0d8974aa8b..0000000000
--- a/dts/Bindings/media/renesas,drif.txt
+++ /dev/null
@@ -1,177 +0,0 @@
-Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
-------------------------------------------------------------
-
-R-Car Gen3 DRIF is a SPI like receive only slave device. A general
-representation of DRIF interfacing with a master device is shown below.
-
-+---------------------+ +---------------------+
-| |-----SCK------->|CLK |
-| Master |-----SS-------->|SYNC DRIFn (slave) |
-| |-----SD0------->|D0 |
-| |-----SD1------->|D1 |
-+---------------------+ +---------------------+
-
-As per datasheet, each DRIF channel (drifn) is made up of two internal
-channels (drifn0 & drifn1). These two internal channels share the common
-CLK & SYNC. Each internal channel has its own dedicated resources like
-irq, dma channels, address space & clock. This internal split is not
-visible to the external master device.
-
-The device tree model represents each internal channel as a separate node.
-The internal channels sharing the CLK & SYNC are tied together by their
-phandles using a property called "renesas,bonding". For the rest of
-the documentation, unless explicitly stated, the word channel implies an
-internal channel.
-
-When both internal channels are enabled they need to be managed together
-as one (i.e.) they cannot operate alone as independent devices. Out of the
-two, one of them needs to act as a primary device that accepts common
-properties of both the internal channels. This channel is identified by a
-property called "renesas,primary-bond".
-
-To summarize,
- - When both the internal channels that are bonded together are enabled,
- the zeroth channel is selected as primary-bond. This channels accepts
- properties common to all the members of the bond.
- - When only one of the bonded channels need to be enabled, the property
- "renesas,bonding" or "renesas,primary-bond" will have no effect. That
- enabled channel can act alone as any other independent device.
-
-Required properties of an internal channel:
--------------------------------------------
-- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
- "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
- "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: offset and length of that channel.
-- interrupts: associated with that channel.
-- clocks: phandle and clock specifier of that channel.
-- clock-names: clock input name string: "fck".
-- dmas: phandles to the DMA channels.
-- dma-names: names of the DMA channel: "rx".
-- renesas,bonding: phandle to the other channel.
-
-Optional properties of an internal channel:
--------------------------------------------
-- power-domains: phandle to the respective power domain.
-
-Required properties of an internal channel when:
- - It is the only enabled channel of the bond (or)
- - If it acts as primary among enabled bonds
---------------------------------------------------------
-- pinctrl-0: pin control group to be used for this channel.
-- pinctrl-names: must be "default".
-- renesas,primary-bond: empty property indicating the channel acts as primary
- among the bonded channels.
-- port: child port node corresponding to the data input, in accordance with
- the video interface bindings defined in
- Documentation/devicetree/bindings/media/video-interfaces.txt. The port
- node must contain at least one endpoint.
-
-Optional endpoint property:
----------------------------
-- sync-active: Indicates sync signal polarity, 0/1 for low/high respectively.
- This property maps to SYNCAC bit in the hardware manual. The
- default is 1 (active high).
-
-Example:
---------
-
-(1) Both internal channels enabled:
------------------------------------
-
-When interfacing with a third party tuner device with two data pins as shown
-below.
-
-+---------------------+ +---------------------+
-| |-----SCK------->|CLK |
-| Master |-----SS-------->|SYNC DRIFn (slave) |
-| |-----SD0------->|D0 |
-| |-----SD1------->|D1 |
-+---------------------+ +---------------------+
-
- drif00: rif@e6f40000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f40000 0 0x64>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>;
- clock-names = "fck";
- dmas = <&dmac1 0x20>, <&dmac2 0x20>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- renesas,bonding = <&drif01>;
- renesas,primary-bond;
- pinctrl-0 = <&drif0_pins>;
- pinctrl-names = "default";
- port {
- drif0_ep: endpoint {
- remote-endpoint = <&tuner_ep>;
- };
- };
- };
-
- drif01: rif@e6f50000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f50000 0 0x64>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>;
- clock-names = "fck";
- dmas = <&dmac1 0x22>, <&dmac2 0x22>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- renesas,bonding = <&drif00>;
- };
-
-
-(2) Internal channel 1 alone is enabled:
-----------------------------------------
-
-When interfacing with a third party tuner device with one data pin as shown
-below.
-
-+---------------------+ +---------------------+
-| |-----SCK------->|CLK |
-| Master |-----SS-------->|SYNC DRIFn (slave) |
-| | |D0 (unused) |
-| |-----SD-------->|D1 |
-+---------------------+ +---------------------+
-
- drif00: rif@e6f40000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f40000 0 0x64>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>;
- clock-names = "fck";
- dmas = <&dmac1 0x20>, <&dmac2 0x20>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- renesas,bonding = <&drif01>;
- };
-
- drif01: rif@e6f50000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f50000 0 0x64>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>;
- clock-names = "fck";
- dmas = <&dmac1 0x22>, <&dmac2 0x22>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- renesas,bonding = <&drif00>;
- pinctrl-0 = <&drif0_pins>;
- pinctrl-names = "default";
- port {
- drif0_ep: endpoint {
- remote-endpoint = <&tuner_ep>;
- sync-active = <0>;
- };
- };
- };
diff --git a/dts/Bindings/media/renesas,drif.yaml b/dts/Bindings/media/renesas,drif.yaml
new file mode 100644
index 0000000000..f1bdaeab40
--- /dev/null
+++ b/dts/Bindings/media/renesas,drif.yaml
@@ -0,0 +1,279 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/renesas,drif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
+
+maintainers:
+ - Ramesh Shanmugasundaram <rashanmu@gmail.com>
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
+
+description: |
+ R-Car Gen3 DRIF is a SPI like receive only slave device. A general
+ representation of DRIF interfacing with a master device is shown below.
+
+ +---------------------+ +---------------------+
+ | |-----SCK------->|CLK |
+ | Master |-----SS-------->|SYNC DRIFn (slave) |
+ | |-----SD0------->|D0 |
+ | |-----SD1------->|D1 |
+ +---------------------+ +---------------------+
+
+ As per datasheet, each DRIF channel (drifn) is made up of two internal
+ channels (drifn0 & drifn1). These two internal channels share the common
+ CLK & SYNC. Each internal channel has its own dedicated resources like
+ irq, dma channels, address space & clock. This internal split is not
+ visible to the external master device.
+
+ The device tree model represents each internal channel as a separate node.
+ The internal channels sharing the CLK & SYNC are tied together by their
+ phandles using a property called "renesas,bonding". For the rest of
+ the documentation, unless explicitly stated, the word channel implies an
+ internal channel.
+
+ When both internal channels are enabled they need to be managed together
+ as one (i.e.) they cannot operate alone as independent devices. Out of the
+ two, one of them needs to act as a primary device that accepts common
+ properties of both the internal channels. This channel is identified by a
+ property called "renesas,primary-bond".
+
+ To summarize,
+ * When both the internal channels that are bonded together are enabled,
+ the zeroth channel is selected as primary-bond. This channels accepts
+ properties common to all the members of the bond.
+ * When only one of the bonded channels need to be enabled, the property
+ "renesas,bonding" or "renesas,primary-bond" will have no effect. That
+ enabled channel can act alone as any other independent device.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a7795-drif # R-Car H3
+ - renesas,r8a7796-drif # R-Car M3-W
+ - renesas,r8a77965-drif # R-Car M3-N
+ - renesas,r8a77990-drif # R-Car E3
+ - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+ items:
+ - const: fck
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ minItems: 1
+ maxItems: 2
+
+ dma-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: rx
+ - const: rx
+
+ renesas,bonding:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle to the other internal channel of DRIF
+
+ power-domains:
+ maxItems: 1
+
+ renesas,primary-bond:
+ type: boolean
+ description:
+ Indicates that the channel acts as primary among the bonded channels.
+
+ port:
+ type: object
+ description:
+ Child port node corresponding to the data input, in accordance with the
+ video interface bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ The port node must contain at least one endpoint.
+
+ properties:
+ endpoint:
+ type: object
+
+ properties:
+ remote-endpoint:
+ description:
+ A phandle to the remote tuner endpoint subnode in remote node
+ port.
+
+ sync-active:
+ enum: [0, 1]
+ description:
+ Indicates sync signal polarity, 0/1 for low/high respectively.
+ This property maps to SYNCAC bit in the hardware manual. The
+ default is 1 (active high).
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - dmas
+ - dma-names
+ - renesas,bonding
+ - power-domains
+
+allOf:
+ - if:
+ required:
+ - renesas,primary-bond
+ then:
+ required:
+ - pinctrl-0
+ - pinctrl-names
+ - port
+
+ - if:
+ required:
+ - port
+ then:
+ required:
+ - pinctrl-0
+ - pinctrl-names
+ else:
+ properties:
+ pinctrl-0: false
+ pinctrl-names: false
+
+additionalProperties: false
+
+examples:
+ # Example with both internal channels enabled.
+ #
+ # When interfacing with a third party tuner device with two data pins as shown
+ # below.
+ #
+ # +---------------------+ +---------------------+
+ # | |-----SCK------->|CLK |
+ # | Master |-----SS-------->|SYNC DRIFn (slave) |
+ # | |-----SD0------->|D0 |
+ # | |-----SD1------->|D1 |
+ # +---------------------+ +---------------------+
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ renesas,bonding = <&drif01>;
+ resets = <&cpg 515>;
+ renesas,primary-bond;
+ pinctrl-0 = <&drif0_pins>;
+ pinctrl-names = "default";
+ port {
+ drif0_ep: endpoint {
+ remote-endpoint = <&tuner_ep>;
+ };
+ };
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ renesas,bonding = <&drif00>;
+ resets = <&cpg 514>;
+ };
+ };
+
+ # Example with internal channel 1 alone enabled.
+ #
+ # When interfacing with a third party tuner device with one data pin as shown
+ # below.
+ #
+ # +---------------------+ +---------------------+
+ # | |-----SCK------->|CLK |
+ # | Master |-----SS-------->|SYNC DRIFn (slave) |
+ # | | |D0 (unused) |
+ # | |-----SD-------->|D1 |
+ # +---------------------+ +---------------------+
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ drif10: rif@e6f60000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f60000 0 0x64>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 513>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 513>;
+ renesas,bonding = <&drif11>;
+ status = "disabled";
+ };
+
+ drif11: rif@e6f70000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f70000 0 0x64>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 512>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 512>;
+ renesas,bonding = <&drif10>;
+ pinctrl-0 = <&drif1_pins>;
+ pinctrl-names = "default";
+ port {
+ drif1_ep: endpoint {
+ remote-endpoint = <&tuner_ep1>;
+ sync-active = <0>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/media/renesas,vin.yaml b/dts/Bindings/media/renesas,vin.yaml
index fe7c4cbfe4..dd1a5ce589 100644
--- a/dts/Bindings/media/renesas,vin.yaml
+++ b/dts/Bindings/media/renesas,vin.yaml
@@ -193,23 +193,35 @@ required:
- interrupts
- clocks
- power-domains
- - resets
-
-if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,vin-r8a7778
- - renesas,vin-r8a7779
- - renesas,rcar-gen2-vin
-then:
- required:
- - port
-else:
- required:
- - renesas,id
- - ports
+
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,vin-r8a7778
+ - renesas,vin-r8a7779
+ then:
+ required:
+ - resets
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,vin-r8a7778
+ - renesas,vin-r8a7779
+ - renesas,rcar-gen2-vin
+ then:
+ required:
+ - port
+ else:
+ required:
+ - renesas,id
+ - ports
additionalProperties: false
diff --git a/dts/Bindings/media/video-interfaces.yaml b/dts/Bindings/media/video-interfaces.yaml
index 0a7a73fd59..4391dce2ca 100644
--- a/dts/Bindings/media/video-interfaces.yaml
+++ b/dts/Bindings/media/video-interfaces.yaml
@@ -215,130 +215,3 @@ properties:
CCP2, for instance.
additionalProperties: true
-
-examples:
- # The example snippet below describes two data pipelines. ov772x and imx074
- # are camera sensors with a parallel and serial (MIPI CSI-2) video bus
- # respectively. Both sensors are on the I2C control bus corresponding to the
- # i2c0 controller node. ov772x sensor is linked directly to the ceu0 video
- # host interface. imx074 is linked to ceu0 through the MIPI CSI-2 receiver
- # (csi2). ceu0 has a (single) DMA engine writing captured data to memory.
- # ceu0 node has a single 'port' node which may indicate that at any time
- # only one of the following data pipelines can be active:
- # ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
- - |
- ceu@fe910000 {
- compatible = "renesas,sh-mobile-ceu";
- reg = <0xfe910000 0xa0>;
- interrupts = <0x880>;
-
- mclk: master_clock {
- compatible = "renesas,ceu-clock";
- #clock-cells = <1>;
- clock-frequency = <50000000>; /* Max clock frequency */
- clock-output-names = "mclk";
- };
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Parallel bus endpoint */
- ceu0_1: endpoint@1 {
- reg = <1>; /* Local endpoint # */
- remote-endpoint = <&ov772x_1_1>; /* Remote phandle */
- bus-width = <8>; /* Used data lines */
- data-shift = <2>; /* Lines 9:2 are used */
-
- /* If hsync-active/vsync-active are missing,
- embedded BT.656 sync is used */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- data-active = <1>; /* Active high */
- pclk-sample = <1>; /* Rising */
- };
-
- /* MIPI CSI-2 bus endpoint */
- ceu0_0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi2_2>;
- };
- };
- };
-
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- camera@21 {
- compatible = "ovti,ov772x";
- reg = <0x21>;
- vddio-supply = <&regulator1>;
- vddcore-supply = <&regulator2>;
-
- clock-frequency = <20000000>;
- clocks = <&mclk 0>;
- clock-names = "xclk";
-
- port {
- /* With 1 endpoint per port no need for addresses. */
- ov772x_1_1: endpoint {
- bus-width = <8>;
- remote-endpoint = <&ceu0_1>;
- hsync-active = <1>;
- vsync-active = <0>; /* Who came up with an
- inverter here ?... */
- data-active = <1>;
- pclk-sample = <1>;
- };
- };
- };
-
- camera@1a {
- compatible = "sony,imx074";
- reg = <0x1a>;
- vddio-supply = <&regulator1>;
- vddcore-supply = <&regulator2>;
-
- clock-frequency = <30000000>; /* Shared clock with ov772x_1 */
- clocks = <&mclk 0>;
- clock-names = "sysclk"; /* Assuming this is the
- name in the datasheet */
- port {
- imx074_1: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2>;
- remote-endpoint = <&csi2_1>;
- };
- };
- };
- };
-
- csi2: csi2@ffc90000 {
- compatible = "renesas,sh-mobile-csi2";
- reg = <0xffc90000 0x1000>;
- interrupts = <0x17a0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */
- reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S,
- PHY_M has port address 0,
- is unused. */
- csi2_1: endpoint {
- clock-lanes = <0>;
- data-lanes = <2 1>;
- remote-endpoint = <&imx074_1>;
- };
- };
- port@2 {
- reg = <2>; /* port 2: link to the CEU */
-
- csi2_2: endpoint {
- remote-endpoint = <&ceu0_0>;
- };
- };
- };
-
-...
diff --git a/dts/Bindings/media/video-mux.txt b/dts/Bindings/media/video-mux.txt
deleted file mode 100644
index 63b9dc913e..0000000000
--- a/dts/Bindings/media/video-mux.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-Video Multiplexer
-=================
-
-Video multiplexers allow to select between multiple input ports. Video received
-on the active input port is passed through to the output port. Muxes described
-by this binding are controlled by a multiplexer controller that is described by
-the bindings in Documentation/devicetree/bindings/mux/mux-controller.txt
-
-Required properties:
-- compatible : should be "video-mux"
-- mux-controls : mux controller node to use for operating the mux
-- #address-cells: should be <1>
-- #size-cells: should be <0>
-- port@*: at least three port nodes containing endpoints connecting to the
- source and sink devices according to of_graph bindings. The last port is
- the output port, all others are inputs.
-
-Optionally, #address-cells, #size-cells, and port nodes can be grouped under a
-ports node as described in Documentation/devicetree/bindings/graph.txt.
-
-Example:
-
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- };
-
- video-mux {
- compatible = "video-mux";
- mux-controls = <&mux>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mux_in0: endpoint {
- remote-endpoint = <&video_source0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- mux_in1: endpoint {
- remote-endpoint = <&video_source1_out>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- mux_out: endpoint {
- remote-endpoint = <&capture_interface_in>;
- };
- };
- };
-};
diff --git a/dts/Bindings/media/video-mux.yaml b/dts/Bindings/media/video-mux.yaml
new file mode 100644
index 0000000000..2f28a7dad9
--- /dev/null
+++ b/dts/Bindings/media/video-mux.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/video-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Video Multiplexer
+
+maintainers:
+ - Sakari Ailus <sakari.ailus@linux.intel.com>
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description:
+ Video multiplexers allow to select between multiple input ports. Video
+ received on the active input port is passed through to the output port. Muxes
+ described by this binding are controlled by a multiplexer controller.
+
+properties:
+ compatible:
+ const: video-mux
+
+ mux-controls:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ patternProperties:
+ '^port@':
+ $ref: /schemas/graph.yaml#/properties/port
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+patternProperties:
+ '^port@':
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ At least three port nodes containing endpoints connecting to the source
+ and sink devices according to of_graph bindings. The last port is the
+ output port, all others are inputs.
+
+required:
+ - compatible
+ - mux-controls
+
+oneOf:
+ - required:
+ - ports
+ - required:
+ - port@0
+ - port@1
+ - port@2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ video-mux {
+ compatible = "video-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mux_in0: endpoint {
+ remote-endpoint = <&video_source0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mux_in1: endpoint {
+ remote-endpoint = <&video_source1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mux_out: endpoint {
+ remote-endpoint = <&capture_interface_in>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/media/zx-irdec.txt b/dts/Bindings/media/zx-irdec.txt
deleted file mode 100644
index 295b9fab59..0000000000
--- a/dts/Bindings/media/zx-irdec.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-IR Decoder (IRDEC) on ZTE ZX family SoCs
-
-Required properties:
- - compatible: Should be "zte,zx296718-irdec".
- - reg: Physical base address and length of IRDEC registers.
- - interrupts: Interrupt number of IRDEC.
-
-Exmaples:
-
- irdec: ir-decoder@111000 {
- compatible = "zte,zx296718-irdec";
- reg = <0x111000 0x1000>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
index 09bde65e19..9163c3f12a 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -37,9 +37,10 @@ properties:
description:
phandle of the memory controller node
- core-supply:
+ power-domains:
+ maxItems: 1
description:
- Phandle of voltage regulator of the SoC "core" power domain.
+ Phandle of the SoC "core" power domain.
operating-points-v2:
description:
@@ -370,7 +371,7 @@ examples:
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
- core-supply = <&vdd_core>;
+ power-domains = <&domain>;
#interconnect-cells = <0>;
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt
index cc443fcf4b..d2250498c3 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt
+++ b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt
@@ -23,7 +23,7 @@ For each opp entry in 'operating-points-v2' table:
matches, the OPP gets enabled.
Optional properties:
-- core-supply: Phandle of voltage regulator of the SoC "core" power domain.
+- power-domains: Phandle of the SoC "core" power domain.
Child device nodes describe the memory settings for different configurations and clock rates.
@@ -48,7 +48,7 @@ Example:
interrupts = <0 78 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
nvidia,memory-controller = <&mc>;
- core-supply = <&core_vdd_reg>;
+ power-domains = <&domain>;
operating-points-v2 = <&opp_table>;
}
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
deleted file mode 100644
index 739b7c6f2e..0000000000
--- a/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-NVIDIA Tegra20 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra20-mc-gart"
-- reg : Should contain 2 register ranges: physical base address and length of
- the controller's registers and the GART aperture respectively.
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - mc: the module's clock input
-- interrupts : Should contain MC General interrupt.
-- #reset-cells : Should be 1. This cell represents memory client module ID.
- The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
- or in the TRM documentation.
-- #iommu-cells: Should be 0. This cell represents the number of cells in an
- IOMMU specifier needed to encode an address. GART supports only a single
- address space that is shared by all devices, therefore no additional
- information needed for the address encoding.
-- #interconnect-cells : Should be 1. This cell represents memory client.
- The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.
-
-Example:
- mc: memory-controller@7000f000 {
- compatible = "nvidia,tegra20-mc-gart";
- reg = <0x7000f000 0x400 /* controller registers */
- 0x58000000 0x02000000>; /* GART aperture */
- clocks = <&tegra_car TEGRA20_CLK_MC>;
- clock-names = "mc";
- interrupts = <GIC_SPI 77 0x04>;
- #reset-cells = <1>;
- #iommu-cells = <0>;
- #interconnect-cells = <1>;
- };
-
- video-codec@6001a000 {
- compatible = "nvidia,tegra20-vde";
- ...
- resets = <&mc TEGRA20_MC_RESET_VDE>;
- iommus = <&mc>;
- };
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-mc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.yaml
new file mode 100644
index 0000000000..55caf69053
--- /dev/null
+++ b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra20 SoC Memory Controller
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The Tegra20 Memory Controller merges request streams from various client
+ interfaces into request stream(s) for the various memory target devices,
+ and returns response data to the various clients. The Memory Controller
+ has a configurable arbitration algorithm to allow the user to fine-tune
+ performance among the various clients.
+
+ Tegra20 Memory Controller includes the GART (Graphics Address Relocation
+ Table) which allows Memory Controller to provide a linear view of a
+ fragmented memory pages.
+
+properties:
+ compatible:
+ const: nvidia,tegra20-mc-gart
+
+ reg:
+ items:
+ - description: controller registers
+ - description: GART registers
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: mc
+
+ interrupts:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+ "#iommu-cells":
+ const: 0
+
+ "#interconnect-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#reset-cells"
+ - "#iommu-cells"
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ memory-controller@7000f000 {
+ compatible = "nvidia,tegra20-mc-gart";
+ reg = <0x7000f000 0x400>, /* Controller registers */
+ <0x58000000 0x02000000>; /* GART aperture */
+ clocks = <&clock_controller 32>;
+ clock-names = "mc";
+
+ interrupts = <0 77 4>;
+
+ #iommu-cells = <0>;
+ #reset-cells = <1>;
+ #interconnect-cells = <1>;
+ };
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra210-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra210-emc.yaml
index 49ab09252e..bc8477e7ab 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra210-emc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra210-emc.yaml
@@ -34,7 +34,7 @@ properties:
- description: EMC general interrupt
memory-region:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description:
phandle to a reserved memory region describing the table of EMC
frequencies trained by the firmware
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
index 0a2e2c0d0f..fb6af14cb4 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
@@ -39,9 +39,10 @@ properties:
description:
Phandle of the Memory Controller node.
- core-supply:
+ power-domains:
+ maxItems: 1
description:
- Phandle of voltage regulator of the SoC "core" power domain.
+ Phandle of the SoC "core" power domain.
operating-points-v2:
description:
@@ -241,7 +242,7 @@ examples:
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
- core-supply = <&vdd_core>;
+ power-domains = <&domain>;
#interconnect-cells = <0>;
diff --git a/dts/Bindings/mfd/actions,atc260x.yaml b/dts/Bindings/mfd/actions,atc260x.yaml
new file mode 100644
index 0000000000..dd43a0c766
--- /dev/null
+++ b/dts/Bindings/mfd/actions,atc260x.yaml
@@ -0,0 +1,183 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/actions,atc260x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi ATC260x Power Management IC bindings
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+
+description: |
+ ATC260x series PMICs integrates Audio Codec, Power Management, RTC, IR
+ and GPIO controller blocks. Currently only the PM related functionalities
+ (i.e. regulators and system power-off/reboot) for the ATC2603C and ATC2609A
+ chip variants are supported.
+ ATC2603C includes 3 programmable DC-DC converters, 9 programmable LDO
+ regulators and 1 fixed LDO regulator.
+ ATC2609A includes 5 programmable DC-DC converters and 10 programmable LDO
+ regulators.
+
+allOf:
+ - $ref: ../input/input.yaml
+
+properties:
+ compatible:
+ enum:
+ - actions,atc2603c
+ - actions,atc2609a
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-time-sec:
+ description: |
+ Duration in seconds which the key should be kept pressed for device
+ to reset automatically. The hardware default is 8. Use 0 to disable
+ this functionality.
+ enum: [0, 6, 8, 10, 12]
+
+ regulators:
+ type: object
+ description: |
+ List of child nodes specifying the regulators, depending on chip variant:
+ * ATC2603C: dcdc[1-3], ldo[1-3,5-8,11,12], switchldo1
+ * ATC2609A: dcdc[0-4], ldo[0-9]
+
+ properties:
+ compatible:
+ enum:
+ - actions,atc2603c-regulator
+ - actions,atc2609a-regulator
+
+ switchldo1:
+ type: object
+ $ref: ../regulator/regulator.yaml
+
+ properties:
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-min-microvolt: true
+ regulator-max-microvolt: true
+ regulator-allow-bypass: true
+ regulator-active-discharge: true
+
+ additionalProperties: false
+
+ patternProperties:
+ "^(dcdc[0-4]|ldo[0-9]|ldo1[1-2]|switchldo1)-supply$":
+ description: ATC260x voltage regulators supplies
+
+ "^(dcdc[0-4]|ldo[0-9]|ldo1[1-2])$":
+ type: object
+ $ref: ../regulator/regulator.yaml
+
+ properties:
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-min-microvolt: true
+ regulator-max-microvolt: true
+ regulator-allow-bypass: true
+
+ additionalProperties: false
+
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: actions,atc2603c-regulator
+ then:
+ patternProperties:
+ "^(dcdc[0,4]|ldo[0,4,9])(-supply)?$": false
+
+ "^(ldo|dcdc)":
+ properties:
+ regulator-allow-bypass: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: actions,atc2609a-regulator
+ then:
+ patternProperties:
+ "^(ldo1[1-2]|switchldo1)(-supply)?$": false
+
+ "^(dcdc|ldo[3-9])":
+ properties:
+ regulator-allow-bypass: false
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@65 {
+ compatible = "actions,atc2603c";
+ reg = <0x65>;
+ interrupt-parent = <&sirq>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+
+ reset-time-sec = <6>;
+
+ regulators {
+ compatible = "actions,atc2603c-regulator";
+
+ dcdc1-supply = <&reg_5v0>;
+ dcdc3-supply = <&reg_5v0>;
+ ldo5-supply = <&reg_5v0>;
+ switchldo1-supply = <&vcc>;
+
+ vdd_cpu: dcdc1 {
+ regulator-name = "VDD_CPU";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ };
+
+ vcc: dcdc3 {
+ regulator-name = "VCC";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vcc_3v1: ldo5 {
+ regulator-name = "VCC_3V1";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ sd_vcc: switchldo1 {
+ regulator-name = "SD_VCC";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt
index d0a38ba8b9..936aa108ea 100644
--- a/dts/Bindings/mfd/aspeed-lpc.txt
+++ b/dts/Bindings/mfd/aspeed-lpc.txt
@@ -9,13 +9,7 @@ primary use case of the Aspeed LPC controller is as a slave on the bus
conditions it can also take the role of bus master.
The LPC controller is represented as a multi-function device to account for the
-mix of functionality it provides. The principle split is between the register
-layout at the start of the I/O space which is, to quote the Aspeed datasheet,
-"basically compatible with the [LPC registers from the] popular BMC controller
-H8S/2168[1]", and everything else, where everything else is an eclectic
-collection of functions with a esoteric register layout. "Everything else",
-here labeled the "host" portion of the controller, includes, but is not limited
-to:
+mix of functionality, which includes, but is not limited to:
* An IPMI Block Transfer[2] Controller
@@ -44,80 +38,36 @@ Required properties
===================
- compatible: One of:
- "aspeed,ast2400-lpc", "simple-mfd"
- "aspeed,ast2500-lpc", "simple-mfd"
- "aspeed,ast2600-lpc", "simple-mfd"
+ "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
- reg: contains the physical address and length values of the Aspeed
LPC memory region.
- #address-cells: <1>
- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Required LPC Child nodes
-========================
-
-BMC Node
---------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-bmc"
- "aspeed,ast2500-lpc-bmc"
- "aspeed,ast2600-lpc-bmc"
-
-- reg: contains the physical address and length values of the
- H8S/2168-compatible LPC controller memory region
-
-Host Node
----------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"
-
-- reg: contains the address and length values of the host-related
- register space for the Aspeed LPC controller
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the address and length of the host-related LPC memory
+- ranges: Maps 0 to the physical address and length of the LPC memory
region
Example:
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc";
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x0 0x80>;
- };
-
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
};
};
-BMC Node Children
-==================
-
-
-Host Node Children
-==================
LPC Host Interface Controller
-------------------
@@ -149,14 +99,12 @@ Optional properties:
Example:
-lpc-host@80 {
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
- };
+lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
};
LPC Host Controller
@@ -179,9 +127,9 @@ Required properties:
Example:
-lhc: lhc@20 {
+lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
+ reg = <0xa0 0x24 0xc8 0x8>;
};
LPC reset control
@@ -192,16 +140,18 @@ state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- - compatible: "aspeed,ast2600-lpc-reset" or
- "aspeed,ast2500-lpc-reset"
- "aspeed,ast2400-lpc-reset"
+ - compatible: One of:
+ "aspeed,ast2600-lpc-reset";
+ "aspeed,ast2500-lpc-reset";
+ "aspeed,ast2400-lpc-reset";
+
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
Example:
-lpc_reset: reset-controller@18 {
+lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
+ reg = <0x98 0x4>;
#reset-cells = <1>;
};
diff --git a/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml
new file mode 100644
index 0000000000..afc569bc15
--- /dev/null
+++ b/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description:
+ Broadcom BCM6318 SoC GPIO system controller which provides a register map
+ for controlling the GPIO and pins of the SoC.
+
+properties:
+ "#address-cells": true
+
+ "#size-cells": true
+
+ compatible:
+ items:
+ - const: brcm,bcm6318-gpio-sysctl
+ - const: syscon
+ - const: simple-mfd
+
+ ranges:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
+ description:
+ GPIO controller for the SoC GPIOs. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
+
+ "^pinctrl@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml"
+ description:
+ Pin controller for the SoC pins. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.
+
+required:
+ - "#address-cells"
+ - compatible
+ - ranges
+ - reg
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10000080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd";
+ reg = <0x10000080 0x80>;
+ ranges = <0 0x10000080 0x80>;
+
+ gpio@0 {
+ compatible = "brcm,bcm6318-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 50>;
+ #gpio-cells = <2>;
+ };
+
+ pinctrl: pinctrl@10 {
+ compatible = "brcm,bcm6318-pinctrl";
+ reg = <0x18 0x10>, <0x54 0x18>;
+
+ pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
+ function = "ephy0_spd_led";
+ pins = "gpio0";
+ };
+
+ pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
+ function = "ephy1_spd_led";
+ pins = "gpio1";
+ };
+
+ pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
+ function = "ephy2_spd_led";
+ pins = "gpio2";
+ };
+
+ pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
+ function = "ephy3_spd_led";
+ pins = "gpio3";
+ };
+
+ pinctrl_ephy0_act_led: ephy0_act_led-pins {
+ function = "ephy0_act_led";
+ pins = "gpio4";
+ };
+
+ pinctrl_ephy1_act_led: ephy1_act_led-pins {
+ function = "ephy1_act_led";
+ pins = "gpio5";
+ };
+
+ pinctrl_ephy2_act_led: ephy2_act_led-pins {
+ function = "ephy2_act_led";
+ pins = "gpio6";
+ };
+
+ pinctrl_ephy3_act_led: ephy3_act_led-pins {
+ function = "ephy3_act_led";
+ pins = "gpio7";
+ };
+
+ pinctrl_serial_led: serial_led-pins {
+ pinctrl_serial_led_data: serial_led_data-pins {
+ function = "serial_led_data";
+ pins = "gpio6";
+ };
+
+ pinctrl_serial_led_clk: serial_led_clk-pins {
+ function = "serial_led_clk";
+ pins = "gpio7";
+ };
+ };
+
+ pinctrl_inet_act_led: inet_act_led-pins {
+ function = "inet_act_led";
+ pins = "gpio8";
+ };
+
+ pinctrl_inet_fail_led: inet_fail_led-pins {
+ function = "inet_fail_led";
+ pins = "gpio9";
+ };
+
+ pinctrl_dsl_led: dsl_led-pins {
+ function = "dsl_led";
+ pins = "gpio10";
+ };
+
+ pinctrl_post_fail_led: post_fail_led-pins {
+ function = "post_fail_led";
+ pins = "gpio11";
+ };
+
+ pinctrl_wlan_wps_led: wlan_wps_led-pins {
+ function = "wlan_wps_led";
+ pins = "gpio12";
+ };
+
+ pinctrl_usb_pwron: usb_pwron-pins {
+ function = "usb_pwron";
+ pins = "gpio13";
+ };
+
+ pinctrl_usb_device_led: usb_device_led-pins {
+ function = "usb_device_led";
+ pins = "gpio13";
+ };
+
+ pinctrl_usb_active: usb_active-pins {
+ function = "usb_active";
+ pins = "gpio40";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
new file mode 100644
index 0000000000..c7771c86d7
--- /dev/null
+++ b/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
@@ -0,0 +1,194 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description:
+ Broadcom BCM63268 SoC GPIO system controller which provides a register map
+ for controlling the GPIO and pins of the SoC.
+
+properties:
+ "#address-cells": true
+
+ "#size-cells": true
+
+ compatible:
+ items:
+ - const: brcm,bcm63268-gpio-sysctl
+ - const: syscon
+ - const: simple-mfd
+
+ ranges:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
+ description:
+ GPIO controller for the SoC GPIOs. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
+
+ "^pinctrl@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
+ description:
+ Pin controller for the SoC pins. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
+
+required:
+ - "#address-cells"
+ - compatible
+ - ranges
+ - reg
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@100000c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
+ reg = <0x100000c0 0x80>;
+ ranges = <0 0x100000c0 0x80>;
+
+ gpio@0 {
+ compatible = "brcm,bcm63268-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 52>;
+ #gpio-cells = <2>;
+ };
+
+ pinctrl: pinctrl@10 {
+ compatible = "brcm,bcm63268-pinctrl";
+ reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
+
+ pinctrl_serial_led: serial_led-pins {
+ pinctrl_serial_led_clk: serial_led_clk-pins {
+ function = "serial_led_clk";
+ pins = "gpio0";
+ };
+
+ pinctrl_serial_led_data: serial_led_data-pins {
+ function = "serial_led_data";
+ pins = "gpio1";
+ };
+ };
+
+ pinctrl_hsspi_cs4: hsspi_cs4-pins {
+ function = "hsspi_cs4";
+ pins = "gpio16";
+ };
+
+ pinctrl_hsspi_cs5: hsspi_cs5-pins {
+ function = "hsspi_cs5";
+ pins = "gpio17";
+ };
+
+ pinctrl_hsspi_cs6: hsspi_cs6-pins {
+ function = "hsspi_cs6";
+ pins = "gpio8";
+ };
+
+ pinctrl_hsspi_cs7: hsspi_cs7-pins {
+ function = "hsspi_cs7";
+ pins = "gpio9";
+ };
+
+ pinctrl_adsl_spi: adsl_spi-pins {
+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
+ function = "adsl_spi_miso";
+ pins = "gpio18";
+ };
+
+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
+ function = "adsl_spi_mosi";
+ pins = "gpio19";
+ };
+ };
+
+ pinctrl_vreq_clk: vreq_clk-pins {
+ function = "vreq_clk";
+ pins = "gpio22";
+ };
+
+ pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
+ function = "pcie_clkreq_b";
+ pins = "gpio23";
+ };
+
+ pinctrl_robosw_led_clk: robosw_led_clk-pins {
+ function = "robosw_led_clk";
+ pins = "gpio30";
+ };
+
+ pinctrl_robosw_led_data: robosw_led_data-pins {
+ function = "robosw_led_data";
+ pins = "gpio31";
+ };
+
+ pinctrl_nand: nand-pins {
+ function = "nand";
+ group = "nand_grp";
+ };
+
+ pinctrl_gpio35_alt: gpio35_alt-pins {
+ function = "gpio35_alt";
+ pin = "gpio35";
+ };
+
+ pinctrl_dectpd: dectpd-pins {
+ function = "dectpd";
+ group = "dectpd_grp";
+ };
+
+ pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
+ function = "vdsl_phy_override_0";
+ group = "vdsl_phy_override_0_grp";
+ };
+
+ pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
+ function = "vdsl_phy_override_1";
+ group = "vdsl_phy_override_1_grp";
+ };
+
+ pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
+ function = "vdsl_phy_override_2";
+ group = "vdsl_phy_override_2_grp";
+ };
+
+ pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
+ function = "vdsl_phy_override_3";
+ group = "vdsl_phy_override_3_grp";
+ };
+
+ pinctrl_dsl_gpio8: dsl_gpio8-pins {
+ function = "dsl_gpio8";
+ group = "dsl_gpio8";
+ };
+
+ pinctrl_dsl_gpio9: dsl_gpio9-pins {
+ function = "dsl_gpio9";
+ group = "dsl_gpio9";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml
new file mode 100644
index 0000000000..33963c11ae
--- /dev/null
+++ b/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description:
+ Broadcom BCM6328 SoC GPIO system controller which provides a register map
+ for controlling the GPIO and pins of the SoC.
+
+properties:
+ "#address-cells": true
+
+ "#size-cells": true
+
+ compatible:
+ items:
+ - const: brcm,bcm6328-gpio-sysctl
+ - const: syscon
+ - const: simple-mfd
+
+ ranges:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
+ description:
+ GPIO controller for the SoC GPIOs. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
+
+ "^pinctrl@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../pinctrl/brcm,bcm6328-pinctrl.yaml"
+ description:
+ Pin controller for the SoC pins. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml.
+
+required:
+ - "#address-cells"
+ - compatible
+ - ranges
+ - reg
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10000080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "brcm,bcm6328-gpio-sysctl", "syscon", "simple-mfd";
+ reg = <0x10000080 0x80>;
+ ranges = <0 0x10000080 0x80>;
+
+ gpio@0 {
+ compatible = "brcm,bcm6328-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+ };
+
+ pinctrl: pinctrl@18 {
+ compatible = "brcm,bcm6328-pinctrl";
+ reg = <0x18 0x10>;
+
+ pinctrl_serial_led: serial_led-pins {
+ pinctrl_serial_led_data: serial_led_data-pins {
+ function = "serial_led_data";
+ pins = "gpio6";
+ };
+
+ pinctrl_serial_led_clk: serial_led_clk-pins {
+ function = "serial_led_clk";
+ pins = "gpio7";
+ };
+ };
+
+ pinctrl_inet_act_led: inet_act_led-pins {
+ function = "inet_act_led";
+ pins = "gpio11";
+ };
+
+ pinctrl_pcie_clkreq: pcie_clkreq-pins {
+ function = "pcie_clkreq";
+ pins = "gpio16";
+ };
+
+ pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
+ function = "led";
+ pins = "gpio17";
+ };
+
+ pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
+ function = "led";
+ pins = "gpio18";
+ };
+
+ pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
+ function = "led";
+ pins = "gpio19";
+ };
+
+ pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
+ function = "led";
+ pins = "gpio20";
+ };
+
+ pinctrl_ephy0_act_led: ephy0_act_led-pins {
+ function = "ephy0_act_led";
+ pins = "gpio25";
+ };
+
+ pinctrl_ephy1_act_led: ephy1_act_led-pins {
+ function = "ephy1_act_led";
+ pins = "gpio26";
+ };
+
+ pinctrl_ephy2_act_led: ephy2_act_led-pins {
+ function = "ephy2_act_led";
+ pins = "gpio27";
+ };
+
+ pinctrl_ephy3_act_led: ephy3_act_led-pins {
+ function = "ephy3_act_led";
+ pins = "gpio28";
+ };
+
+ pinctrl_hsspi_cs1: hsspi_cs1-pins {
+ function = "hsspi_cs1";
+ pins = "hsspi_cs1";
+ };
+
+ pinctrl_usb_port1_device: usb_port1_device-pins {
+ function = "usb_device_port";
+ pins = "usb_port1";
+ };
+
+ pinctrl_usb_port1_host: usb_port1_host-pins {
+ function = "usb_host_port";
+ pins = "usb_port1";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml
new file mode 100644
index 0000000000..3e44bea78b
--- /dev/null
+++ b/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6358 GPIO System Controller Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description:
+ Broadcom BCM6358 SoC GPIO system controller which provides a register map
+ for controlling the GPIO and pins of the SoC.
+
+properties:
+ "#address-cells": true
+
+ "#size-cells": true
+
+ compatible:
+ items:
+ - const: brcm,bcm6358-gpio-sysctl
+ - const: syscon
+ - const: simple-mfd
+
+ ranges:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
+ description:
+ GPIO controller for the SoC GPIOs. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
+
+ "^pinctrl@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../pinctrl/brcm,bcm6358-pinctrl.yaml"
+ description:
+ Pin controller for the SoC pins. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml.
+
+required:
+ - "#address-cells"
+ - compatible
+ - ranges
+ - reg
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@fffe0080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "brcm,bcm6358-gpio-sysctl", "syscon", "simple-mfd";
+ reg = <0xfffe0080 0x80>;
+ ranges = <0 0xfffe0080 0x80>;
+
+ gpio@0 {
+ compatible = "brcm,bcm6358-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 40>;
+ #gpio-cells = <2>;
+ };
+
+ pinctrl: pinctrl@18 {
+ compatible = "brcm,bcm6358-pinctrl";
+ reg = <0x18 0x4>;
+
+ pinctrl_ebi_cs: ebi_cs-pins {
+ function = "ebi_cs";
+ groups = "ebi_cs_grp";
+ };
+
+ pinctrl_uart1: uart1-pins {
+ function = "uart1";
+ groups = "uart1_grp";
+ };
+
+ pinctrl_serial_led: serial_led-pins {
+ function = "serial_led";
+ groups = "serial_led_grp";
+ };
+
+ pinctrl_legacy_led: legacy_led-pins {
+ function = "legacy_led";
+ groups = "legacy_led_grp";
+ };
+
+ pinctrl_led: led-pins {
+ function = "led";
+ groups = "led_grp";
+ };
+
+ pinctrl_spi_cs_23: spi_cs-pins {
+ function = "spi_cs";
+ groups = "spi_cs_grp";
+ };
+
+ pinctrl_utopia: utopia-pins {
+ function = "utopia";
+ groups = "utopia_grp";
+ };
+
+ pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
+ function = "pwm_syn_clk";
+ groups = "pwm_syn_clk_grp";
+ };
+
+ pinctrl_sys_irq: sys_irq-pins {
+ function = "sys_irq";
+ groups = "sys_irq_grp";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
new file mode 100644
index 0000000000..48d14a5fe0
--- /dev/null
+++ b/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
@@ -0,0 +1,236 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description:
+ Broadcom BCM6362 SoC GPIO system controller which provides a register map
+ for controlling the GPIO and pins of the SoC.
+
+properties:
+ "#address-cells": true
+
+ "#size-cells": true
+
+ compatible:
+ items:
+ - const: brcm,bcm6362-gpio-sysctl
+ - const: syscon
+ - const: simple-mfd
+
+ ranges:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
+ description:
+ GPIO controller for the SoC GPIOs. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
+
+ "^pinctrl@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml"
+ description:
+ Pin controller for the SoC pins. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.
+
+required:
+ - "#address-cells"
+ - compatible
+ - ranges
+ - reg
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10000080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd";
+ reg = <0x10000080 0x80>;
+ ranges = <0 0x10000080 0x80>;
+
+ gpio@0 {
+ compatible = "brcm,bcm6362-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 48>;
+ #gpio-cells = <2>;
+ };
+
+ pinctrl: pinctrl@18 {
+ compatible = "brcm,bcm6362-pinctrl";
+ reg = <0x18 0x10>, <0x38 0x4>;
+
+ pinctrl_usb_device_led: usb_device_led-pins {
+ function = "usb_device_led";
+ pins = "gpio0";
+ };
+
+ pinctrl_sys_irq: sys_irq-pins {
+ function = "sys_irq";
+ pins = "gpio1";
+ };
+
+ pinctrl_serial_led: serial_led-pins {
+ pinctrl_serial_led_clk: serial_led_clk-pins {
+ function = "serial_led_clk";
+ pins = "gpio2";
+ };
+
+ pinctrl_serial_led_data: serial_led_data-pins {
+ function = "serial_led_data";
+ pins = "gpio3";
+ };
+ };
+
+ pinctrl_robosw_led_data: robosw_led_data-pins {
+ function = "robosw_led_data";
+ pins = "gpio4";
+ };
+
+ pinctrl_robosw_led_clk: robosw_led_clk-pins {
+ function = "robosw_led_clk";
+ pins = "gpio5";
+ };
+
+ pinctrl_robosw_led0: robosw_led0-pins {
+ function = "robosw_led0";
+ pins = "gpio6";
+ };
+
+ pinctrl_robosw_led1: robosw_led1-pins {
+ function = "robosw_led1";
+ pins = "gpio7";
+ };
+
+ pinctrl_inet_led: inet_led-pins {
+ function = "inet_led";
+ pins = "gpio8";
+ };
+
+ pinctrl_spi_cs2: spi_cs2-pins {
+ function = "spi_cs2";
+ pins = "gpio9";
+ };
+
+ pinctrl_spi_cs3: spi_cs3-pins {
+ function = "spi_cs3";
+ pins = "gpio10";
+ };
+
+ pinctrl_ntr_pulse: ntr_pulse-pins {
+ function = "ntr_pulse";
+ pins = "gpio11";
+ };
+
+ pinctrl_uart1_scts: uart1_scts-pins {
+ function = "uart1_scts";
+ pins = "gpio12";
+ };
+
+ pinctrl_uart1_srts: uart1_srts-pins {
+ function = "uart1_srts";
+ pins = "gpio13";
+ };
+
+ pinctrl_uart1: uart1-pins {
+ pinctrl_uart1_sdin: uart1_sdin-pins {
+ function = "uart1_sdin";
+ pins = "gpio14";
+ };
+
+ pinctrl_uart1_sdout: uart1_sdout-pins {
+ function = "uart1_sdout";
+ pins = "gpio15";
+ };
+ };
+
+ pinctrl_adsl_spi: adsl_spi-pins {
+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
+ function = "adsl_spi_miso";
+ pins = "gpio16";
+ };
+
+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
+ function = "adsl_spi_mosi";
+ pins = "gpio17";
+ };
+
+ pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
+ function = "adsl_spi_clk";
+ pins = "gpio18";
+ };
+
+ pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
+ function = "adsl_spi_cs";
+ pins = "gpio19";
+ };
+ };
+
+ pinctrl_ephy0_led: ephy0_led-pins {
+ function = "ephy0_led";
+ pins = "gpio20";
+ };
+
+ pinctrl_ephy1_led: ephy1_led-pins {
+ function = "ephy1_led";
+ pins = "gpio21";
+ };
+
+ pinctrl_ephy2_led: ephy2_led-pins {
+ function = "ephy2_led";
+ pins = "gpio22";
+ };
+
+ pinctrl_ephy3_led: ephy3_led-pins {
+ function = "ephy3_led";
+ pins = "gpio23";
+ };
+
+ pinctrl_ext_irq0: ext_irq0-pins {
+ function = "ext_irq0";
+ pins = "gpio24";
+ };
+
+ pinctrl_ext_irq1: ext_irq1-pins {
+ function = "ext_irq1";
+ pins = "gpio25";
+ };
+
+ pinctrl_ext_irq2: ext_irq2-pins {
+ function = "ext_irq2";
+ pins = "gpio26";
+ };
+
+ pinctrl_ext_irq3: ext_irq3-pins {
+ function = "ext_irq3";
+ pins = "gpio27";
+ };
+
+ pinctrl_nand: nand-pins {
+ function = "nand";
+ group = "nand_grp";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml
new file mode 100644
index 0000000000..307270b0cf
--- /dev/null
+++ b/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml
@@ -0,0 +1,246 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+ - Jonas Gorski <jonas.gorski@gmail.com>
+
+description:
+ Broadcom BCM6368 SoC GPIO system controller which provides a register map
+ for controlling the GPIO and pins of the SoC.
+
+properties:
+ "#address-cells": true
+
+ "#size-cells": true
+
+ compatible:
+ items:
+ - const: brcm,bcm6368-gpio-sysctl
+ - const: syscon
+ - const: simple-mfd
+
+ ranges:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
+ description:
+ GPIO controller for the SoC GPIOs. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
+
+ "^pinctrl@[0-9a-f]+$":
+ # Child node
+ type: object
+ $ref: "../pinctrl/brcm,bcm6368-pinctrl.yaml"
+ description:
+ Pin controller for the SoC pins. This child node definition
+ should follow the bindings specified in
+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.
+
+required:
+ - "#address-cells"
+ - compatible
+ - ranges
+ - reg
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10000080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd";
+ reg = <0x10000080 0x80>;
+ ranges = <0 0x10000080 0x80>;
+
+ gpio@0 {
+ compatible = "brcm,bcm6368-gpio";
+ reg-names = "dirout", "dat";
+ reg = <0x0 0x8>, <0x8 0x8>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 38>;
+ #gpio-cells = <2>;
+ };
+
+ pinctrl: pinctrl@18 {
+ compatible = "brcm,bcm6368-pinctrl";
+ reg = <0x18 0x4>, <0x38 0x4>;
+
+ pinctrl_analog_afe_0: analog_afe_0-pins {
+ function = "analog_afe_0";
+ pins = "gpio0";
+ };
+
+ pinctrl_analog_afe_1: analog_afe_1-pins {
+ function = "analog_afe_1";
+ pins = "gpio1";
+ };
+
+ pinctrl_sys_irq: sys_irq-pins {
+ function = "sys_irq";
+ pins = "gpio2";
+ };
+
+ pinctrl_serial_led: serial_led-pins {
+ pinctrl_serial_led_data: serial_led_data-pins {
+ function = "serial_led_data";
+ pins = "gpio3";
+ };
+
+ pinctrl_serial_led_clk: serial_led_clk-pins {
+ function = "serial_led_clk";
+ pins = "gpio4";
+ };
+ };
+
+ pinctrl_inet_led: inet_led-pins {
+ function = "inet_led";
+ pins = "gpio5";
+ };
+
+ pinctrl_ephy0_led: ephy0_led-pins {
+ function = "ephy0_led";
+ pins = "gpio6";
+ };
+
+ pinctrl_ephy1_led: ephy1_led-pins {
+ function = "ephy1_led";
+ pins = "gpio7";
+ };
+
+ pinctrl_ephy2_led: ephy2_led-pins {
+ function = "ephy2_led";
+ pins = "gpio8";
+ };
+
+ pinctrl_ephy3_led: ephy3_led-pins {
+ function = "ephy3_led";
+ pins = "gpio9";
+ };
+
+ pinctrl_robosw_led_data: robosw_led_data-pins {
+ function = "robosw_led_data";
+ pins = "gpio10";
+ };
+
+ pinctrl_robosw_led_clk: robosw_led_clk-pins {
+ function = "robosw_led_clk";
+ pins = "gpio11";
+ };
+
+ pinctrl_robosw_led0: robosw_led0-pins {
+ function = "robosw_led0";
+ pins = "gpio12";
+ };
+
+ pinctrl_robosw_led1: robosw_led1-pins {
+ function = "robosw_led1";
+ pins = "gpio13";
+ };
+
+ pinctrl_usb_device_led: usb_device_led-pins {
+ function = "usb_device_led";
+ pins = "gpio14";
+ };
+
+ pinctrl_pci: pci-pins {
+ pinctrl_pci_req1: pci_req1-pins {
+ function = "pci_req1";
+ pins = "gpio16";
+ };
+
+ pinctrl_pci_gnt1: pci_gnt1-pins {
+ function = "pci_gnt1";
+ pins = "gpio17";
+ };
+
+ pinctrl_pci_intb: pci_intb-pins {
+ function = "pci_intb";
+ pins = "gpio18";
+ };
+
+ pinctrl_pci_req0: pci_req0-pins {
+ function = "pci_req0";
+ pins = "gpio19";
+ };
+
+ pinctrl_pci_gnt0: pci_gnt0-pins {
+ function = "pci_gnt0";
+ pins = "gpio20";
+ };
+ };
+
+ pinctrl_pcmcia: pcmcia-pins {
+ pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
+ function = "pcmcia_cd1";
+ pins = "gpio22";
+ };
+
+ pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
+ function = "pcmcia_cd2";
+ pins = "gpio23";
+ };
+
+ pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
+ function = "pcmcia_vs1";
+ pins = "gpio24";
+ };
+
+ pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
+ function = "pcmcia_vs2";
+ pins = "gpio25";
+ };
+ };
+
+ pinctrl_ebi_cs2: ebi_cs2-pins {
+ function = "ebi_cs2";
+ pins = "gpio26";
+ };
+
+ pinctrl_ebi_cs3: ebi_cs3-pins {
+ function = "ebi_cs3";
+ pins = "gpio27";
+ };
+
+ pinctrl_spi_cs2: spi_cs2-pins {
+ function = "spi_cs2";
+ pins = "gpio28";
+ };
+
+ pinctrl_spi_cs3: spi_cs3-pins {
+ function = "spi_cs3";
+ pins = "gpio29";
+ };
+
+ pinctrl_spi_cs4: spi_cs4-pins {
+ function = "spi_cs4";
+ pins = "gpio30";
+ };
+
+ pinctrl_spi_cs5: spi_cs5-pins {
+ function = "spi_cs5";
+ pins = "gpio31";
+ };
+
+ pinctrl_uart1: uart1-pins {
+ function = "uart1";
+ group = "uart1_grp";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/google,cros-ec.yaml b/dts/Bindings/mfd/google,cros-ec.yaml
index 76bf16ee27..4dfa70a013 100644
--- a/dts/Bindings/mfd/google,cros-ec.yaml
+++ b/dts/Bindings/mfd/google,cros-ec.yaml
@@ -94,6 +94,9 @@ properties:
keyboard-controller:
$ref: "/schemas/input/google,cros-ec-keyb.yaml#"
+ proximity:
+ $ref: "/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#"
+
codecs:
type: object
additionalProperties: false
@@ -180,6 +183,10 @@ examples:
interrupts = <99 0>;
interrupt-parent = <&gpio7>;
spi-max-frequency = <5000000>;
+
+ proximity {
+ compatible = "google,cros-ec-mkbp-proximity";
+ };
};
};
diff --git a/dts/Bindings/mfd/netronix,ntxec.yaml b/dts/Bindings/mfd/netronix,ntxec.yaml
new file mode 100644
index 0000000000..59a630025f
--- /dev/null
+++ b/dts/Bindings/mfd/netronix,ntxec.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/netronix,ntxec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Netronix Embedded Controller
+
+maintainers:
+ - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+
+description: |
+ This EC is found in e-book readers of multiple brands (e.g. Kobo, Tolino), and
+ is typically implemented as a TI MSP430 microcontroller.
+
+properties:
+ compatible:
+ const: netronix,ntxec
+
+ reg:
+ items:
+ - description: The I2C address of the EC
+
+ system-power-controller:
+ type: boolean
+ description: See Documentation/devicetree/bindings/power/power-controller.txt
+
+ interrupts:
+ minItems: 1
+ description:
+ The EC can signal interrupts via a GPIO line
+
+ "#pwm-cells":
+ const: 2
+ description: |
+ Number of cells in a PWM specifier.
+
+ The following PWM channels are supported:
+ - 0: The PWM channel controlled by registers 0xa1-0xa7
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ec: embedded-controller@43 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ntxec>;
+
+ compatible = "netronix,ntxec";
+ reg = <0x43>;
+ system-power-controller;
+ interrupt-parent = <&gpio4>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ #pwm-cells = <2>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ec 0 50000>;
+ power-supply = <&backlight_regulator>;
+ };
+
+ backlight_regulator: regulator-dummy {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight";
+ };
diff --git a/dts/Bindings/mfd/qcom-pm8xxx.txt b/dts/Bindings/mfd/qcom-pm8xxx.txt
deleted file mode 100644
index 9e5eba4a4f..0000000000
--- a/dts/Bindings/mfd/qcom-pm8xxx.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-Qualcomm PM8xxx PMIC multi-function devices
-
-The PM8xxx family of Power Management ICs are used to provide regulated
-voltages and other various functionality to Qualcomm SoCs.
-
-= PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be one of:
- "qcom,pm8058"
- "qcom,pm8821"
- "qcom,pm8921"
-
-- #address-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 1
-
-- #size-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 0
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: specifies the interrupt that indicates a subdevice
- has generated an interrupt (summary interrupt). The
- format of the specifier is defined by the binding document
- describing the node's interrupt parent.
-
-- #interrupt-cells:
- Usage: required
- Value type : <u32>
- Definition: must be 2. Specifies the number of cells needed to encode
- an interrupt source. The 1st cell contains the interrupt
- number. The 2nd cell is the trigger type and level flags
- encoded as follows:
-
- 1 = low-to-high edge triggered
- 2 = high-to-low edge triggered
- 4 = active high level-sensitive
- 8 = active low level-sensitive
-
-- interrupt-controller:
- Usage: required
- Value type: <empty>
- Definition: identifies this node as an interrupt controller
-
-= SUBCOMPONENTS
-
-The PMIC contains multiple independent functions, each described in a subnode.
-The below bindings specify the set of valid subnodes.
-
-== Real-Time Clock
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be one of:
- "qcom,pm8058-rtc"
- "qcom,pm8921-rtc"
- "qcom,pm8941-rtc"
- "qcom,pm8018-rtc"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: single entry specifying the base address of the RTC registers
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: single entry specifying the RTC's alarm interrupt
-
-- allow-set-time:
- Usage: optional
- Value type: <empty>
- Definition: indicates that the setting of RTC time is allowed by
- the host CPU
-
-= EXAMPLE
-
- pmicintc: pmic@0 {
- compatible = "qcom,pm8921";
- interrupts = <104 8>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@11d {
- compatible = "qcom,pm8921-rtc";
- reg = <0x11d>;
- interrupts = <0x27 0>;
- };
- };
diff --git a/dts/Bindings/mfd/qcom-pm8xxx.yaml b/dts/Bindings/mfd/qcom-pm8xxx.yaml
new file mode 100644
index 0000000000..9065ec53e6
--- /dev/null
+++ b/dts/Bindings/mfd/qcom-pm8xxx.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qcom-pm8xxx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PM8xxx PMIC multi-function devices
+
+maintainers:
+ - Satya Priya <skakit@codeaurora.org>
+
+description: |
+ The PM8xxx family of Power Management ICs are used to provide regulated
+ voltages and other various functionality to Qualcomm SoCs.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pm8058
+ - qcom,pm8821
+ - qcom,pm8921
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ interrupts:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupt-controller: true
+
+patternProperties:
+ "rtc@[0-9a-f]+$":
+ type: object
+ $ref: "../rtc/qcom-pm8xxx-rtc.yaml"
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+ - interrupts
+ - '#interrupt-cells'
+ - interrupt-controller
+
+additionalProperties: false
+...
diff --git a/dts/Bindings/mfd/ricoh,rn5t618.yaml b/dts/Bindings/mfd/ricoh,rn5t618.yaml
new file mode 100644
index 0000000000..032a7fb0b4
--- /dev/null
+++ b/dts/Bindings/mfd/ricoh,rn5t618.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/ricoh,rn5t618.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ricoh RN5T567/RN5T618/RC5T619 PMIC
+
+maintainers:
+ - Andreas Kemnade <andreas@kemnade.info>
+
+description: |
+ Ricoh RN5T567/RN5T618/RC5T619 is a power management IC family which
+ integrates 3 to 5 step-down DCDC converters, 7 to 10 low-dropout regulators,
+ GPIOs, and a watchdog timer. It can be controlled through an I2C interface.
+ The RN5T618/RC5T619 provides additionally a Li-ion battery charger,
+ fuel gauge, and an ADC.
+ The RC5T619 additionally includes USB charger detection and an RTC.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ricoh,rn5t567
+ then:
+ properties:
+ regulators:
+ patternProperties:
+ "^(DCDC[1-4]|LDO[1-5]|LDORTC[12])$":
+ $ref: ../regulator/regulator.yaml
+ additionalProperties: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ricoh,rn5t618
+ then:
+ properties:
+ regulators:
+ patternProperties:
+ "^(DCDC[1-3]|LDO[1-5]|LDORTC[12])$":
+ $ref: ../regulator/regulator.yaml
+ additionalProperties: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ricoh,rc5t619
+ then:
+ properties:
+ regulators:
+ patternProperties:
+ "^(DCDC[1-5]|LDO[1-9]|LDO10|LDORTC[12])$":
+ $ref: ../regulator/regulator.yaml
+ additionalProperties: false
+
+properties:
+ compatible:
+ enum:
+ - ricoh,rn5t567
+ - ricoh,rn5t618
+ - ricoh,rc5t619
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ system-power-controller:
+ type: boolean
+ description: |
+ See Documentation/devicetree/bindings/power/power-controller.txt
+
+ regulators:
+ type: object
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@32 {
+ compatible = "ricoh,rn5t618";
+ reg = <0x32>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ system-power-controller;
+
+ regulators {
+ DCDC1 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ DCDC2 {
+ regulator-min-microvolt = <1175000>;
+ regulator-max-microvolt = <1175000>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/rn5t618.txt b/dts/Bindings/mfd/rn5t618.txt
deleted file mode 100644
index 16778ea00d..0000000000
--- a/dts/Bindings/mfd/rn5t618.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* Ricoh RN5T567/RN5T618 PMIC
-
-Ricoh RN5T567/RN5T618/RC5T619 is a power management IC family which
-integrates 3 to 5 step-down DCDC converters, 7 to 10 low-dropout regulators,
-GPIOs, and a watchdog timer. It can be controlled through an I2C interface.
-The RN5T618/RC5T619 provides additionally a Li-ion battery charger,
-fuel gauge, and an ADC.
-The RC5T619 additionnally includes USB charger detection and an RTC.
-
-Required properties:
- - compatible: must be one of
- "ricoh,rn5t567"
- "ricoh,rn5t618"
- "ricoh,rc5t619"
- - reg: the I2C slave address of the device
-
-Optional properties:
- - interrupts: interrupt mapping for IRQ
- See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- - system-power-controller:
- See Documentation/devicetree/bindings/power/power-controller.txt
-
-Sub-nodes:
- - regulators: the node is required if the regulator functionality is
- needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4
- (RN5T567/RC5T619), LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8,
- LDO9, LDO10, LDORTC1 and LDORTC2.
- LDO7-10 are specific to RC5T619.
- The common bindings for each individual regulator can be found in:
- Documentation/devicetree/bindings/regulator/regulator.txt
-
-Example:
-
- pmic@32 {
- compatible = "ricoh,rn5t618";
- reg = <0x32>;
- interrupt-parent = <&gpio5>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- system-power-controller;
-
- regulators {
- DCDC1 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- DCDC2 {
- regulator-min-microvolt = <1175000>;
- regulator-max-microvolt = <1175000>;
- };
- };
- };
diff --git a/dts/Bindings/mfd/rohm,bd71815-pmic.yaml b/dts/Bindings/mfd/rohm,bd71815-pmic.yaml
new file mode 100644
index 0000000000..fe265bcab5
--- /dev/null
+++ b/dts/Bindings/mfd/rohm,bd71815-pmic.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rohm,bd71815-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD71815 Power Management Integrated Circuit bindings
+
+maintainers:
+ - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+
+description: |
+ BD71815AGW is a single-chip power management ICs for battery-powered
+ portable devices. It integrates 5 buck converters, 8 LDOs, a boost driver
+ for LED and a 500 mA single-cell linear charger. Also included is a Coulomb
+ counter, a real-time clock (RTC), and a 32.768 kHz clock gate and two GPOs.
+
+properties:
+ compatible:
+ const: rohm,bd71815
+
+ reg:
+ description:
+ I2C slave address.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ The first cell is the pin number and the second cell is used to specify
+ flags. See ../gpio/gpio.txt for more information.
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ const: bd71815-32k-out
+
+ rohm,clkout-open-drain:
+ description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 1
+
+ rohm,charger-sense-resistor-ohms:
+ minimum: 10000000
+ maximum: 50000000
+ description: |
+ BD71827 and BD71828 have SAR ADC for measuring charging currents.
+ External sense resistor (RSENSE in data sheet) should be used. If
+ something other but 30MOhm resistor is used the resistance value
+ should be given here in Ohms.
+ default: 30000000
+
+ regulators:
+ $ref: ../regulator/rohm,bd71815-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+ gpio-reserved-ranges:
+ description: |
+ Usage of BD71828 GPIO pins can be changed via OTP. This property can be
+ used to mark the pins which should not be configured for GPIO. Please see
+ the ../gpio/gpio.txt for more information.
+
+ rohm,enable-hidden-gpo:
+ description: |
+ The BD71815 has undocumented GPO at pin E5. Pin is marked as GND at the
+ data-sheet as it's location in the middle of GND pins makes it hard to
+ use on PCB. If your board has managed to use this pin you can enable the
+ second GPO by defining this property. Dont enable this if you are unsure
+ about how the E5 pin is connected on your board.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - "#clock-cells"
+ - regulators
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/leds/common.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic: pmic@4b {
+ compatible = "rohm,bd71815";
+ reg = <0x4b>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ clocks = <&osc 0>;
+ #clock-cells = <0>;
+ clock-output-names = "bd71815-32k-out";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rohm,charger-sense-resistor-ohms = <10000000>;
+
+ regulators {
+ buck1: buck1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1150000>;
+ rohm,dvs-suspend-voltage = <950000>;
+ };
+ buck2: buck2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1150000>;
+ rohm,dvs-suspend-voltage = <950000>;
+ };
+ buck3: buck3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-always-on;
+ };
+ buck4: buck4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-always-on;
+ };
+ buck5: buck5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ ldo1: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ ldo2: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ ldo3: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ ldo4: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ ldo5: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ ldo6: ldodvref {
+ regulator-name = "ldodvref";
+ regulator-always-on;
+ };
+ ldo7: ldolpsr {
+ regulator-name = "ldolpsr";
+ regulator-always-on;
+ };
+
+ boost: wled {
+ regulator-name = "wled";
+ regulator-min-microamp = <10>;
+ regulator-max-microamp = <25000>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/rohm,bd71828-pmic.yaml b/dts/Bindings/mfd/rohm,bd71828-pmic.yaml
index 3a6a1a26e2..8380166d17 100644
--- a/dts/Bindings/mfd/rohm,bd71828-pmic.yaml
+++ b/dts/Bindings/mfd/rohm,bd71828-pmic.yaml
@@ -44,6 +44,12 @@ properties:
clock-output-names:
const: bd71828-32k-out
+ rohm,clkout-open-drain:
+ description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 1
+
rohm,charger-sense-resistor-ohms:
minimum: 10000000
maximum: 50000000
diff --git a/dts/Bindings/mfd/rohm,bd9576-pmic.yaml b/dts/Bindings/mfd/rohm,bd9576-pmic.yaml
new file mode 100644
index 0000000000..6483860da9
--- /dev/null
+++ b/dts/Bindings/mfd/rohm,bd9576-pmic.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD9576MUF and BD9573MUF Power Management Integrated Circuit bindings
+
+maintainers:
+ - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+
+description: |
+ BD9576MUF and BD9573MUF are power management ICs primarily intended for
+ powering the R-Car series processors.
+ The IC provides 6 power outputs with configurable sequencing and safety
+ monitoring. A watchdog logic with slow ping/windowed modes is also included.
+
+properties:
+ compatible:
+ enum:
+ - rohm,bd9576
+ - rohm,bd9573
+
+ reg:
+ description:
+ I2C slave address.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ rohm,vout1-en-low:
+ description:
+ BD9576 and BD9573 VOUT1 regulator enable state can be individually
+ controlled by a GPIO. This is dictated by state of vout1-en pin during
+ the PMIC startup. If vout1-en is LOW during PMIC startup then the VOUT1
+ enable sate is controlled via this pin. Set this property if vout1-en
+ is wired to be down at PMIC start-up.
+ type: boolean
+
+ rohm,vout1-en-gpios:
+ description:
+ GPIO specifier to specify the GPIO connected to vout1-en for vout1 ON/OFF
+ state control.
+ maxItems: 1
+
+ rohm,ddr-sel-low:
+ description:
+ The BD9576 and BD9573 output voltage for DDR can be selected by setting
+ the ddr-sel pin low or high. Set this property if ddr-sel is grounded.
+ type: boolean
+
+ rohm,watchdog-enable-gpios:
+ description: The GPIO line used to enable the watchdog.
+ maxItems: 1
+
+ rohm,watchdog-ping-gpios:
+ description: The GPIO line used to ping the watchdog.
+ maxItems: 1
+
+ rohm,hw-timeout-ms:
+ maxItems: 2
+ description:
+ Watchog timeout in milliseconds. If single value is given it is
+ the maximum timeout. Eg. if pinging watchdog is not done within this time
+ limit the watchdog will be triggered. If two values are given watchdog
+ is configured in "window mode". Then first value is limit for short-ping
+ Eg. if watchdog is pinged sooner than that the watchdog will trigger.
+ When two values is given the second value is the maximum timeout.
+ # (HW) minimum for short timeout is 2ms, maximum 220 ms.
+ # (HW) minimum for max timeout is 4ms, maximum 4416 ms.
+
+ regulators:
+ $ref: ../regulator/rohm,bd9576-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+required:
+ - compatible
+ - reg
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic: pmic@30 {
+ compatible = "rohm,bd9576";
+ reg = <0x30>;
+ rohm,vout1-en-low;
+ rohm,vout1-en-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ rohm,ddr-sel-low;
+ rohm,watchdog-enable-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ rohm,watchdog-ping-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ rohm,hw-timeout-ms = <150>, <2300>;
+
+ regulators {
+ boost1: regulator-vd50 {
+ regulator-name = "VD50";
+ };
+ buck1: regulator-vd18 {
+ regulator-name = "VD18";
+ };
+ buck2: regulator-vdddr {
+ regulator-name = "VDDDR";
+ };
+ buck3: regulator-vd10 {
+ regulator-name = "VD10";
+ };
+ ldo: regulator-voutl1 {
+ regulator-name = "VOUTL1";
+ };
+ sw: regulator-vouts1 {
+ regulator-name = "VOUTS1";
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/ti,lp87524-q1.yaml b/dts/Bindings/mfd/ti,lp87524-q1.yaml
index c4fc5345d3..f6cac4b107 100644
--- a/dts/Bindings/mfd/ti,lp87524-q1.yaml
+++ b/dts/Bindings/mfd/ti,lp87524-q1.yaml
@@ -17,6 +17,10 @@ properties:
description: I2C slave address
const: 0x60
+ reset-gpios:
+ description: GPIO connected to NRST pin (active low reset, pin 20)
+ maxItems: 1
+
gpio-controller: true
'#gpio-cells':
diff --git a/dts/Bindings/mfd/ti,lp87561-q1.yaml b/dts/Bindings/mfd/ti,lp87561-q1.yaml
index a7e57c0913..dc5a29b5ef 100644
--- a/dts/Bindings/mfd/ti,lp87561-q1.yaml
+++ b/dts/Bindings/mfd/ti,lp87561-q1.yaml
@@ -17,6 +17,10 @@ properties:
description: I2C slave address
const: 0x60
+ reset-gpios:
+ description: GPIO connected to NRST pin (active low reset, pin 20)
+ maxItems: 1
+
gpio-controller: true
'#gpio-cells':
diff --git a/dts/Bindings/mfd/ti,lp87565-q1.yaml b/dts/Bindings/mfd/ti,lp87565-q1.yaml
index 1da6d6a958..48d4d53c25 100644
--- a/dts/Bindings/mfd/ti,lp87565-q1.yaml
+++ b/dts/Bindings/mfd/ti,lp87565-q1.yaml
@@ -19,6 +19,10 @@ properties:
description: I2C slave address
const: 0x60
+ reset-gpios:
+ description: GPIO connected to NRST pin (active low reset, pin 20)
+ maxItems: 1
+
gpio-controller: true
'#gpio-cells':
diff --git a/dts/Bindings/mmc/brcm,iproc-sdhci.yaml b/dts/Bindings/mmc/brcm,iproc-sdhci.yaml
new file mode 100644
index 0000000000..6f569fbfa1
--- /dev/null
+++ b/dts/Bindings/mmc/brcm,iproc-sdhci.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom IPROC SDHCI controller
+
+maintainers:
+ - Ray Jui <ray.jui@broadcom.com>
+ - Scott Branden <scott.branden@broadcom.com>
+ - Nicolas Saenz Julienne <nsaenz@kernel.org>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2835-sdhci
+ - brcm,bcm2711-emmc2
+ - brcm,sdhci-iproc-cygnus
+ - brcm,sdhci-iproc
+
+ reg:
+ minItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Handle to core clock for the sdhci controller.
+
+ sdhci,auto-cmd12:
+ type: boolean
+ description: Specifies that controller should use auto CMD12
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/bcm-cygnus.h>
+
+ mmc@18041000 {
+ compatible = "brcm,sdhci-iproc-cygnus";
+ reg = <0x18041000 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
+ bus-width = <4>;
+ sdhci,auto-cmd12;
+ no-1-8-v;
+ };
+...
diff --git a/dts/Bindings/mmc/brcm,sdhci-iproc.txt b/dts/Bindings/mmc/brcm,sdhci-iproc.txt
deleted file mode 100644
index 09d87cc118..0000000000
--- a/dts/Bindings/mmc/brcm,sdhci-iproc.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-Broadcom IPROC SDHCI controller
-
-This file documents differences between the core properties described
-by mmc.txt and the properties that represent the IPROC SDHCI controller.
-
-Required properties:
-- compatible : Should be one of the following
- "brcm,bcm2835-sdhci"
- "brcm,bcm2711-emmc2"
- "brcm,sdhci-iproc-cygnus"
- "brcm,sdhci-iproc"
-
-Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
-bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
-
-Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
-restricted to 32bit host accesses to SDHCI registers.
-
-Use sdhci-iproc for Broadcom SDHCI Controllers that allow standard
-8, 16, 32-bit host access to SDHCI register.
-
-- clocks : The clock feeding the SDHCI controller.
-
-Optional properties:
- - sdhci,auto-cmd12: specifies that controller should use auto CMD12.
-
-Example:
-
-sdhci0: sdhci@18041000 {
- compatible = "brcm,sdhci-iproc-cygnus";
- reg = <0x18041000 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
- bus-width = <4>;
- sdhci,auto-cmd12;
- no-1-8-v;
-};
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.yaml b/dts/Bindings/mmc/fsl-imx-esdhc.yaml
index 802c9df237..3694718144 100644
--- a/dts/Bindings/mmc/fsl-imx-esdhc.yaml
+++ b/dts/Bindings/mmc/fsl-imx-esdhc.yaml
@@ -103,6 +103,26 @@ properties:
Only eMMC HS400 mode need to take care of this property.
default: 0
+ clocks:
+ maxItems: 3
+ description:
+ Handle clocks for the sdhc controller.
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: ahb
+ - const: per
+
+ pinctrl-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: default
+ - const: state_100mhz
+ - const: state_200mhz
+ - const: sleep
+
required:
- compatible
- reg
diff --git a/dts/Bindings/mmc/mmc-spi-slot.txt b/dts/Bindings/mmc/mmc-spi-slot.txt
index 75486cca80..5e74db69f5 100644
--- a/dts/Bindings/mmc/mmc-spi-slot.txt
+++ b/dts/Bindings/mmc/mmc-spi-slot.txt
@@ -5,11 +5,11 @@ by mmc.txt and the properties used by the mmc_spi driver.
Required properties:
- spi-max-frequency : maximum frequency for this device (Hz).
-- voltage-ranges : two cells are required, first cell specifies minimum
- slot voltage (mV), second cell specifies maximum slot voltage (mV).
- Several ranges could be specified.
Optional properties:
+- voltage-ranges : two cells are required, first cell specifies minimum
+ slot voltage (mV), second cell specifies maximum slot voltage (mV).
+ Several ranges could be specified. If not provided, 3.2v..3.4v is assumed.
- gpios : may specify GPIOs in this order: Card-Detect GPIO,
Write-Protect GPIO. Note that this does not follow the
binding from mmc.txt, for historical reasons.
diff --git a/dts/Bindings/mmc/mtk-sd.yaml b/dts/Bindings/mmc/mtk-sd.yaml
index 01630b0ece..8648d48dbb 100644
--- a/dts/Bindings/mmc/mtk-sd.yaml
+++ b/dts/Bindings/mmc/mtk-sd.yaml
@@ -31,6 +31,7 @@ properties:
- const: mediatek,mt2701-mmc
- items:
- const: mediatek,mt8192-mmc
+ - const: mediatek,mt8195-mmc
- const: mediatek,mt8183-mmc
clocks:
diff --git a/dts/Bindings/mmc/sdhci-of-dwcmshc.txt b/dts/Bindings/mmc/sdhci-of-dwcmshc.txt
deleted file mode 100644
index ee4253b33b..0000000000
--- a/dts/Bindings/mmc/sdhci-of-dwcmshc.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Synopsys DesignWare Cores Mobile Storage Host Controller
-
-Required properties:
-- compatible: should be one of the following:
- "snps,dwcmshc-sdhci"
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: Array of clocks required for SDHCI; requires at least one for
- core clock.
-- clock-names: Array of names corresponding to clocks property; shall be
- "core" for core clock and "bus" for optional bus clock.
-
-Example:
- sdhci2: sdhci@aa0000 {
- compatible = "snps,dwcmshc-sdhci";
- reg = <0xaa0000 0x1000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&emmcclk>;
- bus-width = <8>;
- }
diff --git a/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml b/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml
new file mode 100644
index 0000000000..e6c9a2f77c
--- /dev/null
+++ b/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys Designware Mobile Storage Host Controller Binding
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+ - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-dwcmshc
+ - snps,dwcmshc-sdhci
+
+ reg:
+ minItems: 1
+ items:
+ - description: Offset and length of the register set for the device
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: core clock
+ - description: bus clock for optional
+ - description: axi clock for rockchip specified
+ - description: block clock for rockchip specified
+ - description: timer clock for rockchip specified
+
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: bus
+ - const: axi
+ - const: block
+ - const: timer
+
+ rockchip,txclk-tapnum:
+ description: Specify the number of delay for tx sampling.
+ $ref: /schemas/types.yaml#/definitions/uint8
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@fe310000 {
+ compatible = "rockchip,rk3568-dwcmshc";
+ reg = <0xfe310000 0x10000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - |
+ mmc@aa0000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xaa000 0x1000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>;
+ clock-names = "core", "bus";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+...
diff --git a/dts/Bindings/mtd/nand-controller.yaml b/dts/Bindings/mtd/nand-controller.yaml
index d0e422f4b3..678b399525 100644
--- a/dts/Bindings/mtd/nand-controller.yaml
+++ b/dts/Bindings/mtd/nand-controller.yaml
@@ -143,6 +143,13 @@ patternProperties:
Ready/Busy pins. Active state refers to the NAND ready state and
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
+ secure-regions:
+ $ref: /schemas/types.yaml#/definitions/uint64-matrix
+ description:
+ Regions in the NAND chip which are protected using a secure element
+ like Trustzone. This property contains the start address and size of
+ the secure regions present.
+
required:
- reg
diff --git a/dts/Bindings/mtd/partitions/linksys,ns-partitions.yaml b/dts/Bindings/mtd/partitions/linksys,ns-partitions.yaml
new file mode 100644
index 0000000000..99249cdfbf
--- /dev/null
+++ b/dts/Bindings/mtd/partitions/linksys,ns-partitions.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/linksys,ns-partitions.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Linksys Northstar partitioning
+
+description: |
+ Linksys devices based on Broadcom Northstar architecture often use two
+ firmware partitions. One is used for regular booting, the other is treated as
+ fallback.
+
+ This binding allows defining all fixed partitions and marking those containing
+ firmware. System can use that information e.g. for booting or flashing
+ purposes.
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+ compatible:
+ const: linksys,ns-partitions
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+patternProperties:
+ "^partition@[0-9a-f]+$":
+ $ref: "partition.yaml#"
+ properties:
+ compatible:
+ items:
+ - const: linksys,ns-firmware
+ - const: brcm,trx
+ unevaluatedProperties: false
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ partitions {
+ compatible = "linksys,ns-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "nvram";
+ reg = <0x100000 0x100000>;
+ };
+
+ partition@200000 {
+ compatible = "linksys,ns-firmware", "brcm,trx";
+ reg = <0x200000 0xf00000>;
+ };
+
+ partition@1100000 {
+ compatible = "linksys,ns-firmware", "brcm,trx";
+ reg = <0x1100000 0xf00000>;
+ };
+ };
diff --git a/dts/Bindings/mtd/partitions/nvmem-cells.yaml b/dts/Bindings/mtd/partitions/nvmem-cells.yaml
new file mode 100644
index 0000000000..5cdd2efa91
--- /dev/null
+++ b/dts/Bindings/mtd/partitions/nvmem-cells.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/nvmem-cells.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nvmem cells
+
+description: |
+ Any partition containing the compatible "nvmem-cells" will register as a
+ nvmem provider.
+ Each direct subnodes represents a nvmem cell following the nvmem binding.
+ Nvmem binding to declare nvmem-cells can be found in:
+ Documentation/devicetree/bindings/nvmem/nvmem.yaml
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+allOf:
+ - $ref: /schemas/nvmem/nvmem.yaml#
+
+properties:
+ compatible:
+ const: nvmem-cells
+
+required:
+ - compatible
+
+additionalProperties: true
+
+examples:
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* ... */
+
+ };
+ art: art@1200000 {
+ compatible = "nvmem-cells";
+ reg = <0x1200000 0x0140000>;
+ label = "art";
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_gmac1: macaddr_gmac1@0 {
+ reg = <0x0 0x6>;
+ };
+
+ macaddr_gmac2: macaddr_gmac2@6 {
+ reg = <0x6 0x6>;
+ };
+
+ pre_cal_24g: pre_cal_24g@1000 {
+ reg = <0x1000 0x2f20>;
+ };
+
+ pre_cal_5g: pre_cal_5g@5000{
+ reg = <0x5000 0x2f20>;
+ };
+ };
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x000000 0x100000>;
+ read-only;
+ };
+
+ firmware@100000 {
+ compatible = "brcm,trx";
+ label = "firmware";
+ reg = <0x100000 0xe00000>;
+ };
+
+ calibration@f00000 {
+ compatible = "nvmem-cells";
+ label = "calibration";
+ reg = <0xf00000 0x100000>;
+ ranges = <0 0xf00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ wifi0@0 {
+ reg = <0x000000 0x080000>;
+ };
+
+ wifi1@80000 {
+ reg = <0x080000 0x080000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/mtd/qcom,nandc.yaml b/dts/Bindings/mtd/qcom,nandc.yaml
new file mode 100644
index 0000000000..84ad7ff301
--- /dev/null
+++ b/dts/Bindings/mtd/qcom,nandc.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NAND controller
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq806x-nand
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Core Clock
+ - description: Always ON Clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: aon
+
+ "#address-cells": true
+ "#size-cells": true
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ nand-bus-width:
+ const: 8
+
+ nand-ecc-strength:
+ enum: [1, 4, 8]
+
+ nand-ecc-step-size:
+ enum:
+ - 512
+
+allOf:
+ - $ref: "nand-controller.yaml#"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ipq806x-nand
+ then:
+ properties:
+ dmas:
+ items:
+ - description: rxtx DMA channel
+
+ dma-names:
+ items:
+ - const: rxtx
+
+ qcom,cmd-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM command type CRCI block instance number
+ specified for the NAND controller on the given platform
+
+ qcom,data-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM data type CRCI block instance number
+ specified for the NAND controller on the given platform
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
+
+ then:
+ properties:
+ dmas:
+ items:
+ - description: tx DMA channel
+ - description: rx DMA channel
+ - description: cmd DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ - const: cmd
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+ nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+ };
+
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/mtd/qcom_nandc.txt b/dts/Bindings/mtd/qcom_nandc.txt
deleted file mode 100644
index 5647913d88..0000000000
--- a/dts/Bindings/mtd/qcom_nandc.txt
+++ /dev/null
@@ -1,142 +0,0 @@
-* Qualcomm NAND controller
-
-Required properties:
-- compatible: must be one of the following:
- * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
- SoC and it uses ADM DMA
- * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
- IPQ4019 SoC and it uses BAM DMA
- * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
- IPQ6018 SoC and it uses BAM DMA
- * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
- IPQ8074 SoC and it uses BAM DMA
- * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
- SDX55 SoC and it uses BAM DMA
-
-- reg: MMIO address range
-- clocks: must contain core clock and always on clock
-- clock-names: must contain "core" for the core clock and "aon" for the
- always on clock
-
-EBI2 specific properties:
-- dmas: DMA specifier, consisting of a phandle to the ADM DMA
- controller node and the channel number to be used for
- NAND. Refer to dma.txt and qcom_adm.txt for more details
-- dma-names: must be "rxtx"
-- qcom,cmd-crci: must contain the ADM command type CRCI block instance
- number specified for the NAND controller on the given
- platform
-- qcom,data-crci: must contain the ADM data type CRCI block instance
- number specified for the NAND controller on the given
- platform
-
-QPIC specific properties:
-- dmas: DMA specifier, consisting of a phandle to the BAM DMA
- and the channel number to be used for NAND. Refer to
- dma.txt, qcom_bam_dma.txt for more details
-- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
-- #address-cells: <1> - subnodes give the chip-select number
-- #size-cells: <0>
-
-* NAND chip-select
-
-Each controller may contain one or more subnodes to represent enabled
-chip-selects which (may) contain NAND flash chips. Their properties are as
-follows.
-
-Required properties:
-- reg: a single integer representing the chip-select
- number (e.g., 0, 1, 2, etc.)
-- #address-cells: see partition.txt
-- #size-cells: see partition.txt
-
-Optional properties:
-- nand-bus-width: see nand-controller.yaml
-- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
- be used according to chip requirement and available
- OOB size.
-
-Each nandcs device node may optionally contain a 'partitions' sub-node, which
-further contains sub-nodes describing the flash partition mapping. See
-partition.txt for more detail.
-
-Example:
-
-nand-controller@1ac00000 {
- compatible = "qcom,ipq806x-nand";
- reg = <0x1ac00000 0x800>;
-
- clocks = <&gcc EBI2_CLK>,
- <&gcc EBI2_AON_CLK>;
- clock-names = "core", "aon";
-
- dmas = <&adm_dma 3>;
- dma-names = "rxtx";
- qcom,cmd-crci = <15>;
- qcom,data-crci = <3>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "boot-nand";
- reg = <0 0x58a0000>;
- };
-
- partition@58a0000 {
- label = "fs-nand";
- reg = <0x58a0000 0x4000000>;
- };
- };
- };
-};
-
-nand-controller@79b0000 {
- compatible = "qcom,ipq4019-nand";
- reg = <0x79b0000 0x1000>;
-
- clocks = <&gcc GCC_QPIC_CLK>,
- <&gcc GCC_QPIC_AHB_CLK>;
- clock-names = "core", "aon";
-
- dmas = <&qpicbam 0>,
- <&qpicbam 1>,
- <&qpicbam 2>;
- dma-names = "tx", "rx", "cmd";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>;
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "boot-nand";
- reg = <0 0x58a0000>;
- };
-
- partition@58a0000 {
- label = "fs-nand";
- reg = <0x58a0000 0x4000000>;
- };
- };
- };
-};
diff --git a/dts/Bindings/mtd/tango-nand.txt b/dts/Bindings/mtd/tango-nand.txt
deleted file mode 100644
index 91c8420241..0000000000
--- a/dts/Bindings/mtd/tango-nand.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Sigma Designs Tango4 NAND Flash Controller (NFC)
-
-Required properties:
-
-- compatible: "sigma,smp8758-nand"
-- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
-- dmas: reference to the DMA channel used by the controller
-- dma-names: "rxtx"
-- clocks: reference to the system clock
-- #address-cells: <1>
-- #size-cells: <0>
-
-Children nodes represent the available NAND chips.
-See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
-
-Example:
-
- nandc: nand-controller@2c000 {
- compatible = "sigma,smp8758-nand";
- reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
- dmas = <&dma0 3>;
- dma-names = "rxtx";
- clocks = <&clkgen SYS_CLK>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>; /* CS0 */
- nand-ecc-strength = <14>;
- nand-ecc-step-size = <1024>;
- };
-
- nand@1 {
- reg = <1>; /* CS1 */
- nand-ecc-strength = <14>;
- nand-ecc-step-size = <1024>;
- };
- };
diff --git a/dts/Bindings/net/actions,owl-emac.yaml b/dts/Bindings/net/actions,owl-emac.yaml
new file mode 100644
index 0000000000..1626e0a821
--- /dev/null
+++ b/dts/Bindings/net/actions,owl-emac.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl SoCs Ethernet MAC Controller
+
+maintainers:
+ - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+
+description: |
+ This Ethernet MAC is used on the Owl family of SoCs from Actions Semi.
+ It provides the RMII and SMII interfaces and is compliant with the
+ IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
+ operation modes at 10/100 Mb/s data transfer rates.
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - const: actions,owl-emac
+ - items:
+ - enum:
+ - actions,s500-emac
+ - const: actions,owl-emac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ additionalItems: false
+ items:
+ - const: eth
+ - const: rmii
+
+ resets:
+ maxItems: 1
+
+ actions,ethcfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the device containing custom config.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - phy-mode
+ - phy-handle
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/actions,s500-cmu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/actions,s500-reset.h>
+
+ ethernet@b0310000 {
+ compatible = "actions,s500-emac", "actions,owl-emac";
+ reg = <0xb0310000 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
+ clock-names = "eth", "rmii";
+ resets = <&cmu RESET_ETHERNET>;
+ phy-mode = "rmii";
+ phy-handle = <&eth_phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@3 {
+ reg = <0x3>;
+ interrupt-parent = <&sirq>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+ };
diff --git a/dts/Bindings/net/brcm,bcm4908-enet.yaml b/dts/Bindings/net/brcm,bcm4908-enet.yaml
index 13c26f23a8..2f46e45dcd 100644
--- a/dts/Bindings/net/brcm,bcm4908-enet.yaml
+++ b/dts/Bindings/net/brcm,bcm4908-enet.yaml
@@ -22,10 +22,18 @@ properties:
maxItems: 1
interrupts:
- description: RX interrupt
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: RX interrupt
+ - description: TX interrupt
interrupt-names:
- const: rx
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: rx
+ - const: tx
required:
- reg
@@ -43,6 +51,7 @@ examples:
compatible = "brcm,bcm4908-enet";
reg = <0x80002000 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rx";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
};
diff --git a/dts/Bindings/net/brcm,bcm6368-mdio-mux.yaml b/dts/Bindings/net/brcm,bcm6368-mdio-mux.yaml
new file mode 100644
index 0000000000..2f34fda55f
--- /dev/null
+++ b/dts/Bindings/net/brcm,bcm6368-mdio-mux.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6368 MDIO bus multiplexer
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+
+description:
+ This MDIO bus multiplexer defines buses that could be internal as well as
+ external to SoCs. When child bus is selected, one needs to select these two
+ properties as well to generate desired MDIO transaction on appropriate bus.
+
+allOf:
+ - $ref: "mdio.yaml#"
+
+properties:
+ compatible:
+ const: brcm,bcm6368-mdio-mux
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+patternProperties:
+ '^mdio@[0-1]$':
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ required:
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio0: mdio@10e000b0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6368-mdio-mux";
+ reg = <0x10e000b0 0x6>;
+
+ mdio_int: mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ mdio_ext: mdio@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
diff --git a/dts/Bindings/net/broadcom-bluetooth.txt b/dts/Bindings/net/broadcom-bluetooth.txt
deleted file mode 100644
index a7d57ba5f2..0000000000
--- a/dts/Bindings/net/broadcom-bluetooth.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Broadcom Bluetooth Chips
----------------------
-
-This documents the binding structure and common properties for serial
-attached Broadcom devices.
-
-Serial attached Broadcom devices shall be a child node of the host UART
-device the slave device is attached to.
-
-Required properties:
-
- - compatible: should contain one of the following:
- * "brcm,bcm20702a1"
- * "brcm,bcm4329-bt"
- * "brcm,bcm4330-bt"
- * "brcm,bcm43438-bt"
- * "brcm,bcm4345c5"
- * "brcm,bcm43540-bt"
- * "brcm,bcm4335a0"
-
-Optional properties:
-
- - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml
- - shutdown-gpios: GPIO specifier, used to enable the BT module
- - device-wakeup-gpios: GPIO specifier, used to wakeup the controller
- - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor.
- deprecated, replaced by interrupts and
- "host-wakeup" interrupt-names
- - clocks: 1 or 2 clocks as defined in clock-names below, in that order
- - clock-names: names for clock inputs, matching the clocks given
- - "extclk": deprecated, replaced by "txco"
- - "txco": external reference clock (not a standalone crystal)
- - "lpo": external low power 32.768 kHz clock
- - vbat-supply: phandle to regulator supply for VBAT
- - vddio-supply: phandle to regulator supply for VDDIO
- - brcm,bt-pcm-int-params: configure PCM parameters via a 5-byte array
- - sco-routing: 0 = PCM, 1 = Transport, 2 = Codec, 3 = I2S
- - pcm-interface-rate: 128KBps, 256KBps, 512KBps, 1024KBps, 2048KBps
- - pcm-frame-type: short, long
- - pcm-sync-mode: slave, master
- - pcm-clock-mode: slave, master
- - interrupts: must be one, used to wakeup the host processor
- - interrupt-names: must be "host-wakeup"
-
-Example:
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <921600>;
- brcm,bt-pcm-int-params = [01 02 00 01 01];
- };
-};
diff --git a/dts/Bindings/net/broadcom-bluetooth.yaml b/dts/Bindings/net/broadcom-bluetooth.yaml
new file mode 100644
index 0000000000..fbdc2083be
--- /dev/null
+++ b/dts/Bindings/net/broadcom-bluetooth.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/broadcom-bluetooth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Bluetooth Chips
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+ This binding describes Broadcom UART-attached bluetooth chips.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm20702a1
+ - brcm,bcm4329-bt
+ - brcm,bcm4330-bt
+ - brcm,bcm4334-bt
+ - brcm,bcm43438-bt
+ - brcm,bcm4345c5
+ - brcm,bcm43540-bt
+ - brcm,bcm4335a0
+
+ shutdown-gpios:
+ maxItems: 1
+ description: GPIO specifier for the line BT_REG_ON used to
+ power on the BT module
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO specifier for the line BT_RST_N used to
+ reset the BT module. This should be marked as
+ GPIO_ACTIVE_LOW.
+
+ device-wakeup-gpios:
+ maxItems: 1
+ description: GPIO specifier for the line BT_WAKE used to
+ wakeup the controller. This is using the BT_GPIO_0
+ pin on the chip when in use.
+
+ host-wakeup-gpios:
+ maxItems: 1
+ deprecated: true
+ description: GPIO specifier for the line HOST_WAKE used
+ to wakeup the host processor. This is using he BT_GPIO_1
+ pin on the chip when in use. This is deprecated and replaced
+ by interrupts and "host-wakeup" interrupt-names
+
+ clocks:
+ maxItems: 2
+ description: 1 or 2 clocks as defined in clock-names below,
+ in that order
+
+ clock-names:
+ description: Names of the 1 to 2 supplied clocks
+ items:
+ - const: txco
+ - const: lpo
+ - const: extclk
+
+ vbat-supply:
+ description: phandle to regulator supply for VBAT
+
+ vddio-supply:
+ description: phandle to regulator supply for VDDIO
+
+ brcm,bt-pcm-int-params:
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ minItems: 5
+ maxItems: 5
+ description: |-
+ configure PCM parameters via a 5-byte array:
+ sco-routing: 0 = PCM, 1 = Transport, 2 = Codec, 3 = I2S
+ pcm-interface-rate: 128KBps, 256KBps, 512KBps, 1024KBps, 2048KBps
+ pcm-frame-type: short, long
+ pcm-sync-mode: slave, master
+ pcm-clock-mode: slave, master
+
+ interrupts:
+ items:
+ - description: Handle to the line HOST_WAKE used to wake
+ up the host processor. This uses the BT_GPIO_1 pin on
+ the chip when in use.
+
+ interrupt-names:
+ items:
+ - const: host-wakeup
+
+ max-speed: true
+ current-speed: true
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ uart {
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ max-speed = <921600>;
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ shutdown-gpios = <&gpio 30 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
diff --git a/dts/Bindings/net/can/fsl,flexcan.yaml b/dts/Bindings/net/can/fsl,flexcan.yaml
index fe6a949a2e..55bff1586b 100644
--- a/dts/Bindings/net/can/fsl,flexcan.yaml
+++ b/dts/Bindings/net/can/fsl,flexcan.yaml
@@ -57,7 +57,6 @@ properties:
- const: per
clock-frequency:
- $ref: /schemas/types.yaml#/definitions/uint32
description: |
The oscillator frequency driving the flexcan device, filled in by the
boot loader. This property should only be used the used operating system
diff --git a/dts/Bindings/net/can/rcar_can.txt b/dts/Bindings/net/can/rcar_can.txt
index 6a59563478..90ac4fef23 100644
--- a/dts/Bindings/net/can/rcar_can.txt
+++ b/dts/Bindings/net/can/rcar_can.txt
@@ -19,7 +19,8 @@ Required properties:
"renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC.
"renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
"renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
- "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC.
+ "renesas,can-r8a7796" if CAN controller is a part of R8A77960 SoC.
+ "renesas,can-r8a77961" if CAN controller is a part of R8A77961 SoC.
"renesas,can-r8a77965" if CAN controller is a part of R8A77965 SoC.
"renesas,can-r8a77990" if CAN controller is a part of R8A77990 SoC.
"renesas,can-r8a77995" if CAN controller is a part of R8A77995 SoC.
@@ -40,7 +41,7 @@ Required properties:
- pinctrl-names: must be "default".
Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795,
-R8A7796, R8A77965, R8A77990, and R8A77995:
+R8A77960, R8A77961, R8A77965, R8A77990, and R8A77995:
For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can
be used by both CAN and CAN FD controller at the same time. It needs to be
scaled to maximum frequency if any of these controllers use it. This is done
diff --git a/dts/Bindings/net/dsa/dsa.yaml b/dts/Bindings/net/dsa/dsa.yaml
index 8a3494db4d..16aa192c11 100644
--- a/dts/Bindings/net/dsa/dsa.yaml
+++ b/dts/Bindings/net/dsa/dsa.yaml
@@ -70,6 +70,15 @@ patternProperties:
device is what the switch port is connected to
$ref: /schemas/types.yaml#/definitions/phandle
+ dsa-tag-protocol:
+ description:
+ Instead of the default, the switch will use this tag protocol if
+ possible. Useful when a device supports multiple protcols and
+ the default is incompatible with the Ethernet device.
+ enum:
+ - dsa
+ - edsa
+
phy-handle: true
phy-mode: true
diff --git a/dts/Bindings/net/dsa/lantiq-gswip.txt b/dts/Bindings/net/dsa/lantiq-gswip.txt
index 886cbe8ffb..e3829d3e48 100644
--- a/dts/Bindings/net/dsa/lantiq-gswip.txt
+++ b/dts/Bindings/net/dsa/lantiq-gswip.txt
@@ -5,6 +5,10 @@ Required properties for GSWIP core:
- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
xRX200 SoC
+ "lantiq,xrx300-gswip" for the embedded GSWIP in the
+ xRX300 SoC
+ "lantiq,xrx330-gswip" for the embedded GSWIP in the
+ xRX330 SoC
- reg : memory range of the GSWIP core registers
: memory range of the GSWIP MDIO registers
: memory range of the GSWIP MII registers
diff --git a/dts/Bindings/net/dsa/microchip,ksz.yaml b/dts/Bindings/net/dsa/microchip,ksz.yaml
index 9f7d131bbc..84985f53bf 100644
--- a/dts/Bindings/net/dsa/microchip,ksz.yaml
+++ b/dts/Bindings/net/dsa/microchip,ksz.yaml
@@ -21,6 +21,8 @@ properties:
- microchip,ksz8765
- microchip,ksz8794
- microchip,ksz8795
+ - microchip,ksz8863
+ - microchip,ksz8873
- microchip,ksz9477
- microchip,ksz9897
- microchip,ksz9896
diff --git a/dts/Bindings/net/fsl-enetc.txt b/dts/Bindings/net/fsl-enetc.txt
index b7034ccbc1..9b9a3f197e 100644
--- a/dts/Bindings/net/fsl-enetc.txt
+++ b/dts/Bindings/net/fsl-enetc.txt
@@ -102,3 +102,18 @@ Example:
full-duplex;
};
};
+
+* Integrated Endpoint Register Block bindings
+
+Optionally, the fsl_enetc driver can probe on the Integrated Endpoint Register
+Block, which preconfigures the FIFO limits for the ENETC ports. This is a node
+with the following properties:
+
+- reg : Specifies the address in the SoC memory space.
+- compatible : Must be "fsl,ls1028a-enetc-ierb".
+
+Example:
+ ierb@1f0800000 {
+ compatible = "fsl,ls1028a-enetc-ierb";
+ reg = <0x01 0xf0800000 0x0 0x10000>;
+ };
diff --git a/dts/Bindings/net/idt,3243x-emac.yaml b/dts/Bindings/net/idt,3243x-emac.yaml
new file mode 100644
index 0000000000..11ffc306dd
--- /dev/null
+++ b/dts/Bindings/net/idt,3243x-emac.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/idt,3243x-emac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IDT 79rc3243x Ethernet controller
+
+description: Ethernet controller integrated into IDT 79RC3243x family SoCs
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+properties:
+ compatible:
+ const: idt,3243x-emac
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: emac
+ - const: dma_rx
+ - const: dma_tx
+
+ interrupts:
+ items:
+ - description: RX interrupt
+ - description: TX interrupt
+
+ interrupt-names:
+ items:
+ - const: rx
+ - const: tx
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: mdioclk
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+
+ ethernet@60000 {
+ compatible = "idt,3243x-emac";
+
+ reg = <0x60000 0x10000>,
+ <0x40000 0x14>,
+ <0x40014 0x14>;
+ reg-names = "emac", "dma_rx", "dma_tx";
+
+ interrupt-parent = <&rcpic3>;
+ interrupts = <0>, <1>;
+ interrupt-names = "rx", "tx";
+
+ clocks = <&iclk>;
+ clock-names = "mdioclk";
+ };
diff --git a/dts/Bindings/net/intel,ixp4xx-ethernet.yaml b/dts/Bindings/net/intel,ixp4xx-ethernet.yaml
new file mode 100644
index 0000000000..f2e91d1bf7
--- /dev/null
+++ b/dts/Bindings/net/intel,ixp4xx-ethernet.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx ethernet
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network
+ Processing Engine) and the IXP4xx Queue Manager to process
+ the ethernet frames. It can optionally contain an MDIO bus to
+ talk to PHYs.
+
+properties:
+ compatible:
+ const: intel,ixp4xx-ethernet
+
+ reg:
+ maxItems: 1
+ description: Ethernet MMIO address range
+
+ queue-rx:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the RX queue on the NPE
+
+ queue-txready:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the TX READY queue on the NPE
+
+ phy-mode: true
+
+ phy-handle: true
+
+ intel,npe-handle:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the NPE this ethernet instance is using
+ and the instance to use in the second cell
+
+ mdio:
+ type: object
+ $ref: "mdio.yaml#"
+ description: optional node for embedded MDIO controller
+
+required:
+ - compatible
+ - reg
+ - queue-rx
+ - queue-txready
+ - intel,npe-handle
+
+additionalProperties: false
+
+examples:
+ - |
+ npe: npe@c8006000 {
+ compatible = "intel,ixp4xx-network-processing-engine";
+ reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+ };
+
+ ethernet@c8009000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc8009000 0x1000>;
+ status = "disabled";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ intel,npe-handle = <&npe 1>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+
+ ethernet@c800c000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800c000 0x1000>;
+ status = "disabled";
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ intel,npe-handle = <&npe 2>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy2>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ };
+ };
diff --git a/dts/Bindings/net/mdio-gpio.txt b/dts/Bindings/net/mdio-gpio.txt
index 8dbcf8295c..4d91a36c5c 100644
--- a/dts/Bindings/net/mdio-gpio.txt
+++ b/dts/Bindings/net/mdio-gpio.txt
@@ -2,6 +2,7 @@ MDIO on GPIOs
Currently defined compatibles:
- virtual,gpio-mdio
+- microchip,mdio-smi0
MDC and MDIO lines connected to GPIO controllers are listed in the
gpios property as described in section VIII.1 in the following order:
diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml
index 8f86084bf1..7443490d4c 100644
--- a/dts/Bindings/net/qcom,ipa.yaml
+++ b/dts/Bindings/net/qcom,ipa.yaml
@@ -43,7 +43,12 @@ description:
properties:
compatible:
- const: "qcom,sdm845-ipa"
+ enum:
+ - qcom,sc7180-ipa
+ - qcom,sc7280-ipa
+ - qcom,sdm845-ipa
+ - qcom,sdx55-ipa
+ - qcom,sm8350-ipa
reg:
items:
@@ -120,6 +125,14 @@ properties:
the firmware passed to Trust Zone for authentication. Required
when Trust Zone (not the modem) performs early initialization.
+ firmware-name:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ If present, name (or relative path) of the file within the
+ firmware search path containing the firmware image used when
+ initializing IPA hardware. Optional, and only used when
+ Trust Zone performs early initialization.
+
required:
- compatible
- iommus
@@ -129,12 +142,23 @@ required:
- interconnects
- qcom,smem-states
+# Either modem-init is present, or memory-region must be present.
oneOf:
- required:
- modem-init
- required:
- memory-region
+# If memory-region is present, firmware-name may optionally be present.
+# But if modem-init is present, firmware-name must not be present.
+if:
+ required:
+ - modem-init
+then:
+ not:
+ required:
+ - firmware-name
+
additionalProperties: false
examples:
diff --git a/dts/Bindings/net/renesas,etheravb.yaml b/dts/Bindings/net/renesas,etheravb.yaml
index 91ba96d43c..005868f703 100644
--- a/dts/Bindings/net/renesas,etheravb.yaml
+++ b/dts/Bindings/net/renesas,etheravb.yaml
@@ -50,7 +50,16 @@ properties:
interrupt-names: true
clocks:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: AVB functional clock
+ - description: Optional TXC reference clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: fck
+ - const: refclk
iommus:
maxItems: 1
diff --git a/dts/Bindings/net/rockchip-dwmac.txt b/dts/Bindings/net/rockchip-dwmac.txt
deleted file mode 100644
index 3b71da7e87..0000000000
--- a/dts/Bindings/net/rockchip-dwmac.txt
+++ /dev/null
@@ -1,76 +0,0 @@
-Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
-
-The device node has following properties.
-
-Required properties:
- - compatible: should be "rockchip,<name>-gamc"
- "rockchip,px30-gmac": found on PX30 SoCs
- "rockchip,rk3128-gmac": found on RK312x SoCs
- "rockchip,rk3228-gmac": found on RK322x SoCs
- "rockchip,rk3288-gmac": found on RK3288 SoCs
- "rockchip,rk3328-gmac": found on RK3328 SoCs
- "rockchip,rk3366-gmac": found on RK3366 SoCs
- "rockchip,rk3368-gmac": found on RK3368 SoCs
- "rockchip,rk3399-gmac": found on RK3399 SoCs
- "rockchip,rv1108-gmac": found on RV1108 SoCs
- - reg: addresses and length of the register sets for the device.
- - interrupts: Should contain the GMAC interrupts.
- - interrupt-names: Should contain the interrupt names "macirq".
- - rockchip,grf: phandle to the syscon grf used to control speed and mode.
- - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
- <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
- <&cru SCLK_MAC_RX>: clock gate for RX
- <&cru SCLK_MAC_TX>: clock gate for TX
- <&cru SCLK_MACREF>: clock gate for RMII referce clock
- <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
- <&cru ACLK_GMAC>: AXI clock gate for GMAC
- <&cru PCLK_GMAC>: APB clock gate for GMAC
- - clock-names: One name for each entry in the clocks property.
- - phy-mode: See ethernet.txt file in the same directory.
- - pinctrl-names: Names corresponding to the numbered pinctrl states.
- - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
- - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
- is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
- PHY provides the reference clock(50MHz), "output" means GMAC provides the
- reference clock.
- - snps,reset-gpio gpio number for phy reset.
- - snps,reset-active-low boolean flag to indicate if phy reset is active low.
- - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
- - assigned-clock-parents = parent of main clock.
- can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
-
-Optional properties:
- - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
- - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
- - phy-supply: phandle to a regulator if the PHY needs one
-
-Example:
-
-gmac: ethernet@ff290000 {
- compatible = "rockchip,rk3288-gmac";
- reg = <0xff290000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- rockchip,grf = <&grf>;
- clocks = <&cru SCLK_MAC>,
- <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
- <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
- clock-names = "stmmaceth",
- "mac_clk_rx", "mac_clk_tx",
- "clk_mac_ref", "clk_mac_refout",
- "aclk_mac", "pclk_mac";
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
-
- clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
- snps,reset-active-low;
-
- assigned-clocks = <&cru SCLK_MAC>;
- assigned-clock-parents = <&ext_gmac>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-
-};
diff --git a/dts/Bindings/net/rockchip-dwmac.yaml b/dts/Bindings/net/rockchip-dwmac.yaml
new file mode 100644
index 0000000000..5acddb6171
--- /dev/null
+++ b/dts/Bindings/net/rockchip-dwmac.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Rockchip 10/100/1000 Ethernet driver(GMAC)
+
+maintainers:
+ - David Wu <david.wu@rock-chips.com>
+
+# We need a select here so we don't match all nodes with 'snps,dwmac'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,px30-gmac
+ - rockchip,rk3128-gmac
+ - rockchip,rk3228-gmac
+ - rockchip,rk3288-gmac
+ - rockchip,rk3328-gmac
+ - rockchip,rk3366-gmac
+ - rockchip,rk3368-gmac
+ - rockchip,rk3399-gmac
+ - rockchip,rv1108-gmac
+ required:
+ - compatible
+
+allOf:
+ - $ref: "snps,dwmac.yaml#"
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - rockchip,px30-gmac
+ - rockchip,rk3128-gmac
+ - rockchip,rk3228-gmac
+ - rockchip,rk3288-gmac
+ - rockchip,rk3328-gmac
+ - rockchip,rk3366-gmac
+ - rockchip,rk3368-gmac
+ - rockchip,rk3399-gmac
+ - rockchip,rv1108-gmac
+
+ clocks:
+ minItems: 5
+ maxItems: 8
+
+ clock-names:
+ contains:
+ enum:
+ - stmmaceth
+ - mac_clk_tx
+ - mac_clk_rx
+ - aclk_mac
+ - pclk_mac
+ - clk_mac_ref
+ - clk_mac_refout
+ - clk_mac_speed
+
+ clock_in_out:
+ description:
+ For RGMII, it must be "input", means main clock(125MHz)
+ is not sourced from SoC's PLL, but input from PHY.
+ For RMII, "input" means PHY provides the reference clock(50MHz),
+ "output" means GMAC provides the reference clock.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [input, output]
+
+ rockchip,grf:
+ description: The phandle of the syscon node for the general register file.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ tx_delay:
+ description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ rx_delay:
+ description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ phy-supply:
+ description: PHY regulator
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/rk3288-cru.h>
+
+ gmac: ethernet@ff290000 {
+ compatible = "rockchip,rk3288-gmac";
+ reg = <0xff290000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>,
+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+ <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth",
+ "mac_clk_rx", "mac_clk_tx",
+ "clk_mac_ref", "clk_mac_refout",
+ "aclk_mac", "pclk_mac";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+
+ rockchip,grf = <&grf>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ };
diff --git a/dts/Bindings/net/snps,dwmac.yaml b/dts/Bindings/net/snps,dwmac.yaml
index 0642b0f594..2edd8bea99 100644
--- a/dts/Bindings/net/snps,dwmac.yaml
+++ b/dts/Bindings/net/snps,dwmac.yaml
@@ -56,6 +56,15 @@ properties:
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac
+ - rockchip,px30-gmac
+ - rockchip,rk3128-gmac
+ - rockchip,rk3228-gmac
+ - rockchip,rk3288-gmac
+ - rockchip,rk3328-gmac
+ - rockchip,rk3366-gmac
+ - rockchip,rk3368-gmac
+ - rockchip,rk3399-gmac
+ - rockchip,rv1108-gmac
- snps,dwmac
- snps,dwmac-3.50a
- snps,dwmac-3.610
@@ -89,7 +98,7 @@ properties:
clocks:
minItems: 1
- maxItems: 5
+ maxItems: 8
additionalItems: true
items:
- description: GMAC main clock
@@ -101,7 +110,7 @@ properties:
clock-names:
minItems: 1
- maxItems: 5
+ maxItems: 8
additionalItems: true
contains:
enum:
diff --git a/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml b/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml
new file mode 100644
index 0000000000..c11f23b20c
--- /dev/null
+++ b/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM4329 family fullmac wireless SDIO devices
+
+maintainers:
+ - Arend van Spriel <arend@broadcom.com>
+
+description:
+ The Broadcom Single chip MAC part for the BCM4329 family and
+ later Cypress chips in the same family named CYW4373 and similar.
+ These chips also have a Bluetooth portion described in a separate
+ binding.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm43143-fmac
+ - brcm,bcm4341b0-fmac
+ - brcm,bcm4341b4-fmac
+ - brcm,bcm4341b5-fmac
+ - brcm,bcm4329-fmac
+ - brcm,bcm4330-fmac
+ - brcm,bcm4334-fmac
+ - brcm,bcm43340-fmac
+ - brcm,bcm4335-fmac
+ - brcm,bcm43362-fmac
+ - brcm,bcm4339-fmac
+ - brcm,bcm43430a0-fmac
+ - brcm,bcm43430a1-fmac
+ - brcm,bcm43455-fmac
+ - brcm,bcm43456-fmac
+ - brcm,bcm4354-fmac
+ - brcm,bcm4356-fmac
+ - brcm,bcm4359-fmac
+ - cypress,cyw4373-fmac
+ - cypress,cyw43012-fmac
+ - const: brcm,bcm4329-fmac
+ - const: brcm,bcm4329-fmac
+
+ reg:
+ description: SDIO function number for the device, for most cases
+ this will be 1.
+
+ interrupts:
+ maxItems: 1
+ description: Out-of-band (OOB) IRQ line for waking up the host
+ in response to WLAN activity. This corresponds to the HOST_WAKE
+ line into the chip.
+
+ interrupt-names:
+ description: Name for the OOB IRQ, this must be set to "host-wake".
+ const: host-wake
+
+ brcm,drive-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Drive strength used for the SDIO pins on the device in mA.
+ minimum: 0
+ maximum: 32
+
+ reset-gpios:
+ maxItems: 1
+ description: A GPIO line connected to the WL_RST line, if present
+ this shall be flagged as active low.
+
+ brcm,ccode-map:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Multiple strings for translating ISO3166 country code to
+ brcmfmac firmware country code and revision.
+ items:
+ pattern: '^[A-Z][A-Z]-[A-Z][0-9A-Z]-[0-9]+$'
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ mmc@80118000 {
+ compatible = "arm,pl18x", "ar