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authorSascha Hauer <s.hauer@pengutronix.de>2022-04-12 10:22:44 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-04-14 09:33:24 +0200
commitb01786baa849369ff2345c51e63857c952a01130 (patch)
tree43970a0ff46d32b8cad45b1dc3f3ca638e04fc5e /dts/Bindings
parent610797b376e65475f7aed1218a085ff8701da474 (diff)
downloadbarebox-b01786baa849369ff2345c51e63857c952a01130.tar.gz
barebox-b01786baa849369ff2345c51e63857c952a01130.tar.xz
dts: update to v5.18-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/Makefile49
-rw-r--r--dts/Bindings/arm/airoha.yaml28
-rw-r--r--dts/Bindings/arm/altera.yaml46
-rw-r--r--dts/Bindings/arm/amlogic.yaml12
-rw-r--r--dts/Bindings/arm/apple/apple,pmgr.yaml2
-rw-r--r--dts/Bindings/arm/arm,cci-400.yaml5
-rw-r--r--dts/Bindings/arm/atmel-at91.yaml9
-rw-r--r--dts/Bindings/arm/bcm/bcm2835.yaml1
-rw-r--r--dts/Bindings/arm/cpu-capacity.txt4
-rw-r--r--dts/Bindings/arm/cpus.yaml13
-rw-r--r--dts/Bindings/arm/freescale/fsl,scu.txt1
-rw-r--r--dts/Bindings/arm/fsl.yaml24
-rw-r--r--dts/Bindings/arm/fw-cfg.txt38
-rw-r--r--dts/Bindings/arm/intel,socfpga.yaml26
-rw-r--r--dts/Bindings/arm/linux,dummy-virt.yaml20
-rw-r--r--dts/Bindings/arm/mediatek.yaml4
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mmsys.yaml1
-rw-r--r--dts/Bindings/arm/msm/qcom,idle-state.txt2
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.yaml2
-rw-r--r--dts/Bindings/arm/mstar/mstar.yaml4
-rw-r--r--dts/Bindings/arm/npcm/nuvoton,gcr.yaml48
-rw-r--r--dts/Bindings/arm/pmu.yaml4
-rw-r--r--dts/Bindings/arm/psci.yaml2
-rw-r--r--dts/Bindings/arm/qcom.yaml23
-rw-r--r--dts/Bindings/arm/renesas.yaml9
-rw-r--r--dts/Bindings/arm/rockchip.yaml13
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.yaml2
-rw-r--r--dts/Bindings/arm/stm32/stm32.yaml6
-rw-r--r--dts/Bindings/arm/sunxi.yaml5
-rw-r--r--dts/Bindings/arm/tesla.yaml27
-rw-r--r--dts/Bindings/arm/ti/k3.yaml6
-rw-r--r--dts/Bindings/ata/ahci-platform.txt79
-rw-r--r--dts/Bindings/ata/ahci-platform.yaml189
-rw-r--r--dts/Bindings/ata/cortina,gemini-sata-bridge.txt55
-rw-r--r--dts/Bindings/ata/cortina,gemini-sata-bridge.yaml109
-rw-r--r--dts/Bindings/ata/sata_highbank.yaml3
-rw-r--r--dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml5
-rw-r--r--dts/Bindings/bus/nvidia,tegra210-aconnect.yaml1
-rw-r--r--dts/Bindings/clock/apple,nco.yaml62
-rw-r--r--dts/Bindings/clock/bitmain,bm1880-clk.yaml12
-rw-r--r--dts/Bindings/clock/cirrus,cs2000-cp.yaml91
-rw-r--r--dts/Bindings/clock/cs2000-cp.txt22
-rw-r--r--dts/Bindings/clock/idt,versaclock5.yaml7
-rw-r--r--dts/Bindings/clock/imx1-clock.yaml9
-rw-r--r--dts/Bindings/clock/imx21-clock.yaml9
-rw-r--r--dts/Bindings/clock/imx23-clock.yaml9
-rw-r--r--dts/Bindings/clock/imx25-clock.yaml8
-rw-r--r--dts/Bindings/clock/imx27-clock.yaml9
-rw-r--r--dts/Bindings/clock/imx28-clock.yaml9
-rw-r--r--dts/Bindings/clock/imx31-clock.yaml8
-rw-r--r--dts/Bindings/clock/imx35-clock.yaml8
-rw-r--r--dts/Bindings/clock/imx7ulp-pcc-clock.yaml11
-rw-r--r--dts/Bindings/clock/imx7ulp-scg-clock.yaml11
-rw-r--r--dts/Bindings/clock/imx8qxp-lpcg.yaml11
-rw-r--r--dts/Bindings/clock/imx93-clock.yaml62
-rw-r--r--dts/Bindings/clock/imxrt1050-clock.yaml59
-rw-r--r--dts/Bindings/clock/intc_stratix10.txt20
-rw-r--r--dts/Bindings/clock/intel,stratix10.yaml35
-rw-r--r--dts/Bindings/clock/marvell,armada-3700-uart-clock.yaml59
-rw-r--r--dts/Bindings/clock/mediatek,mt7621-sysc.yaml12
-rw-r--r--dts/Bindings/clock/microchip,mpfs.yaml58
-rw-r--r--dts/Bindings/clock/mstar,msc313-cpupll.yaml45
-rw-r--r--dts/Bindings/clock/nvidia,tegra124-car.yaml7
-rw-r--r--dts/Bindings/clock/nvidia,tegra20-car.yaml7
-rw-r--r--dts/Bindings/clock/qcom,a7pll.yaml2
-rw-r--r--dts/Bindings/clock/qcom,camcc.txt18
-rw-r--r--dts/Bindings/clock/qcom,dispcc-sm6125.yaml87
-rw-r--r--dts/Bindings/clock/qcom,dispcc-sm6350.yaml86
-rw-r--r--dts/Bindings/clock/qcom,gcc-apq8064.yaml29
-rw-r--r--dts/Bindings/clock/qcom,gcc-ipq8064.yaml76
-rw-r--r--dts/Bindings/clock/qcom,gcc-other.yaml70
-rw-r--r--dts/Bindings/clock/qcom,gcc.yaml59
-rw-r--r--dts/Bindings/clock/qcom,gpucc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,mmcc.yaml1
-rw-r--r--dts/Bindings/clock/qcom,qcm2290-dispcc.yaml87
-rw-r--r--dts/Bindings/clock/qcom,rpmhcc.yaml1
-rw-r--r--dts/Bindings/clock/qcom,sdm845-camcc.yaml65
-rw-r--r--dts/Bindings/clock/renesas,9series.yaml97
-rw-r--r--dts/Bindings/clock/renesas,cpg-div6-clock.yaml12
-rw-r--r--dts/Bindings/clock/renesas,rzg2l-cpg.yaml14
-rw-r--r--dts/Bindings/clock/starfive,jh7100-audclk.yaml57
-rw-r--r--dts/Bindings/clock/tesla,fsd-clock.yaml198
-rw-r--r--dts/Bindings/clock/ti/ti,clksel.yaml51
-rw-r--r--dts/Bindings/connector/usb-connector.yaml3
-rw-r--r--dts/Bindings/cpu/idle-states.yaml (renamed from dts/Bindings/arm/idle-states.yaml)308
-rw-r--r--dts/Bindings/cpufreq/cpufreq-qcom-hw.txt172
-rw-r--r--dts/Bindings/cpufreq/cpufreq-qcom-hw.yaml201
-rw-r--r--dts/Bindings/cpufreq/qcom-cpufreq-nvmem.yaml166
-rw-r--r--dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml66
-rw-r--r--dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml60
-rw-r--r--dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml64
-rw-r--r--dts/Bindings/crypto/atmel-crypto.txt68
-rw-r--r--dts/Bindings/crypto/intel,ixp4xx-crypto.yaml15
-rw-r--r--dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml2
-rw-r--r--dts/Bindings/display/brcm,bcm2711-hdmi.yaml3
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.yaml5
-rw-r--r--dts/Bindings/display/bridge/analogix,anx7625.yaml17
-rw-r--r--dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml82
-rw-r--r--dts/Bindings/display/bridge/lvds-codec.yaml3
-rw-r--r--dts/Bindings/display/bridge/renesas,lvds.yaml1
-rw-r--r--dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml5
-rw-r--r--dts/Bindings/display/bridge/ti,sn65dsi83.yaml5
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358768.yaml7
-rw-r--r--dts/Bindings/display/exynos/exynos-mic.txt51
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt60
-rw-r--r--dts/Bindings/display/exynos/exynos7-decon.txt65
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmi.txt64
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmiddc.txt15
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmiphy.txt15
-rw-r--r--dts/Bindings/display/exynos/exynos_mixer.txt26
-rw-r--r--dts/Bindings/display/exynos/samsung-fimd.txt107
-rw-r--r--dts/Bindings/display/lvds.yaml (renamed from dts/Bindings/display/panel/lvds.yaml)35
-rw-r--r--dts/Bindings/display/mediatek/mediatek,aal.yaml86
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ccorr.yaml85
-rw-r--r--dts/Bindings/display/mediatek/mediatek,color.yaml95
-rw-r--r--dts/Bindings/display/mediatek/mediatek,disp.txt219
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dither.yaml85
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.yaml3
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dsc.yaml80
-rw-r--r--dts/Bindings/display/mediatek/mediatek,gamma.yaml86
-rw-r--r--dts/Bindings/display/mediatek/mediatek,hdmi.yaml5
-rw-r--r--dts/Bindings/display/mediatek/mediatek,merge.yaml105
-rw-r--r--dts/Bindings/display/mediatek/mediatek,mutex.yaml92
-rw-r--r--dts/Bindings/display/mediatek/mediatek,od.yaml59
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml88
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ovl.yaml103
-rw-r--r--dts/Bindings/display/mediatek/mediatek,postmask.yaml78
-rw-r--r--dts/Bindings/display/mediatek/mediatek,rdma.yaml117
-rw-r--r--dts/Bindings/display/mediatek/mediatek,split.yaml65
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ufoe.yaml68
-rw-r--r--dts/Bindings/display/mediatek/mediatek,wdma.yaml86
-rw-r--r--dts/Bindings/display/msm/dp-controller.yaml1
-rw-r--r--dts/Bindings/display/msm/dpu-msm8998.yaml219
-rw-r--r--dts/Bindings/display/msm/dpu-qcm2290.yaml215
-rw-r--r--dts/Bindings/display/msm/dsi-controller-main.yaml5
-rw-r--r--dts/Bindings/display/msm/dsi-phy-10nm.yaml36
-rw-r--r--dts/Bindings/display/msm/gpu.yaml2
-rw-r--r--dts/Bindings/display/msm/mdp4.txt114
-rw-r--r--dts/Bindings/display/msm/mdp4.yaml124
-rw-r--r--dts/Bindings/display/panel/advantech,idk-1110wr.yaml19
-rw-r--r--dts/Bindings/display/panel/display-timings.yaml3
-rw-r--r--dts/Bindings/display/panel/innolux,ee101ia-01d.yaml23
-rw-r--r--dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml2
-rw-r--r--dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml19
-rw-r--r--dts/Bindings/display/panel/mitsubishi,aa121td01.yaml19
-rw-r--r--dts/Bindings/display/panel/panel-lvds.yaml57
-rw-r--r--dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml126
-rw-r--r--dts/Bindings/display/panel/panel-simple.yaml4
-rw-r--r--dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml19
-rw-r--r--dts/Bindings/display/panel/sony,acx424akp.yaml11
-rw-r--r--dts/Bindings/display/renesas,du.yaml10
-rw-r--r--dts/Bindings/display/rockchip/rockchip-drm.yaml2
-rw-r--r--dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml42
-rw-r--r--dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml227
-rw-r--r--dts/Bindings/display/samsung/samsung,exynos-mixer.yaml143
-rw-r--r--dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml148
-rw-r--r--dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml95
-rw-r--r--dts/Bindings/display/samsung/samsung,exynos7-decon.yaml120
-rw-r--r--dts/Bindings/display/samsung/samsung,fimd.yaml198
-rw-r--r--dts/Bindings/display/simple-framebuffer.yaml12
-rw-r--r--dts/Bindings/display/solomon,ssd1307fb.yaml1
-rw-r--r--dts/Bindings/display/sprd/sprd,display-subsystem.yaml2
-rw-r--r--dts/Bindings/display/ste,mcde.yaml4
-rw-r--r--dts/Bindings/display/ti/ti,am65x-dss.yaml3
-rw-r--r--dts/Bindings/dma/dma-router.yaml2
-rw-r--r--dts/Bindings/dma/mediatek,uart-dma.yaml122
-rw-r--r--dts/Bindings/dma/mtk-uart-apdma.txt56
-rw-r--r--dts/Bindings/dma/nvidia,tegra210-adma.yaml4
-rw-r--r--dts/Bindings/dma/renesas,rz-dmac.yaml4
-rw-r--r--dts/Bindings/dma/sifive,fu540-c000-pdma.yaml8
-rw-r--r--dts/Bindings/dma/st,stm32-dmamux.yaml2
-rw-r--r--dts/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml85
-rw-r--r--dts/Bindings/dma/xilinx/zynqmp_dma.txt26
-rw-r--r--dts/Bindings/dvfs/performance-domain.yaml15
-rw-r--r--dts/Bindings/example-schema.yaml14
-rw-r--r--dts/Bindings/extcon/maxim,max77843.yaml40
-rw-r--r--dts/Bindings/firmware/arm,scmi.yaml77
-rw-r--r--dts/Bindings/firmware/arm,scpi.yaml6
-rw-r--r--dts/Bindings/firmware/qemu,fw-cfg-mmio.yaml54
-rw-r--r--dts/Bindings/gnss/gnss-common.yaml55
-rw-r--r--dts/Bindings/gnss/gnss.txt37
-rw-r--r--dts/Bindings/gnss/sirfstar.txt46
-rw-r--r--dts/Bindings/gnss/sirfstar.yaml76
-rw-r--r--dts/Bindings/gnss/u-blox,neo-6m.yaml14
-rw-r--r--dts/Bindings/gpio/airoha,en7523-gpio.yaml66
-rw-r--r--dts/Bindings/gpio/delta,tn48m-gpio.yaml39
-rw-r--r--dts/Bindings/gpio/faraday,ftgpio010.txt27
-rw-r--r--dts/Bindings/gpio/faraday,ftgpio010.yaml65
-rw-r--r--dts/Bindings/gpio/gpio-pca95xx.yaml8
-rw-r--r--dts/Bindings/gpio/gpio-vf610.yaml4
-rw-r--r--dts/Bindings/gpio/gpio.txt2
-rw-r--r--dts/Bindings/gpio/microchip,mpfs-gpio.yaml79
-rw-r--r--dts/Bindings/gpio/sifive,gpio.yaml2
-rw-r--r--dts/Bindings/gpu/arm,mali-bifrost.yaml15
-rw-r--r--dts/Bindings/hwlock/ti,omap-hwspinlock.yaml33
-rw-r--r--dts/Bindings/hwmon/adi,adm1275.yaml68
-rw-r--r--dts/Bindings/hwmon/national,lm90.yaml4
-rw-r--r--dts/Bindings/hwmon/ti,tmp464.yaml114
-rw-r--r--dts/Bindings/i2c/atmel,at91sam-i2c.yaml146
-rw-r--r--dts/Bindings/i2c/i2c-at91.txt82
-rw-r--r--dts/Bindings/i2c/i2c-imx.yaml7
-rw-r--r--dts/Bindings/i2c/i2c-mpc.yaml2
-rw-r--r--dts/Bindings/i2c/i2c-mt65xx.txt2
-rw-r--r--dts/Bindings/i2c/i2c-qcom-cci.txt4
-rw-r--r--dts/Bindings/i2c/i2c-s3c2410.txt58
-rw-r--r--dts/Bindings/i2c/i2c.txt4
-rw-r--r--dts/Bindings/i2c/ingenic,i2c.yaml4
-rw-r--r--dts/Bindings/i2c/microchip,corei2c.yaml56
-rw-r--r--dts/Bindings/i2c/renesas,rcar-i2c.yaml6
-rw-r--r--dts/Bindings/i2c/renesas,riic.yaml2
-rw-r--r--dts/Bindings/i2c/samsung,s3c2410-i2c.yaml164
-rw-r--r--dts/Bindings/i2c/st,stm32-i2c.yaml24
-rw-r--r--dts/Bindings/iio/accel/adi,adxl367.yaml79
-rw-r--r--dts/Bindings/iio/adc/adi,ad7280a.yaml77
-rw-r--r--dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml2
-rw-r--r--dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml1
-rw-r--r--dts/Bindings/iio/adc/microchip,mcp3201.yaml2
-rw-r--r--dts/Bindings/iio/adc/qcom,spmi-iadc.yaml2
-rw-r--r--dts/Bindings/iio/adc/ti,palmas-gpadc.yaml6
-rw-r--r--dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml8
-rw-r--r--dts/Bindings/iio/afe/temperature-sense-rtd.yaml101
-rw-r--r--dts/Bindings/iio/afe/temperature-transducer.yaml114
-rw-r--r--dts/Bindings/iio/amplifiers/adi,ada4250.yaml50
-rw-r--r--dts/Bindings/iio/dac/adi,ltc2688.yaml146
-rw-r--r--dts/Bindings/iio/frequency/adi,admv1014.yaml134
-rw-r--r--dts/Bindings/iio/frequency/adi,admv4420.yaml55
-rw-r--r--dts/Bindings/iio/proximity/semtech,sx9324.yaml161
-rw-r--r--dts/Bindings/iio/proximity/semtech,sx9360.yaml89
-rw-r--r--dts/Bindings/iio/st,st-sensors.yaml3
-rw-r--r--dts/Bindings/input/adc-joystick.yaml9
-rw-r--r--dts/Bindings/input/mediatek,mt6779-keypad.yaml77
-rw-r--r--dts/Bindings/input/mtk-pmic-keys.txt5
-rw-r--r--dts/Bindings/input/touchscreen/imagis,ist3038c.yaml74
-rw-r--r--dts/Bindings/interconnect/qcom,rpm.yaml33
-rw-r--r--dts/Bindings/interconnect/qcom,rpmh.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/andestech,ativic32.txt19
-rw-r--r--dts/Bindings/interrupt-controller/apple,aic.yaml31
-rw-r--r--dts/Bindings/interrupt-controller/apple,aic2.yaml98
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.yaml6
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.yaml1
-rw-r--r--dts/Bindings/interrupt-controller/qcom,mpm.yaml96
-rw-r--r--dts/Bindings/interrupt-controller/st,stm32-exti.yaml1
-rw-r--r--dts/Bindings/interrupt-controller/ti,sci-inta.yaml2
-rw-r--r--dts/Bindings/iommu/mediatek,iommu.yaml6
-rw-r--r--dts/Bindings/iommu/renesas,ipmmu-vmsa.yaml10
-rw-r--r--dts/Bindings/ipmi/ipmi-ipmb.yaml8
-rw-r--r--dts/Bindings/leds/backlight/led-backlight.yaml2
-rw-r--r--dts/Bindings/leds/backlight/qcom-wled.yaml1
-rw-r--r--dts/Bindings/leds/common.yaml9
-rw-r--r--dts/Bindings/leds/cznic,turris-omnia-leds.yaml3
-rw-r--r--dts/Bindings/leds/leds-lp50xx.yaml3
-rw-r--r--dts/Bindings/leds/maxim,max77693.yaml105
-rw-r--r--dts/Bindings/mailbox/fsl,mu.yaml35
-rw-r--r--dts/Bindings/mailbox/microchip,mpfs-mailbox.yaml (renamed from dts/Bindings/mailbox/microchip,polarfire-soc-mailbox.yaml)6
-rw-r--r--dts/Bindings/mailbox/mtk,adsp-mbox.yaml50
-rw-r--r--dts/Bindings/mailbox/mtk-gce.txt8
-rw-r--r--dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml1
-rw-r--r--dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml4
-rw-r--r--dts/Bindings/media/amphion,vpu.yaml180
-rw-r--r--dts/Bindings/media/i2c/hynix,hi846.yaml6
-rw-r--r--dts/Bindings/media/i2c/isil,isl79987.yaml113
-rw-r--r--dts/Bindings/media/i2c/maxim,max9286.yaml275
-rw-r--r--dts/Bindings/media/mediatek,vcodec-decoder.yaml169
-rw-r--r--dts/Bindings/media/mediatek,vcodec-encoder.yaml179
-rw-r--r--dts/Bindings/media/mediatek,vcodec-subdev-decoder.yaml271
-rw-r--r--dts/Bindings/media/mediatek-jpeg-decoder.txt38
-rw-r--r--dts/Bindings/media/mediatek-jpeg-decoder.yaml80
-rw-r--r--dts/Bindings/media/mediatek-jpeg-encoder.txt35
-rw-r--r--dts/Bindings/media/mediatek-jpeg-encoder.yaml72
-rw-r--r--dts/Bindings/media/mediatek-mdp.txt8
-rw-r--r--dts/Bindings/media/mediatek-vcodec.txt131
-rw-r--r--dts/Bindings/media/microchip,csi2dc.yaml197
-rw-r--r--dts/Bindings/media/nxp,imx-mipi-csi2.yaml (renamed from dts/Bindings/media/nxp,imx7-mipi-csi2.yaml)2
-rw-r--r--dts/Bindings/media/nxp,imx7-csi.yaml1
-rw-r--r--dts/Bindings/media/nxp,imx8mq-mipi-csi2.yaml10
-rw-r--r--dts/Bindings/media/nxp,imx8mq-vpu.yaml68
-rw-r--r--dts/Bindings/media/qcom,msm8916-camss.yaml10
-rw-r--r--dts/Bindings/media/qcom,msm8996-camss.yaml20
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-rw-r--r--dts/Bindings/sound/nvidia,tegra210-amx.yaml3
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-dmic.yaml1
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-i2s.yaml1
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-mixer.yaml1
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-mvc.yaml1
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-sfc.yaml1
-rw-r--r--dts/Bindings/sound/nvidia,tegra30-hda.yaml3
-rw-r--r--dts/Bindings/sound/qcom,lpass-cpu.yaml75
-rw-r--r--dts/Bindings/sound/qcom,lpass-rx-macro.yaml8
-rw-r--r--dts/Bindings/sound/qcom,lpass-tx-macro.yaml8
-rw-r--r--dts/Bindings/sound/qcom,lpass-va-macro.yaml8
-rw-r--r--dts/Bindings/sound/qcom,sm8250.yaml10
-rw-r--r--dts/Bindings/sound/qcom,wcd938x.yaml4
-rw-r--r--dts/Bindings/sound/realtek,rt5682s.yaml8
-rw-r--r--dts/Bindings/sound/renesas,rsnd.yaml16
-rw-r--r--dts/Bindings/sound/renesas,rz-ssi.yaml3
-rw-r--r--dts/Bindings/sound/samsung,aries-wm8994.yaml7
-rw-r--r--dts/Bindings/sound/samsung,arndale.yaml45
-rw-r--r--dts/Bindings/sound/samsung,midas-audio.yaml2
-rw-r--r--dts/Bindings/sound/samsung,odroid.yaml9
-rw-r--r--dts/Bindings/sound/samsung,smdk-wm8994.txt14
-rw-r--r--dts/Bindings/sound/samsung,smdk5250.yaml38
-rw-r--r--dts/Bindings/sound/samsung,snow.yaml74
-rw-r--r--dts/Bindings/sound/samsung,tm2-audio.txt42
-rw-r--r--dts/Bindings/sound/samsung,tm2.yaml80
-rw-r--r--dts/Bindings/sound/simple-card.yaml53
-rw-r--r--dts/Bindings/sound/snow.txt31
-rw-r--r--dts/Bindings/sound/sound-dai.yaml20
-rw-r--r--dts/Bindings/sound/st,stm32-sai.yaml11
-rw-r--r--dts/Bindings/sound/tas5805m.yaml56
-rw-r--r--dts/Bindings/sound/tlv320adcx140.yaml13
-rw-r--r--dts/Bindings/sound/tlv320aic31xx.txt2
-rw-r--r--dts/Bindings/soundwire/qcom,sdw.txt14
-rw-r--r--dts/Bindings/spi/mediatek,spi-mt65xx.yaml107
-rw-r--r--dts/Bindings/spi/mediatek,spi-mtk-nor.yaml6
-rw-r--r--dts/Bindings/spi/mediatek,spi-slave-mt27xx.yaml58
-rw-r--r--dts/Bindings/spi/microchip,mpfs-spi.yaml52
-rw-r--r--dts/Bindings/spi/mxicy,mx25f0a-spi.yaml65
-rw-r--r--dts/Bindings/spi/nvidia,tegra210-quad.yaml3
-rw-r--r--dts/Bindings/spi/qcom,spi-qcom-qspi.yaml2
-rw-r--r--dts/Bindings/spi/renesas,rspi.yaml4
-rw-r--r--dts/Bindings/spi/samsung,spi-peripheral-props.yaml33
-rw-r--r--dts/Bindings/spi/samsung,spi.yaml188
-rw-r--r--dts/Bindings/spi/spi-controller.yaml11
-rw-r--r--dts/Bindings/spi/spi-mt65xx.txt68
-rw-r--r--dts/Bindings/spi/spi-mxic.txt34
-rw-r--r--dts/Bindings/spi/spi-nxp-fspi.yaml3
-rw-r--r--dts/Bindings/spi/spi-peripheral-props.yaml26
-rw-r--r--dts/Bindings/spi/spi-pl022.yaml4
-rw-r--r--dts/Bindings/spi/spi-samsung.txt122
-rw-r--r--dts/Bindings/spi/spi-slave-mt27xx.txt33
-rw-r--r--dts/Bindings/spi/spi-sunplus-sp7021.yaml78
-rw-r--r--dts/Bindings/spi/sprd,spi-adi.yaml2
-rw-r--r--dts/Bindings/staging/net/wireless/silabs,wfx.yaml137
-rw-r--r--dts/Bindings/thermal/exynos-thermal.txt106
-rw-r--r--dts/Bindings/thermal/qcom-lmh.yaml1
-rw-r--r--dts/Bindings/thermal/qcom-tsens.yaml1
-rw-r--r--dts/Bindings/thermal/samsung,exynos-thermal.yaml184
-rw-r--r--dts/Bindings/thermal/thermal-cooling-devices.yaml6
-rw-r--r--dts/Bindings/thermal/thermal-idle.yaml8
-rw-r--r--dts/Bindings/timer/andestech,atcpit100-timer.txt33
-rw-r--r--dts/Bindings/timer/arm,armv7m-systick.txt26
-rw-r--r--dts/Bindings/timer/arm,armv7m-systick.yaml54
-rw-r--r--dts/Bindings/timer/ingenic,tcu.yaml1
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt1
-rw-r--r--dts/Bindings/timer/nuvoton,npcm7xx-timer.txt21
-rw-r--r--dts/Bindings/timer/nuvoton,npcm7xx-timer.yaml46
-rw-r--r--dts/Bindings/timer/nvidia,tegra-timer.yaml150
-rw-r--r--dts/Bindings/timer/nvidia,tegra20-timer.txt24
-rw-r--r--dts/Bindings/timer/nvidia,tegra210-timer.txt36
-rw-r--r--dts/Bindings/timer/nvidia,tegra30-timer.txt28
-rw-r--r--dts/Bindings/timer/renesas,ostm.yaml2
-rw-r--r--dts/Bindings/timer/sifive,clint.yaml9
-rw-r--r--dts/Bindings/trivial-devices.yaml25
-rw-r--r--dts/Bindings/ufs/cdns,ufshc.txt32
-rw-r--r--dts/Bindings/ufs/cdns,ufshc.yaml68
-rw-r--r--dts/Bindings/ufs/hisilicon,ufs.yaml90
-rw-r--r--dts/Bindings/ufs/mediatek,ufs.yaml67
-rw-r--r--dts/Bindings/ufs/qcom,ufs.yaml244
-rw-r--r--dts/Bindings/ufs/samsung,exynos-ufs.yaml13
-rw-r--r--dts/Bindings/ufs/snps,tc-dwc-g210.yaml51
-rw-r--r--dts/Bindings/ufs/tc-dwc-g210-pltfrm.txt26
-rw-r--r--dts/Bindings/ufs/ti,j721e-ufs.yaml7
-rw-r--r--dts/Bindings/ufs/ufs-common.yaml82
-rw-r--r--dts/Bindings/ufs/ufs-hisi.txt42
-rw-r--r--dts/Bindings/ufs/ufs-mediatek.txt45
-rw-r--r--dts/Bindings/ufs/ufs-qcom.txt63
-rw-r--r--dts/Bindings/ufs/ufshcd-pltfrm.txt90
-rw-r--r--dts/Bindings/usb/dwc2.yaml8
-rw-r--r--dts/Bindings/usb/dwc3-cavium.txt2
-rw-r--r--dts/Bindings/usb/exynos-usb.txt115
-rw-r--r--dts/Bindings/usb/fsl,imx8mp-dwc3.yaml31
-rw-r--r--dts/Bindings/usb/mediatek,mtk-xhci.yaml7
-rw-r--r--dts/Bindings/usb/mediatek,mtu3.yaml4
-rw-r--r--dts/Bindings/usb/mediatek,musb.yaml2
-rw-r--r--dts/Bindings/usb/microchip,mpfs-musb.yaml59
-rw-r--r--dts/Bindings/usb/nvidia,tegra-xudc.yaml2
-rw-r--r--dts/Bindings/usb/qcom,dwc3.yaml1
-rw-r--r--dts/Bindings/usb/renesas,usbhs.yaml5
-rw-r--r--dts/Bindings/usb/richtek,rt1719.yaml85
-rw-r--r--dts/Bindings/usb/rockchip,dwc3.yaml2
-rw-r--r--dts/Bindings/usb/samsung,exynos-dwc3.yaml129
-rw-r--r--dts/Bindings/usb/samsung,exynos-usb2.yaml117
-rw-r--r--dts/Bindings/usb/snps,dwc3.yaml13
-rw-r--r--dts/Bindings/usb/st,stusb160x.yaml4
-rw-r--r--dts/Bindings/usb/ti,keystone-dwc3.yaml2
-rw-r--r--dts/Bindings/usb/usb-hcd.yaml2
-rw-r--r--dts/Bindings/usb/willsemi,wusb3801.yaml75
-rw-r--r--dts/Bindings/vendor-prefixes.yaml45
-rw-r--r--dts/Bindings/virtio/mmio.yaml2
-rw-r--r--dts/Bindings/watchdog/fsl-imx7ulp-wdt.yaml8
-rw-r--r--dts/Bindings/watchdog/mtk-wdt.txt1
-rw-r--r--dts/Bindings/watchdog/renesas,wdt.yaml5
-rw-r--r--dts/Bindings/writing-schema.rst28
675 files changed, 25029 insertions, 8037 deletions
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile
index 41c555181b..c9953f86b1 100644
--- a/dts/Bindings/Makefile
+++ b/dts/Bindings/Makefile
@@ -3,9 +3,10 @@ DT_DOC_CHECKER ?= dt-doc-validate
DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
-DT_SCHEMA_LINT = $(shell which yamllint)
+DT_SCHEMA_LINT = $(shell which yamllint || \
+ echo "warning: python package 'yamllint' not installed, skipping" >&2)
-DT_SCHEMA_MIN_VERSION = 2021.2.1
+DT_SCHEMA_MIN_VERSION = 2022.3
PHONY += check_dtschema_version
check_dtschema_version:
@@ -24,18 +25,11 @@ quiet_cmd_extract_ex = DTEX $@
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
$(call if_changed,extract_ex)
-# Use full schemas when checking %.example.dts
-DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
-
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
- -name 'processed-schema*' ! \
- -name '*.example.dt.yaml' \)
+ -name 'processed-schema*' \)
-ifeq ($(DT_SCHEMA_FILES),)
-find_cmd = $(find_all_cmd)
-else
-find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES))
-endif
+find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)"
+CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
@@ -72,35 +66,14 @@ override DTC_FLAGS := \
# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=
-$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
+$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)
-ifeq ($(DT_SCHEMA_FILES),)
-
-# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
-# Just copy processed-schema-examples.json
-
-$(obj)/processed-schema.json: $(obj)/processed-schema-examples.json FORCE
- $(call if_changed,copy)
-
-DT_SCHEMA_FILES = $(DT_DOCS)
-
-else
-
-# If DT_SCHEMA_FILES is specified, use it for processed-schema.json
-
-$(obj)/processed-schema.json: DT_MK_SCHEMA_FLAGS := -u
-$(obj)/processed-schema.json: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
- $(call if_changed,mk_schema)
-
-endif
-
-always-$(CHECK_DT_BINDING) += processed-schema-examples.json
-always-$(CHECK_DTBS) += processed-schema.json
-always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
-always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
+always-y += processed-schema.json
+always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dts, $(CHK_DT_DOCS))
+always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, $(CHK_DT_DOCS))
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
# build artifacts here before they are processed by scripts/Makefile.clean
clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
- -name '*.example.dt.yaml' \) -delete 2>/dev/null)
+ -name '*.example.dtb' \) -delete 2>/dev/null)
diff --git a/dts/Bindings/arm/airoha.yaml b/dts/Bindings/arm/airoha.yaml
new file mode 100644
index 0000000000..fc19b1a6f3
--- /dev/null
+++ b/dts/Bindings/arm/airoha.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/airoha.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha SoC based Platforms Device Tree Bindings
+
+maintainers:
+ - Felix Fietkau <nbd@nbd.name>
+ - John Crispin <john@phrozen.org>
+
+description:
+ Boards with an Airoha SoC shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - airoha,en7523-evb
+ - const: airoha,en7523
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/altera.yaml b/dts/Bindings/arm/altera.yaml
index c15c92fdf2..5e2017c0a0 100644
--- a/dts/Bindings/arm/altera.yaml
+++ b/dts/Bindings/arm/altera.yaml
@@ -13,12 +13,46 @@ properties:
$nodename:
const: "/"
compatible:
- items:
- - enum:
- - altr,socfpga-cyclone5
- - altr,socfpga-arria5
- - altr,socfpga-arria10
- - const: altr,socfpga
+ oneOf:
+ - description: Arria 5 boards
+ items:
+ - enum:
+ - altr,socfpga-arria5-socdk
+ - const: altr,socfpga-arria5
+ - const: altr,socfpga
+
+ - description: Arria 10 boards
+ items:
+ - enum:
+ - altr,socfpga-arria10-socdk
+ - enclustra,mercury-aa1
+ - const: altr,socfpga-arria10
+ - const: altr,socfpga
+
+ - description: Cyclone 5 boards
+ items:
+ - enum:
+ - altr,socfpga-cyclone5-socdk
+ - denx,mcvevk
+ - ebv,socrates
+ - macnica,sodia
+ - novtech,chameleon96
+ - samtec,vining
+ - terasic,de0-atlas
+ - terasic,socfpga-cyclone5-sockit
+ - const: altr,socfpga-cyclone5
+ - const: altr,socfpga
+
+ - description: Stratix 10 boards
+ items:
+ - enum:
+ - altr,socfpga-stratix10-socdk
+ - const: altr,socfpga-stratix10
+
+ - description: SoCFPGA VT
+ items:
+ - const: altr,socfpga-vt
+ - const: altr,socfpga
additionalProperties: true
diff --git a/dts/Bindings/arm/amlogic.yaml b/dts/Bindings/arm/amlogic.yaml
index 36081734f7..61a6cabb37 100644
--- a/dts/Bindings/arm/amlogic.yaml
+++ b/dts/Bindings/arm/amlogic.yaml
@@ -108,6 +108,7 @@ properties:
- amlogic,p230
- amlogic,p231
- libretech,aml-s905d-pc
+ - osmc,vero4k-plus
- phicomm,n1
- smartlabs,sml5442tw
- videostrong,gxl-kii-pro
@@ -170,9 +171,14 @@ properties:
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
+ - amediatech,x96-air
+ - amediatech,x96-air-gbit
- bananapi,bpi-m5
+ - cyx,a95xf3-air
+ - cyx,a95xf3-air-gbit
- hardkernel,odroid-c4
- hardkernel,odroid-hc4
+ - haochuangyi,h96-max
- khadas,vim3l
- seirobotics,sei610
- const: amlogic,sm1
@@ -183,6 +189,12 @@ properties:
- amlogic,ad401
- const: amlogic,a1
+ - description: Boards with the Amlogic Meson S4 S805X2 SoC
+ items:
+ - enum:
+ - amlogic,aq222
+ - const: amlogic,s4
+
additionalProperties: true
...
diff --git a/dts/Bindings/arm/apple/apple,pmgr.yaml b/dts/Bindings/arm/apple/apple,pmgr.yaml
index b6b5d3a912..0dc957a56d 100644
--- a/dts/Bindings/arm/apple/apple,pmgr.yaml
+++ b/dts/Bindings/arm/apple/apple,pmgr.yaml
@@ -42,7 +42,7 @@ patternProperties:
description:
The individual power management domains within this controller
type: object
- $ref: /power/apple,pmgr-pwrstate.yaml#
+ $ref: /schemas/power/apple,pmgr-pwrstate.yaml#
required:
- compatible
diff --git a/dts/Bindings/arm/arm,cci-400.yaml b/dts/Bindings/arm/arm,cci-400.yaml
index f8530a5086..1706134b75 100644
--- a/dts/Bindings/arm/arm,cci-400.yaml
+++ b/dts/Bindings/arm/arm,cci-400.yaml
@@ -119,6 +119,11 @@ examples:
arm,hbi = <0x249>;
interrupt-parent = <&gic>;
+ gic: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
/*
* This CCI node corresponds to a CCI component whose control
* registers sits at address 0x000000002c090000.
diff --git a/dts/Bindings/arm/atmel-at91.yaml b/dts/Bindings/arm/atmel-at91.yaml
index ff91df04f9..4e495e0326 100644
--- a/dts/Bindings/arm/atmel-at91.yaml
+++ b/dts/Bindings/arm/atmel-at91.yaml
@@ -175,6 +175,15 @@ properties:
- const: microchip,lan9668
- const: microchip,lan966
+ - description: Kontron KSwitch D10 MMT series
+ items:
+ - enum:
+ - kontron,kswitch-d10-mmt-8g
+ - kontron,kswitch-d10-mmt-6g-2gs
+ - const: kontron,s1921
+ - const: microchip,lan9668
+ - const: microchip,lan966
+
- items:
- enum:
- atmel,sams70j19
diff --git a/dts/Bindings/arm/bcm/bcm2835.yaml b/dts/Bindings/arm/bcm/bcm2835.yaml
index 5dc48241ef..8051a75c2c 100644
--- a/dts/Bindings/arm/bcm/bcm2835.yaml
+++ b/dts/Bindings/arm/bcm/bcm2835.yaml
@@ -51,6 +51,7 @@ properties:
- raspberrypi,3-model-b-plus
- raspberrypi,3-compute-module
- raspberrypi,3-compute-module-lite
+ - raspberrypi,model-zero-2-w
- const: brcm,bcm2837
additionalProperties: true
diff --git a/dts/Bindings/arm/cpu-capacity.txt b/dts/Bindings/arm/cpu-capacity.txt
index 380e21c5fc..cc5e190390 100644
--- a/dts/Bindings/arm/cpu-capacity.txt
+++ b/dts/Bindings/arm/cpu-capacity.txt
@@ -62,8 +62,8 @@ Example 1 (ARM 64-bit, 6-cpu system, two clusters):
The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
are 1024 and 578 for cluster0 and cluster1. Further normalization
is done by the operating system based on cluster0@max-freq=1100 and
-custer1@max-freq=850, final capacities are 1024 for cluster0 and
-446 for cluster1 (576*850/1100).
+cluster1@max-freq=850, final capacities are 1024 for cluster0 and
+446 for cluster1 (578*850/1100).
cpus {
#address-cells = <2>;
diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml
index 0dcebc48ea..ed04650291 100644
--- a/dts/Bindings/arm/cpus.yaml
+++ b/dts/Bindings/arm/cpus.yaml
@@ -173,6 +173,7 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
+ - qcom,kryo250
- qcom,kryo260
- qcom,kryo280
- qcom,kryo385
@@ -232,17 +233,19 @@ properties:
- ti,am4372
cpu-release-addr:
- $ref: '/schemas/types.yaml#/definitions/uint64'
-
+ oneOf:
+ - $ref: '/schemas/types.yaml#/definitions/uint32'
+ - $ref: '/schemas/types.yaml#/definitions/uint64'
description:
+ The DT specification defines this as 64-bit always, but some 32-bit Arm
+ systems have used a 32-bit value which must be supported.
Required for systems that have an "enable-method"
property value of "spin-table".
- On ARM v8 64-bit systems must be a two cell
- property identifying a 64-bit zero-initialised
- memory location.
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
+ items:
+ maxItems: 1
description: |
List of phandles to idle state nodes supported
by this cpu (see ./idle-states.yaml).
diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt
index fd00617124..a87ec15e28 100644
--- a/dts/Bindings/arm/freescale/fsl,scu.txt
+++ b/dts/Bindings/arm/freescale/fsl,scu.txt
@@ -86,6 +86,7 @@ This binding uses the common clock binding[1].
Required properties:
- compatible: Should be one of:
+ "fsl,imx8dxl-clk"
"fsl,imx8qm-clk"
"fsl,imx8qxp-clk"
followed by "fsl,scu-clk"
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
index 97f6eebad7..08bdd30e51 100644
--- a/dts/Bindings/arm/fsl.yaml
+++ b/dts/Bindings/arm/fsl.yaml
@@ -762,6 +762,7 @@ properties:
- enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
+ - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
@@ -769,8 +770,13 @@ properties:
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
+ - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
+ - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
+ - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
+ - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
+ - prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
- description: Engicam i.Core MX8M Mini SoM based boards
@@ -787,6 +793,24 @@ properties:
- const: kontron,imx8mm-n801x-som
- const: fsl,imx8mm
+ - description: Toradex Boards with Verdin iMX8M Mini Modules
+ items:
+ - enum:
+ - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
+ - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
+ - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
+ - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
+ - const: fsl,imx8mm
+
+ - description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules
+ items:
+ - enum:
+ - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
+ - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
+ - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
+ - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
+ - const: fsl,imx8mm
+
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
diff --git a/dts/Bindings/arm/fw-cfg.txt b/dts/Bindings/arm/fw-cfg.txt
deleted file mode 100644
index fd54e1db21..0000000000
--- a/dts/Bindings/arm/fw-cfg.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* QEMU Firmware Configuration bindings for ARM
-
-QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
-provide the following Firmware Configuration interface on the "virt" machine
-type:
-
-- A write-only, 16-bit wide selector (or control) register,
-- a read-write, 64-bit wide data register.
-
-QEMU exposes the control and data register to ARM guests as memory mapped
-registers; their location is communicated to the guest's UEFI firmware in the
-DTB that QEMU places at the bottom of the guest's DRAM.
-
-The authoritative guest-side hardware interface documentation to the fw_cfg
-device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
-
-
-Required properties:
-
-- compatible: "qemu,fw-cfg-mmio".
-
-- reg: the MMIO region used by the device.
- * Bytes 0x0 to 0x7 cover the data register.
- * Bytes 0x8 to 0x9 cover the selector register.
- * Further registers may be appended to the region in case of future interface
- revisions / feature bits.
-
-Example:
-
-/ {
- #size-cells = <0x2>;
- #address-cells = <0x2>;
-
- fw-cfg@9020000 {
- compatible = "qemu,fw-cfg-mmio";
- reg = <0x0 0x9020000 0x0 0xa>;
- };
-};
diff --git a/dts/Bindings/arm/intel,socfpga.yaml b/dts/Bindings/arm/intel,socfpga.yaml
new file mode 100644
index 0000000000..6e043459fc
--- /dev/null
+++ b/dts/Bindings/arm/intel,socfpga.yaml
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA platform device tree bindings
+
+maintainers:
+ - Dinh Nguyen <dinguyen@kernel.org>
+
+properties:
+ $nodename:
+ const: "/"
+ compatible:
+ oneOf:
+ - description: AgileX boards
+ items:
+ - enum:
+ - intel,n5x-socdk
+ - intel,socfpga-agilex-socdk
+ - const: intel,socfpga-agilex
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/linux,dummy-virt.yaml b/dts/Bindings/arm/linux,dummy-virt.yaml
new file mode 100644
index 0000000000..c7c5eb48fc
--- /dev/null
+++ b/dts/Bindings/arm/linux,dummy-virt.yaml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/linux,dummy-virt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QEMU virt machine
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+properties:
+ $nodename:
+ const: "/"
+ compatible:
+ const: linux,dummy-virt
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml
index 0ffe1acf13..ab0593c773 100644
--- a/dts/Bindings/arm/mediatek.yaml
+++ b/dts/Bindings/arm/mediatek.yaml
@@ -32,6 +32,10 @@ properties:
- const: mediatek,mt6580
- items:
- enum:
+ - prestigio,pmt5008-3g
+ - const: mediatek,mt6582
+ - items:
+ - enum:
- fairphone,fp1
- mundoreader,bq-aquaris5
- const: mediatek,mt6589
diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml
index 763c62323a..b31d90dc9e 100644
--- a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -29,6 +29,7 @@ properties:
- mediatek,mt8167-mmsys
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
+ - mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8365-mmsys
- const: syscon
diff --git a/dts/Bindings/arm/msm/qcom,idle-state.txt b/dts/Bindings/arm/msm/qcom,idle-state.txt
index 6ce0b212ec..606b4b1b70 100644
--- a/dts/Bindings/arm/msm/qcom,idle-state.txt
+++ b/dts/Bindings/arm/msm/qcom,idle-state.txt
@@ -81,4 +81,4 @@ Example:
};
};
-[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
+[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml
diff --git a/dts/Bindings/arm/msm/qcom,llcc.yaml b/dts/Bindings/arm/msm/qcom,llcc.yaml
index 03882aac8d..30fcbe2ad8 100644
--- a/dts/Bindings/arm/msm/qcom,llcc.yaml
+++ b/dts/Bindings/arm/msm/qcom,llcc.yaml
@@ -27,6 +27,8 @@ properties:
- qcom,sm6350-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
+ - qcom,sm8350-llcc
+ - qcom,sm8450-llcc
reg:
items:
diff --git a/dts/Bindings/arm/mstar/mstar.yaml b/dts/Bindings/arm/mstar/mstar.yaml
index a316eef1b7..8892eb6bd3 100644
--- a/dts/Bindings/arm/mstar/mstar.yaml
+++ b/dts/Bindings/arm/mstar/mstar.yaml
@@ -23,8 +23,12 @@ properties:
- description: infinity2m boards
items:
- enum:
+ - 100ask,dongshanpione # 100ask DongShanPiOne
- honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
- m5stack,unitv2 # M5Stack UnitV2
+ - miyoo,miyoo-mini # Miyoo Mini
+ - wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01
+ - wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W
- const: mstar,infinity2m
- description: infinity3 boards
diff --git a/dts/Bindings/arm/npcm/nuvoton,gcr.yaml b/dts/Bindings/arm/npcm/nuvoton,gcr.yaml
new file mode 100644
index 0000000000..fcb211add7
--- /dev/null
+++ b/dts/Bindings/arm/npcm/nuvoton,gcr.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Global Control Registers block in Nuvoton SoCs
+
+maintainers:
+ - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+
+description:
+ The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
+ that expose misc functionality such as chip model and version information or
+ pinmux settings.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - nuvoton,wpcm450-gcr
+ - nuvoton,npcm750-gcr
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ gcr: syscon@800000 {
+ compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
+ reg = <0x800000 0x1000>;
+
+ mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x38 0x07>;
+ idle-states = <2>;
+ };
+ };
diff --git a/dts/Bindings/arm/pmu.yaml b/dts/Bindings/arm/pmu.yaml
index 981bac4516..dbb6f3dc5a 100644
--- a/dts/Bindings/arm/pmu.yaml
+++ b/dts/Bindings/arm/pmu.yaml
@@ -20,6 +20,8 @@ properties:
items:
- enum:
- apm,potenza-pmu
+ - apple,firestorm-pmu
+ - apple,icestorm-pmu
- arm,armv8-pmuv3 # Only for s/w models
- arm,arm1136-pmu
- arm,arm1176-pmu
@@ -66,6 +68,8 @@ properties:
interrupt-affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
When using SPIs, specifies a list of phandles to CPU
nodes corresponding directly to the affinity of
diff --git a/dts/Bindings/arm/psci.yaml b/dts/Bindings/arm/psci.yaml
index 8b77cf83a0..dd83ef278a 100644
--- a/dts/Bindings/arm/psci.yaml
+++ b/dts/Bindings/arm/psci.yaml
@@ -101,7 +101,7 @@ properties:
bindings in [1]) must specify this property.
[1] Kernel documentation - ARM idle states bindings
- Documentation/devicetree/bindings/arm/idle-states.yaml
+ Documentation/devicetree/bindings/cpu/idle-states.yaml
patternProperties:
"^power-domain-":
diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml
index 04ff0b55bb..129cdd2462 100644
--- a/dts/Bindings/arm/qcom.yaml
+++ b/dts/Bindings/arm/qcom.yaml
@@ -42,6 +42,7 @@ description: |
sc7180
sc7280
sdm630
+ sdm632
sdm660
sdm845
sdx55
@@ -172,7 +173,21 @@ properties:
- const: qcom,apq8094
- items:
- - const: qcom,msm8996-mtp
+ - enum:
+ - arrow,apq8096-db820c
+ - inforce,ifc6640
+ - const: qcom,apq8096-sbc
+ - const: qcom,apq8096
+
+ - items:
+ - enum:
+ - qcom,msm8996-mtp
+ - sony,dora-row
+ - sony,kagura-row
+ - sony,keyaki-row
+ - xiaomi,gemini
+ - xiaomi,scorpio
+ - const: qcom,msm8996
- items:
- enum:
@@ -212,6 +227,11 @@ properties:
- items:
- enum:
+ - fairphone,fp3
+ - const: qcom,sdm632
+
+ - items:
+ - enum:
- xiaomi,lavender
- const: qcom,sdm660
@@ -262,6 +282,7 @@ properties:
- items:
- enum:
+ - qcom,sm8450-hdk
- qcom,sm8450-qrd
- const: qcom,sm8450
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
index 6a9350ee69..fa435d6fda 100644
--- a/dts/Bindings/arm/renesas.yaml
+++ b/dts/Bindings/arm/renesas.yaml
@@ -421,6 +421,15 @@ properties:
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
- const: renesas,r9a07g044
+ - description: RZ/V2L (R9A07G054)
+ items:
+ - enum:
+ - renesas,smarc-evk # SMARC EVK
+ - enum:
+ - renesas,r9a07g054l1 # Single Cortex-A55 RZ/V2L
+ - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
+ - const: renesas,r9a07g054
+
additionalProperties: true
...
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index 4aed161764..eece92f83a 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -481,6 +481,14 @@ properties:
- const: pine64,pinebook-pro
- const: rockchip,rk3399
+ - description: Pine64 PineNote
+ items:
+ - enum:
+ - pine64,pinenote-v1.1
+ - pine64,pinenote-v1.2
+ - const: pine64,pinenote
+ - const: rockchip,rk3566
+
- description: Pine64 Rock64
items:
- const: pine64,rock64
@@ -651,6 +659,11 @@ properties:
- const: rockchip,rk3568-evb1-v10
- const: rockchip,rk3568
+ - description: Rockchip RK3568 Banana Pi R2 Pro
+ items:
+ - const: rockchip,rk3568-bpi-r2pro
+ - const: rockchip,rk3568
+
additionalProperties: true
...
diff --git a/dts/Bindings/arm/samsung/samsung-boards.yaml b/dts/Bindings/arm/samsung/samsung-boards.yaml
index 052cd94113..faea33e4f7 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.yaml
+++ b/dts/Bindings/arm/samsung/samsung-boards.yaml
@@ -140,6 +140,8 @@ properties:
items:
- enum:
- insignal,arndale-octa # Insignal Arndale Octa
+ - samsung,chagall-wifi # Samsung SM-T800
+ - samsung,klimt-wifi # Samsung SM-T700
- samsung,smdk5420 # Samsung SMDK5420 eval
- const: samsung,exynos5420
- const: samsung,exynos5
diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml
index b07720ea96..fa0a1b8412 100644
--- a/dts/Bindings/arm/stm32/stm32.yaml
+++ b/dts/Bindings/arm/stm32/stm32.yaml
@@ -28,6 +28,12 @@ properties:
- enum:
- st,stm32mp153
- st,stm32mp157
+
+ - description: emtrion STM32MP1 Argon based Boards
+ items:
+ - const: emtrion,stm32mp157c-emsbc-argon
+ - const: emtrion,stm32mp157c-emstamp-argon
+ - const: st,stm32mp157
- items:
- enum:
- st,stm32f429i-disco
diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml
index c8a3102c0f..086c68771d 100644
--- a/dts/Bindings/arm/sunxi.yaml
+++ b/dts/Bindings/arm/sunxi.yaml
@@ -444,6 +444,11 @@ properties:
- const: haoyu,a10-marsboard
- const: allwinner,sun4i-a10
+ - description: HAOYU Electronics Marsboard A20
+ items:
+ - const: haoyu,a20-marsboard
+ - const: allwinner,sun7i-a20
+
- description: MapleBoard MP130
items:
- const: mapleboard,mp130
diff --git a/dts/Bindings/arm/tesla.yaml b/dts/Bindings/arm/tesla.yaml
new file mode 100644
index 0000000000..09856da657
--- /dev/null
+++ b/dts/Bindings/arm/tesla.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tesla.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla Full Self Driving(FSD) platforms device tree bindings
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+ - linux-fsd@tesla.com
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: FSD SoC board
+ items:
+ - enum:
+ - tesla,fsd-evb # Tesla FSD Evaluation
+ - const: tesla,fsd
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml
index b03c10fa2e..61c6ab4f52 100644
--- a/dts/Bindings/arm/ti/k3.yaml
+++ b/dts/Bindings/arm/ti/k3.yaml
@@ -46,6 +46,12 @@ properties:
- ti,j7200-evm
- const: ti,j7200
+ - description: K3 AM625 SoC
+ items:
+ - enum:
+ - ti,am625-sk
+ - const: ti,am625
+
- description: K3 AM642 SoC
items:
- enum:
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
deleted file mode 100644
index 77091a2776..0000000000
--- a/dts/Bindings/ata/ahci-platform.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-* AHCI SATA Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-It is possible, but not required, to represent each port as a sub-node.
-It allows to enable each port independently when dealing with multiple
-PHYs.
-
-Required properties:
-- compatible : compatible string, one of:
- - "brcm,iproc-ahci"
- - "hisilicon,hisi-ahci"
- - "cavium,octeon-7130-ahci"
- - "ibm,476gtr-ahci"
- - "marvell,armada-380-ahci"
- - "marvell,armada-3700-ahci"
- - "snps,dwc-ahci"
- - "snps,spear-ahci"
- - "generic-ahci"
-- interrupts : <interrupt mapping for SATA IRQ>
-- reg : <registers mapping>
-
-Please note that when using "generic-ahci" you must also specify a SoC specific
-compatible:
- compatible = "manufacturer,soc-model-ahci", "generic-ahci";
-
-Optional properties:
-- dma-coherent : Present if dma operations are coherent
-- clocks : a list of phandle + clock specifier pairs
-- resets : a list of phandle + reset specifier pairs
-- target-supply : regulator for SATA target power
-- phy-supply : regulator for PHY power
-- phys : reference to the SATA PHY node
-- phy-names : must be "sata-phy"
-- ahci-supply : regulator for AHCI controller
-- ports-implemented : Mask that indicates which ports that the HBA supports
- are available for software to use. Useful if PORTS_IMPL
- is not programmed by the BIOS, which is true with
- some embedded SOC's.
-
-Required properties when using sub-nodes:
-- #address-cells : number of cells to encode an address
-- #size-cells : number of cells representing the size of an address
-
-Sub-nodes required properties:
-- reg : the port number
-And at least one of the following properties:
-- phys : reference to the SATA PHY node
-- target-supply : regulator for SATA target power
-
-Examples:
- sata@ffe08000 {
- compatible = "snps,spear-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
- };
-
-With sub-nodes:
- sata@f7e90000 {
- compatible = "marvell,berlin2q-achi", "generic-ahci";
- reg = <0xe90000 0x1000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_SATA>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata0: sata-port@0 {
- reg = <0>;
- phys = <&sata_phy 0>;
- target-supply = <&reg_sata0>;
- };
-
- sata1: sata-port@1 {
- reg = <1>;
- phys = <&sata_phy 1>;
- target-supply = <&reg_sata1>;;
- };
- };
diff --git a/dts/Bindings/ata/ahci-platform.yaml b/dts/Bindings/ata/ahci-platform.yaml
new file mode 100644
index 0000000000..c146ab8e14
--- /dev/null
+++ b/dts/Bindings/ata/ahci-platform.yaml
@@ -0,0 +1,189 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AHCI SATA Controller
+
+description: |
+ SATA nodes are defined to describe on-chip Serial ATA controllers.
+ Each SATA controller should have its own node.
+
+ It is possible, but not required, to represent each port as a sub-node.
+ It allows to enable each port independently when dealing with multiple
+ PHYs.
+
+maintainers:
+ - Hans de Goede <hdegoede@redhat.com>
+ - Jens Axboe <axboe@kernel.dk>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,iproc-ahci
+ - cavium,octeon-7130-ahci
+ - hisilicon,hisi-ahci
+ - ibm,476gtr-ahci
+ - marvell,armada-3700-ahci
+ - marvell,armada-8k-ahci
+ - marvell,berlin2q-ahci
+ - snps,dwc-ahci
+ - snps,spear-ahci
+ required:
+ - compatible
+
+allOf:
+ - $ref: "sata-common.yaml#"
+
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,iproc-ahci
+ - marvell,armada-8k-ahci
+ - marvell,berlin2-ahci
+ - marvell,berlin2q-ahci
+ - const: generic-ahci
+ - items:
+ - enum:
+ - rockchip,rk3568-dwc-ahci
+ - const: snps,dwc-ahci
+ - enum:
+ - cavium,octeon-7130-ahci
+ - hisilicon,hisi-ahci
+ - ibm,476gtr-ahci
+ - marvell,armada-3700-ahci
+ - snps,dwc-ahci
+ - snps,spear-ahci
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ maxItems: 1
+
+ clocks:
+ description:
+ Clock IDs array as required by the controller.
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ description:
+ Names of clocks corresponding to IDs in the clock property.
+ minItems: 1
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ ahci-supply:
+ description:
+ regulator for AHCI controller
+
+ dma-coherent: true
+
+ phy-supply:
+ description:
+ regulator for PHY power
+
+ phys:
+ description:
+ List of all PHYs on this controller
+ maxItems: 1
+
+ phy-names:
+ description:
+ Name specifier for the PHYs
+ maxItems: 1
+
+ ports-implemented:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ Mask that indicates which ports that the HBA supports
+ are available for software to use. Useful if PORTS_IMPL
+ is not programmed by the BIOS, which is true with
+ some embedded SoCs.
+ maximum: 0x1f
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ target-supply:
+ description:
+ regulator for SATA target power
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+patternProperties:
+ "^sata-port@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+ description:
+ Subnode with configuration of the Ports.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ maxItems: 1
+
+ target-supply:
+ description:
+ regulator for SATA target power
+
+ required:
+ - reg
+
+ anyOf:
+ - required: [ phys ]
+ - required: [ target-supply ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sata@ffe08000 {
+ compatible = "snps,spear-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/berlin2q.h>
+ sata@f7e90000 {
+ compatible = "marvell,berlin2q-ahci", "generic-ahci";
+ reg = <0xf7e90000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ target-supply = <&reg_sata0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ target-supply = <&reg_sata1>;
+ };
+ };
diff --git a/dts/Bindings/ata/cortina,gemini-sata-bridge.txt b/dts/Bindings/ata/cortina,gemini-sata-bridge.txt
deleted file mode 100644
index 1c3d3cc700..0000000000
--- a/dts/Bindings/ata/cortina,gemini-sata-bridge.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-* Cortina Systems Gemini SATA Bridge
-
-The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
-takes two Faraday Technology FTIDE010 PATA controllers and bridges
-them in different configurations to two SATA ports.
-
-Required properties:
-- compatible: should be
- "cortina,gemini-sata-bridge"
-- reg: registers and size for the block
-- resets: phandles to the reset lines for both SATA bridges
-- reset-names: must be "sata0", "sata1"
-- clocks: phandles to the compulsory peripheral clocks
-- clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
-- syscon: a phandle to the global Gemini system controller
-- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for
- the ATA controller and SATA bridges. Values 0..3:
- Mode 0: ata0 master <-> sata0
- ata1 master <-> sata1
- ata0 slave interface brought out on IDE pads
- Mode 1: ata0 master <-> sata0
- ata1 master <-> sata1
- ata1 slave interface brought out on IDE pads
- Mode 2: ata1 master <-> sata1
- ata1 slave <-> sata0
- ata0 master and slave interfaces brought out
- on IDE pads
- Mode 3: ata0 master <-> sata0
- ata0 slave <-> sata1
- ata1 master and slave interfaces brought out
- on IDE pads
-
-Optional boolean properties:
-- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection.
- The muxmode setting decides whether ATA0 or ATA1 is brought out,
- and whether master, slave or both interfaces get brought out.
-- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge
- inside the Gemnini SoC. The Muxmode decides what PATA blocks will
- be muxed out and how.
-
-Example:
-
-sata: sata@46000000 {
- compatible = "cortina,gemini-sata-bridge";
- reg = <0x46000000 0x100>;
- resets = <&rcon 26>, <&rcon 27>;
- reset-names = "sata0", "sata1";
- clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
- <&gcc GEMINI_CLK_GATE_SATA1>;
- clock-names = "SATA0_PCLK", "SATA1_PCLK";
- syscon = <&syscon>;
- cortina,gemini-ata-muxmode = <3>;
- cortina,gemini-enable-ide-pins;
- cortina,gemini-enable-sata-bridge;
-};
diff --git a/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml b/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml
new file mode 100644
index 0000000000..21a9097559
--- /dev/null
+++ b/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortina Systems Gemini SATA Bridge
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
+ takes two Faraday Technology FTIDE010 PATA controllers and bridges
+ them in different configurations to two SATA ports.
+
+properties:
+ compatible:
+ const: cortina,gemini-sata-bridge
+
+ reg:
+ maxItems: 1
+
+ resets:
+ minItems: 2
+ maxItems: 2
+ description: phandles to the reset lines for both SATA bridges
+
+ reset-names:
+ items:
+ - const: sata0
+ - const: sata1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+ description: phandles to the compulsory peripheral clocks
+
+ clock-names:
+ items:
+ - const: SATA0_PCLK
+ - const: SATA1_PCLK
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the global Gemini system controller
+
+ cortina,gemini-ata-muxmode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0
+ - 1
+ - 2
+ - 3
+ description: |
+ Tell the desired multiplexing mode for the ATA controller and SATA
+ bridges.
+ Mode 0: ata0 master <-> sata0
+ ata1 master <-> sata1
+ ata0 slave interface brought out on IDE pads
+ Mode 1: ata0 master <-> sata0
+ ata1 master <-> sata1
+ ata1 slave interface brought out on IDE pads
+ Mode 2: ata1 master <-> sata1
+ ata1 slave <-> sata0
+ ata0 master and slave interfaces brought out on IDE pads
+ Mode 3: ata0 master <-> sata0
+ ata0 slave <-> sata1
+ ata1 master and slave interfaces brought out on IDE pads
+
+ cortina,gemini-enable-ide-pins:
+ type: boolean
+ description: Enables the PATA to IDE connection.
+ The muxmode setting decides whether ATA0 or ATA1 is brought out,
+ and whether master, slave or both interfaces get brought out.
+
+ cortina,gemini-enable-sata-bridge:
+ type: boolean
+ description: Enables the PATA to SATA bridge inside the Gemnini SoC.
+ The Muxmode decides what PATA blocks will be muxed out and how.
+
+required:
+ - clocks
+ - clock-names
+ - cortina,gemini-ata-muxmode
+ - resets
+ - reset-names
+ - compatible
+ - reg
+ - syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ sata@46000000 {
+ compatible = "cortina,gemini-sata-bridge";
+ reg = <0x46000000 0x100>;
+ resets = <&rcon 26>, <&rcon 27>;
+ reset-names = "sata0", "sata1";
+ clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
+ <&gcc GEMINI_CLK_GATE_SATA1>;
+ clock-names = "SATA0_PCLK", "SATA1_PCLK";
+ syscon = <&syscon>;
+ cortina,gemini-ata-muxmode = <3>;
+ cortina,gemini-enable-ide-pins;
+ cortina,gemini-enable-sata-bridge;
+ };
diff --git a/dts/Bindings/ata/sata_highbank.yaml b/dts/Bindings/ata/sata_highbank.yaml
index ce75d77e92..49679b5804 100644
--- a/dts/Bindings/ata/sata_highbank.yaml
+++ b/dts/Bindings/ata/sata_highbank.yaml
@@ -51,6 +51,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
+ items:
+ minItems: 2
+ maxItems: 2
calxeda,tx-atten:
description: |
diff --git a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml
index 863a287ebc..ad313ccaaa 100644
--- a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml
+++ b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml
@@ -35,7 +35,10 @@ properties:
The SRAM that needs to be claimed to access the display engine
bus.
$ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to SRAM
+ - description: register value for device
ranges: true
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml b/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml
index 7b1a08c62a..d3ed048c95 100644
--- a/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml
+++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml
@@ -21,6 +21,7 @@ properties:
- const: nvidia,tegra210-aconnect
- items:
- enum:
+ - nvidia,tegra234-aconnect
- nvidia,tegra186-aconnect
- nvidia,tegra194-aconnect
- const: nvidia,tegra210-aconnect
diff --git a/dts/Bindings/clock/apple,nco.yaml b/dts/Bindings/clock/apple,nco.yaml
new file mode 100644
index 0000000000..74eab5c0d2
--- /dev/null
+++ b/dts/Bindings/clock/apple,nco.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/apple,nco.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple SoCs' NCO block
+
+maintainers:
+ - Martin Povišer <povik+lin@cutebit.org>
+
+description: |
+ The NCO (Numerically Controlled Oscillator) block found on Apple SoCs
+ such as the t8103 (M1) is a programmable clock generator performing
+ fractional division of a high frequency input clock.
+
+ It carries a number of independent channels and is typically used for
+ generation of audio bitclocks.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - apple,t6000-nco
+ - apple,t8103-nco
+ - const: apple,nco
+
+ clocks:
+ description:
+ Specifies the reference clock from which the output clocks
+ are derived through fractional division.
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ nco_clkref: clock-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <900000000>;
+ clock-output-names = "nco-ref";
+ };
+
+ nco: clock-controller@23b044000 {
+ compatible = "apple,t8103-nco", "apple,nco";
+ reg = <0x3b044000 0x14000>;
+ #clock-cells = <1>;
+ clocks = <&nco_clkref>;
+ };
diff --git a/dts/Bindings/clock/bitmain,bm1880-clk.yaml b/dts/Bindings/clock/bitmain,bm1880-clk.yaml
index 228c9313df..f0f9392470 100644
--- a/dts/Bindings/clock/bitmain,bm1880-clk.yaml
+++ b/dts/Bindings/clock/bitmain,bm1880-clk.yaml
@@ -61,16 +61,4 @@ examples:
#clock-cells = <1>;
};
- # Example UART controller node that consumes clock generated by the clock controller:
- - |
- uart0: serial@58018000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x58018000 0x2000>;
- clocks = <&clk 45>, <&clk 46>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <0 9 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-
...
diff --git a/dts/Bindings/clock/cirrus,cs2000-cp.yaml b/dts/Bindings/clock/cirrus,cs2000-cp.yaml
new file mode 100644
index 0000000000..0abd6ba82d
--- /dev/null
+++ b/dts/Bindings/clock/cirrus,cs2000-cp.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+description: |
+ The CS2000-CP is an extremely versatile system clocking device that
+ utilizes a programmable phase lock loop.
+
+ Link: https://www.cirrus.com/products/cs2000/
+
+properties:
+ compatible:
+ enum:
+ - cirrus,cs2000-cp
+
+ clocks:
+ description:
+ Common clock binding for CLK_IN, XTI/REF_CLK
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: clk_in
+ - const: ref_clk
+
+ '#clock-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ cirrus,aux-output-source:
+ description:
+ Specifies the function of the auxiliary clock output pin
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
+ - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
+ - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
+ - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
+ default: 0
+
+ cirrus,clock-skip:
+ description:
+ This mode allows the PLL to maintain lock even when CLK_IN
+ has missing pulses for up to 20 ms.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ cirrus,dynamic-mode:
+ description:
+ In dynamic mode, the CLK_IN input is used to drive the
+ digital PLL of the silicon.
+ If not given, the static mode shall be used to derive the
+ output signal directly from the REF_CLK input.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/cirrus,cs2000-cp.h>
+
+ i2c@0 {
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-controller@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&rcar_sound 0>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+ cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;
+ };
+ };
diff --git a/dts/Bindings/clock/cs2000-cp.txt b/dts/Bindings/clock/cs2000-cp.txt
deleted file mode 100644
index 54e6df0bee..0000000000
--- a/dts/Bindings/clock/cs2000-cp.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
-
-Required properties:
-
-- compatible: "cirrus,cs2000-cp"
-- reg: The chip select number on the I2C bus
-- clocks: common clock binding for CLK_IN, XTI/REF_CLK
-- clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk
-- #clock-cells: must be <0>
-
-Example:
-
-&i2c2 {
- ...
- cs2000: clk_multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&rcar_sound 0>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
- };
-};
diff --git a/dts/Bindings/clock/idt,versaclock5.yaml b/dts/Bindings/clock/idt,versaclock5.yaml
index ffd6ae0eed..be66f1e8b5 100644
--- a/dts/Bindings/clock/idt,versaclock5.yaml
+++ b/dts/Bindings/clock/idt,versaclock5.yaml
@@ -191,11 +191,4 @@ examples:
};
};
- /* Consumer referencing the 5P49V5923 pin OUT1 */
- consumer {
- /* ... */
- clocks = <&vc5 1>;
- /* ... */
- };
-
...
diff --git a/dts/Bindings/clock/imx1-clock.yaml b/dts/Bindings/clock/imx1-clock.yaml
index f4833a29b7..56f524780b 100644
--- a/dts/Bindings/clock/imx1-clock.yaml
+++ b/dts/Bindings/clock/imx1-clock.yaml
@@ -40,12 +40,3 @@ examples:
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
-
- pwm@208000 {
- #pwm-cells = <2>;
- compatible = "fsl,imx1-pwm";
- reg = <0x00208000 0x1000>;
- interrupts = <34>;
- clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
- clock-names = "ipg", "per";
- };
diff --git a/dts/Bindings/clock/imx21-clock.yaml b/dts/Bindings/clock/imx21-clock.yaml
index 518ad9a473..e2d5054470 100644
--- a/dts/Bindings/clock/imx21-clock.yaml
+++ b/dts/Bindings/clock/imx21-clock.yaml
@@ -40,12 +40,3 @@ examples:
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};
-
- serial@1000a000 {
- compatible = "fsl,imx21-uart";
- reg = <0x1000a000 0x1000>;
- interrupts = <20>;
- clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
- <&clks IMX21_CLK_PER1>;
- clock-names = "ipg", "per";
- };
diff --git a/dts/Bindings/clock/imx23-clock.yaml b/dts/Bindings/clock/imx23-clock.yaml
index 5e296a00e1..7e890ab9c7 100644
--- a/dts/Bindings/clock/imx23-clock.yaml
+++ b/dts/Bindings/clock/imx23-clock.yaml
@@ -83,12 +83,3 @@ examples:
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
-
- serial@8006c000 {
- compatible = "fsl,imx23-auart";
- reg = <0x8006c000 0x2000>;
- interrupts = <24>;
- clocks = <&clks 32>;
- dmas = <&dma_apbx 6>, <&dma_apbx 7>;
- dma-names = "rx", "tx";
- };
diff --git a/dts/Bindings/clock/imx25-clock.yaml b/dts/Bindings/clock/imx25-clock.yaml
index 2a2b10778e..1792e13898 100644
--- a/dts/Bindings/clock/imx25-clock.yaml
+++ b/dts/Bindings/clock/imx25-clock.yaml
@@ -176,11 +176,3 @@ examples:
interrupts = <31>;
#clock-cells = <1>;
};
-
- serial@43f90000 {
- compatible = "fsl,imx25-uart", "fsl,imx21-uart";
- reg = <0x43f90000 0x4000>;
- interrupts = <45>;
- clocks = <&clks 79>, <&clks 50>;
- clock-names = "ipg", "per";
- };
diff --git a/dts/Bindings/clock/imx27-clock.yaml b/dts/Bindings/clock/imx27-clock.yaml
index 160268f244..99925aa22a 100644
--- a/dts/Bindings/clock/imx27-clock.yaml
+++ b/dts/Bindings/clock/imx27-clock.yaml
@@ -44,12 +44,3 @@ examples:
interrupts = <31>;
#clock-cells = <1>;
};
-
- serial@1000a000 {
- compatible = "fsl,imx27-uart", "fsl,imx21-uart";
- reg = <0x1000a000 0x1000>;
- interrupts = <20>;
- clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
- <&clks IMX27_CLK_PER1_GATE>;
- clock-names = "ipg", "per";
- };
diff --git a/dts/Bindings/clock/imx28-clock.yaml b/dts/Bindings/clock/imx28-clock.yaml
index f831b780f9..a542d680b1 100644
--- a/dts/Bindings/clock/imx28-clock.yaml
+++ b/dts/Bindings/clock/imx28-clock.yaml
@@ -106,12 +106,3 @@ examples:
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
-
- serial@8006a000 {
- compatible = "fsl,imx28-auart";
- reg = <0x8006a000 0x2000>;
- interrupts = <112>;
- dmas = <&dma_apbx 8>, <&dma_apbx 9>;
- dma-names = "rx", "tx";
- clocks = <&clks 45>;
- };
diff --git a/dts/Bindings/clock/imx31-clock.yaml b/dts/Bindings/clock/imx31-clock.yaml
index d2336261c9..168c8ada5e 100644
--- a/dts/Bindings/clock/imx31-clock.yaml
+++ b/dts/Bindings/clock/imx31-clock.yaml
@@ -110,11 +110,3 @@ examples:
interrupts = <31>, <53>;
#clock-cells = <1>;
};
-
- serial@43f90000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43f90000 0x4000>;
- interrupts = <45>;
- clocks = <&clks 10>, <&clks 30>;
- clock-names = "ipg", "per";
- };
diff --git a/dts/Bindings/clock/imx35-clock.yaml b/dts/Bindings/clock/imx35-clock.yaml
index 3e20ccaf81..6415bb6a8d 100644
--- a/dts/Bindings/clock/imx35-clock.yaml
+++ b/dts/Bindings/clock/imx35-clock.yaml
@@ -129,11 +129,3 @@ examples:
interrupts = <31>;
#clock-cells = <1>;
};
-
- mmc@53fb4000 {
- compatible = "fsl,imx35-esdhc";
- reg = <0x53fb4000 0x4000>;
- interrupts = <7>;
- clocks = <&clks 9>, <&clks 8>, <&clks 43>;
- clock-names = "ipg", "ahb", "per";
- };
diff --git a/dts/Bindings/clock/imx7ulp-pcc-clock.yaml b/dts/Bindings/clock/imx7ulp-pcc-clock.yaml
index 7caf5cee91..739c3378f8 100644
--- a/dts/Bindings/clock/imx7ulp-pcc-clock.yaml
+++ b/dts/Bindings/clock/imx7ulp-pcc-clock.yaml
@@ -108,14 +108,3 @@ examples:
"upll", "sosc_bus_clk", "firc_bus_clk",
"rosc", "spll_bus_clk";
};
-
- mmc@40380000 {
- compatible = "fsl,imx7ulp-usdhc";
- reg = <0x40380000 0x10000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&pcc2 IMX7ULP_CLK_USDHC1>;
- clock-names ="ipg", "ahb", "per";
- bus-width = <4>;
- };
diff --git a/dts/Bindings/clock/imx7ulp-scg-clock.yaml b/dts/Bindings/clock/imx7ulp-scg-clock.yaml
index ee8efb4ed5..d06344d7e3 100644
--- a/dts/Bindings/clock/imx7ulp-scg-clock.yaml
+++ b/dts/Bindings/clock/imx7ulp-scg-clock.yaml
@@ -86,14 +86,3 @@ examples:
"firc", "upll";
#clock-cells = <1>;
};
-
- mmc@40380000 {
- compatible = "fsl,imx7ulp-usdhc";
- reg = <0x40380000 0x10000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&pcc2 IMX7ULP_CLK_USDHC1>;
- clock-names ="ipg", "ahb", "per";
- bus-width = <4>;
- };
diff --git a/dts/Bindings/clock/imx8qxp-lpcg.yaml b/dts/Bindings/clock/imx8qxp-lpcg.yaml
index 0f6fe365eb..cb80105b3c 100644
--- a/dts/Bindings/clock/imx8qxp-lpcg.yaml
+++ b/dts/Bindings/clock/imx8qxp-lpcg.yaml
@@ -101,14 +101,3 @@ examples:
"sdhc0_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
-
- mmc@5b010000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b010000 0x10000>;
- clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
- <&sdhc0_lpcg IMX_LPCG_CLK_5>,
- <&sdhc0_lpcg IMX_LPCG_CLK_0>;
- clock-names = "ipg", "ahb", "per";
- power-domains = <&pd IMX_SC_R_SDHC_0>;
- };
diff --git a/dts/Bindings/clock/imx93-clock.yaml b/dts/Bindings/clock/imx93-clock.yaml
new file mode 100644
index 0000000000..21a06194e4
--- /dev/null
+++ b/dts/Bindings/clock/imx93-clock.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 Clock Control Module Binding
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description: |
+ i.MX93 clock control module is an integrated clock controller, which
+ includes clock generator, clock gate and supplies to all modules.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx93-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ specify the external clocks used by the CCM module.
+ items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+
+ clock-names:
+ description:
+ specify the external clocks names used by the CCM module.
+ items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See include/dt-bindings/clock/imx93-clock.h for the full list of
+ i.MX93 clock IDs.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ clock-controller@44450000 {
+ compatible = "fsl,imx93-ccm";
+ reg = <0x44450000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/dts/Bindings/clock/imxrt1050-clock.yaml b/dts/Bindings/clock/imxrt1050-clock.yaml
new file mode 100644
index 0000000000..03fc5c1a29
--- /dev/null
+++ b/dts/Bindings/clock/imxrt1050-clock.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imxrt1050-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for Freescale i.MXRT
+
+maintainers:
+ - Giulio Benetti <giulio.benetti@benettiengineering.com>
+ - Jesse Taube <Mr.Bossman075@gmail.com>
+
+description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imxrt*-clock.h
+ for the full list of i.MXRT clock IDs.
+
+properties:
+ compatible:
+ const: fsl,imxrt1050-ccm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 2
+
+ clocks:
+ description: 24m osc
+ maxItems: 1
+
+ clock-names:
+ const: osc
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imxrt1050-clock.h>
+
+ clks: clock-controller@400fc000 {
+ compatible = "fsl,imxrt1050-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <95>, <96>;
+ clocks = <&osc>;
+ clock-names = "osc";
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/intc_stratix10.txt b/dts/Bindings/clock/intc_stratix10.txt
deleted file mode 100644
index 9f4ec5cb5c..0000000000
--- a/dts/Bindings/clock/intc_stratix10.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be
- "intel,stratix10-clkmgr"
-
-- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
-
-- #clock-cells : from common clock binding, shall be set to 1.
-
-Example:
- clkmgr: clock-controller@ffd10000 {
- compatible = "intel,stratix10-clkmgr";
- reg = <0xffd10000 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/dts/Bindings/clock/intel,stratix10.yaml b/dts/Bindings/clock/intel,stratix10.yaml
new file mode 100644
index 0000000000..f506e3db97
--- /dev/null
+++ b/dts/Bindings/clock/intel,stratix10.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Stratix10 platform clock controller binding
+
+maintainers:
+ - Dinh Nguyen <dinguyen@kernel.org>
+
+properties:
+ compatible:
+ const: intel,stratix10-clkmgr
+
+ '#clock-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ffd10000 {
+ compatible = "intel,stratix10-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/marvell,armada-3700-uart-clock.yaml b/dts/Bindings/clock/marvell,armada-3700-uart-clock.yaml
new file mode 100644
index 0000000000..175f5c8f2b
--- /dev/null
+++ b/dts/Bindings/clock/marvell,armada-3700-uart-clock.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Marvell Armada 3720 UART clocks
+
+maintainers:
+ - Pali Rohár <pali@kernel.org>
+
+properties:
+ compatible:
+ const: marvell,armada-3700-uart-clock
+
+ reg:
+ items:
+ - description: UART Clock Control Register
+ - description: UART 2 Baud Rate Divisor Register
+
+ clocks:
+ description: |
+ List of parent clocks suitable for UART from following set:
+ "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
+ UART clock can use one from this set and when more are provided
+ then kernel would choose and configure the most suitable one.
+ It is suggest to specify at least one TBG clock to achieve
+ baudrates above 230400 and also to specify clock which bootloader
+ used for UART (most probably xtal) for smooth boot log on UART.
+
+ clock-names:
+ items:
+ - const: TBG-A-P
+ - const: TBG-B-P
+ - const: TBG-A-S
+ - const: TBG-B-S
+ - const: xtal
+ minItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ uartclk: clock-controller@12010 {
+ compatible = "marvell,armada-3700-uart-clock";
+ reg = <0x12010 0x4>, <0x12210 0x4>;
+ clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
+ clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/mediatek,mt7621-sysc.yaml b/dts/Bindings/clock/mediatek,mt7621-sysc.yaml
index 915f84efd7..0c0b0ae5e2 100644
--- a/dts/Bindings/clock/mediatek,mt7621-sysc.yaml
+++ b/dts/Bindings/clock/mediatek,mt7621-sysc.yaml
@@ -22,6 +22,11 @@ description: |
The clocks are provided inside a system controller node.
+ This node is also a reset provider for all the peripherals.
+
+ Reset related bits are defined in:
+ [2]: <include/dt-bindings/reset/mt7621-reset.h>.
+
properties:
compatible:
items:
@@ -37,6 +42,12 @@ properties:
clocks.
const: 1
+ "#reset-cells":
+ description:
+ The first cell indicates the reset bit within the register, see
+ [2] for available resets.
+ const: 1
+
ralink,memctl:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -61,6 +72,7 @@ examples:
compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
+ #reset-cells = <1>;
ralink,memctl = <&memc>;
clock-output-names = "xtal", "cpu", "bus",
"50m", "125m", "150m",
diff --git a/dts/Bindings/clock/microchip,mpfs.yaml b/dts/Bindings/clock/microchip,mpfs.yaml
new file mode 100644
index 0000000000..0c15afa221
--- /dev/null
+++ b/dts/Bindings/clock/microchip,mpfs.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Clock Control Module Binding
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+
+description: |
+ Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
+ which gates and enables all peripheral clocks.
+
+ This device tree binding describes 33 gate clocks. Clocks are referenced by
+ user nodes by the CLKCFG node phandle and the clock index in the group, from
+ 0 to 32.
+
+properties:
+ compatible:
+ const: microchip,mpfs-clkcfg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+ description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
+ for the full list of PolarFire clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock Config node:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clkcfg: clock-controller@20002000 {
+ compatible = "microchip,mpfs-clkcfg";
+ reg = <0x0 0x20002000 0x0 0x1000>;
+ clocks = <&ref>;
+ #clock-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/clock/mstar,msc313-cpupll.yaml b/dts/Bindings/clock/mstar,msc313-cpupll.yaml
new file mode 100644
index 0000000000..a9ad7ab523
--- /dev/null
+++ b/dts/Bindings/clock/mstar,msc313-cpupll.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar/Sigmastar MSC313 CPU PLL
+
+maintainers:
+ - Daniel Palmer <daniel@thingy.jp>
+
+description: |
+ The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable
+ PLL that can be used as the clock source for the CPU(s).
+
+properties:
+ compatible:
+ const: mstar,msc313-cpupll
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mstar-msc313-mpll.h>
+ cpupll: cpupll@206400 {
+ compatible = "mstar,msc313-cpupll";
+ reg = <0x206400 0x200>;
+ #clock-cells = <1>;
+ clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
+ };
diff --git a/dts/Bindings/clock/nvidia,tegra124-car.yaml b/dts/Bindings/clock/nvidia,tegra124-car.yaml
index ec7ab14836..1b2181f6d4 100644
--- a/dts/Bindings/clock/nvidia,tegra124-car.yaml
+++ b/dts/Bindings/clock/nvidia,tegra124-car.yaml
@@ -106,10 +106,3 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
};
-
- usb-controller@c5004000 {
- compatible = "nvidia,tegra20-ehci";
- reg = <0xc5004000 0x4000>;
- clocks = <&car TEGRA124_CLK_USB2>;
- resets = <&car TEGRA124_CLK_USB2>;
- };
diff --git a/dts/Bindings/clock/nvidia,tegra20-car.yaml b/dts/Bindings/clock/nvidia,tegra20-car.yaml
index f832abb7f1..bee2dd4b29 100644
--- a/dts/Bindings/clock/nvidia,tegra20-car.yaml
+++ b/dts/Bindings/clock/nvidia,tegra20-car.yaml
@@ -97,10 +97,3 @@ examples:
power-domains = <&domain>;
};
};
-
- usb-controller@c5004000 {
- compatible = "nvidia,tegra20-ehci";
- reg = <0xc5004000 0x4000>;
- clocks = <&car TEGRA20_CLK_USB2>;
- resets = <&car TEGRA20_CLK_USB2>;
- };
diff --git a/dts/Bindings/clock/qcom,a7pll.yaml b/dts/Bindings/clock/qcom,a7pll.yaml
index 8666e99572..0e96f693b0 100644
--- a/dts/Bindings/clock/qcom,a7pll.yaml
+++ b/dts/Bindings/clock/qcom,a7pll.yaml
@@ -10,7 +10,7 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties:
diff --git a/dts/Bindings/clock/qcom,camcc.txt b/dts/Bindings/clock/qcom,camcc.txt
deleted file mode 100644
index c5eb6694fd..0000000000
--- a/dts/Bindings/clock/qcom,camcc.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Qualcomm Camera Clock & Reset Controller Binding
-------------------------------------------------
-
-Required properties :
-- compatible : shall contain "qcom,sdm845-camcc".
-- reg : shall contain base register location and length.
-- #clock-cells : from common clock binding, shall contain 1.
-- #reset-cells : from common reset binding, shall contain 1.
-- #power-domain-cells : from generic power domain binding, shall contain 1.
-
-Example:
- camcc: clock-controller@ad00000 {
- compatible = "qcom,sdm845-camcc";
- reg = <0xad00000 0x10000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
diff --git a/dts/Bindings/clock/qcom,dispcc-sm6125.yaml b/dts/Bindings/clock/qcom,dispcc-sm6125.yaml
new file mode 100644
index 0000000000..7a03ef19c9
--- /dev/null
+++ b/dts/Bindings/clock/qcom,dispcc-sm6125.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock Controller Binding for SM6125
+
+maintainers:
+ - Martin Botka <martin.botka@somainline.org>
+
+description: |
+ Qualcomm display clock control module which supports the clocks and
+ power domains on SM6125.
+
+ See also:
+ dt-bindings/clock/qcom,dispcc-sm6125.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6125-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+ - description: AHB config clock from GCC
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dsi1_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+ - const: cfg_ahb_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6125.h>
+ clock-controller@5f00000 {
+ compatible = "qcom,sm6125-dispcc";
+ reg = <0x5f00000 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi1_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>,
+ <&gcc GCC_DISP_AHB_CLK>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "cfg_ahb_clk";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,dispcc-sm6350.yaml b/dts/Bindings/clock/qcom,dispcc-sm6350.yaml
new file mode 100644
index 0000000000..e706678b35
--- /dev/null
+++ b/dts/Bindings/clock/qcom,dispcc-sm6350.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM6350
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@somainline.org>
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on SM6350.
+
+ See also dt-bindings/clock/qcom,dispcc-sm6350.h.
+
+properties:
+ compatible:
+ const: qcom,sm6350-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 source from GCC
+ - description: Byte clock from DSI PHY
+ - description: Pixel clock from DSI PHY
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: gcc_disp_gpll0_clk
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm6350-dispcc";
+ reg = <0x0af00000 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK>,
+ <&dsi_phy 0>,
+ <&dsi_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ clock-names = "bi_tcxo",
+ "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/Bindings/clock/qcom,gcc-apq8064.yaml
index 8e2eac6cbf..97936411b6 100644
--- a/dts/Bindings/clock/qcom,gcc-apq8064.yaml
+++ b/dts/Bindings/clock/qcom,gcc-apq8064.yaml
@@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
+allOf:
+ - $ref: qcom,gcc.yaml#
+
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
@@ -17,22 +20,12 @@ description: |
See also:
- dt-bindings/clock/qcom,gcc-msm8960.h
- dt-bindings/reset/qcom,gcc-msm8960.h
+ - dt-bindings/clock/qcom,gcc-apq8084.h
+ - dt-bindings/reset/qcom,gcc-apq8084.h
properties:
compatible:
- const: qcom,gcc-apq8064
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
+ const: qcom,gcc-apq8084
nvmem-cells:
minItems: 1
@@ -53,21 +46,13 @@ properties:
'#thermal-sensor-cells':
const: 1
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
- nvmem-cells
- nvmem-cell-names
- '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/Bindings/clock/qcom,gcc-ipq8064.yaml b/dts/Bindings/clock/qcom,gcc-ipq8064.yaml
new file mode 100644
index 0000000000..9eb91dd225
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-ipq8064.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on IPQ8064.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+
+properties:
+ compatible:
+ items:
+ - const: qcom,gcc-ipq8064
+ - const: syscon
+
+ clocks:
+ items:
+ - description: PXO source
+ - description: CXO source
+
+ clock-names:
+ items:
+ - const: pxo
+ - const: cxo
+
+ thermal-sensor:
+ type: object
+
+ allOf:
+ - $ref: /schemas/thermal/qcom-tsens.yaml#
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gcc: clock-controller@900000 {
+ compatible = "qcom,gcc-ipq8064", "syscon";
+ reg = <0x00900000 0x4000>;
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/clock/qcom,gcc-other.yaml b/dts/Bindings/clock/qcom,gcc-other.yaml
new file mode 100644
index 0000000000..6c45e0f854
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-other.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-ipq4019.h
+ - dt-bindings/clock/qcom,gcc-ipq6018.h
+ - dt-bindings/reset/qcom,gcc-ipq6018.h
+ - dt-bindings/clock/qcom,gcc-msm8939.h
+ - dt-bindings/clock/qcom,gcc-msm8953.h
+ - dt-bindings/reset/qcom,gcc-msm8939.h
+ - dt-bindings/clock/qcom,gcc-msm8660.h
+ - dt-bindings/reset/qcom,gcc-msm8660.h
+ - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/clock/qcom,gcc-mdm9607.h
+ - dt-bindings/clock/qcom,gcc-mdm9615.h
+ - dt-bindings/reset/qcom,gcc-mdm9615.h
+ - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
+
+allOf:
+ - $ref: "qcom,gcc.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-ipq4019
+ - qcom,gcc-ipq6018
+ - qcom,gcc-mdm9607
+ - qcom,gcc-msm8226
+ - qcom,gcc-msm8660
+ - qcom,gcc-msm8916
+ - qcom,gcc-msm8939
+ - qcom,gcc-msm8953
+ - qcom,gcc-msm8960
+ - qcom,gcc-msm8974
+ - qcom,gcc-msm8974pro
+ - qcom,gcc-msm8974pro-ac
+ - qcom,gcc-mdm9615
+ - qcom,gcc-sdm630
+ - qcom,gcc-sdm660
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ # Example for GCC for MSM8960:
+ - |
+ clock-controller@900000 {
+ compatible = "qcom,gcc-msm8960";
+ reg = <0x900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc.yaml b/dts/Bindings/clock/qcom,gcc.yaml
index f66d703bd9..2ed27a2ef4 100644
--- a/dts/Bindings/clock/qcom,gcc.yaml
+++ b/dts/Bindings/clock/qcom,gcc.yaml
@@ -4,57 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller Binding
+title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
- Qualcomm global clock control module which supports the clocks, resets and
- power domains.
-
- See also:
- - dt-bindings/clock/qcom,gcc-apq8084.h
- - dt-bindings/reset/qcom,gcc-apq8084.h
- - dt-bindings/clock/qcom,gcc-ipq4019.h
- - dt-bindings/clock/qcom,gcc-ipq6018.h
- - dt-bindings/reset/qcom,gcc-ipq6018.h
- - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/clock/qcom,gcc-msm8939.h
- - dt-bindings/clock/qcom,gcc-msm8953.h
- - dt-bindings/reset/qcom,gcc-msm8939.h
- - dt-bindings/clock/qcom,gcc-msm8660.h
- - dt-bindings/reset/qcom,gcc-msm8660.h
- - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- - dt-bindings/clock/qcom,gcc-mdm9607.h
- - dt-bindings/clock/qcom,gcc-mdm9615.h
- - dt-bindings/reset/qcom,gcc-mdm9615.h
- - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
+ Common bindings for Qualcomm global clock control module which supports
+ the clocks, resets and power domains.
properties:
- compatible:
- enum:
- - qcom,gcc-apq8084
- - qcom,gcc-ipq4019
- - qcom,gcc-ipq6018
- - qcom,gcc-ipq8064
- - qcom,gcc-mdm9607
- - qcom,gcc-msm8226
- - qcom,gcc-msm8660
- - qcom,gcc-msm8916
- - qcom,gcc-msm8939
- - qcom,gcc-msm8953
- - qcom,gcc-msm8960
- - qcom,gcc-msm8974
- - qcom,gcc-msm8974pro
- - qcom,gcc-msm8974pro-ac
- - qcom,gcc-mdm9615
- - qcom,gcc-sdm630
- - qcom,gcc-sdm660
-
'#clock-cells':
const: 1
@@ -72,22 +32,11 @@ properties:
Protected clock specifier list as per common clock binding.
required:
- - compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+additionalProperties: true
-examples:
- # Example for GCC for MSM8960:
- - |
- clock-controller@900000 {
- compatible = "qcom,gcc-msm8960";
- reg = <0x900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
...
diff --git a/dts/Bindings/clock/qcom,gpucc.yaml b/dts/Bindings/clock/qcom,gpucc.yaml
index 46dff46d57..9ebcb1943b 100644
--- a/dts/Bindings/clock/qcom,gpucc.yaml
+++ b/dts/Bindings/clock/qcom,gpucc.yaml
@@ -17,6 +17,7 @@ description: |
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
+ dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -27,6 +28,7 @@ properties:
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
+ - qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc
diff --git a/dts/Bindings/clock/qcom,mmcc.yaml b/dts/Bindings/clock/qcom,mmcc.yaml
index 68fdc3d498..4b79e89fd1 100644
--- a/dts/Bindings/clock/qcom,mmcc.yaml
+++ b/dts/Bindings/clock/qcom,mmcc.yaml
@@ -19,6 +19,7 @@ properties:
enum:
- qcom,mmcc-apq8064
- qcom,mmcc-apq8084
+ - qcom,mmcc-msm8226
- qcom,mmcc-msm8660
- qcom,mmcc-msm8960
- qcom,mmcc-msm8974
diff --git a/dts/Bindings/clock/qcom,qcm2290-dispcc.yaml b/dts/Bindings/clock/qcom,qcm2290-dispcc.yaml
new file mode 100644
index 0000000000..973e408c62
--- /dev/null
+++ b/dts/Bindings/clock/qcom,qcm2290-dispcc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
+
+maintainers:
+ - Loic Poulain <loic.poulain@linaro.org>
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on qcm2290.
+
+ See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
+
+properties:
+ compatible:
+ const: qcom,qcm2290-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board active-only XO source
+ - description: GPLL0 source from GCC
+ - description: GPLL0 div source from GCC
+ - description: Byte clock from DSI PHY
+ - description: Pixel clock from DSI PHY
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: gcc_disp_gpll0_clk_src
+ - const: gcc_disp_gpll0_div_clk_src
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
+ #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ clock-controller@5f00000 {
+ compatible = "qcom,qcm2290-dispcc";
+ reg = <0x5f00000 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "gcc_disp_gpll0_clk_src",
+ "gcc_disp_gpll0_div_clk_src",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,rpmhcc.yaml b/dts/Bindings/clock/qcom,rpmhcc.yaml
index 8406dde179..8fcaf418f8 100644
--- a/dts/Bindings/clock/qcom,rpmhcc.yaml
+++ b/dts/Bindings/clock/qcom,rpmhcc.yaml
@@ -20,6 +20,7 @@ properties:
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
+ - qcom,sc8280xp-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
diff --git a/dts/Bindings/clock/qcom,sdm845-camcc.yaml b/dts/Bindings/clock/qcom,sdm845-camcc.yaml
new file mode 100644
index 0000000000..d4239ccae9
--- /dev/null
+++ b/dts/Bindings/clock/qcom,sdm845-camcc.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller Binding for SDM845
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ Qualcomm camera clock control module which supports the clocks, resets and
+ power domains on SDM845.
+
+ See also dt-bindings/clock/qcom,camcc-sm845.h
+
+properties:
+ compatible:
+ const: qcom,sdm845-camcc
+
+ clocks:
+ items:
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@ad00000 {
+ compatible = "qcom,sdm845-camcc";
+ reg = <0x0ad00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/renesas,9series.yaml b/dts/Bindings/clock/renesas,9series.yaml
new file mode 100644
index 0000000000..102eb95cb3
--- /dev/null
+++ b/dts/Bindings/clock/renesas,9series.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for Renesas 9-series I2C PCIe clock generators
+
+description: |
+ The Renesas 9-series are I2C PCIe clock generators providing
+ from 1 to 20 output clocks.
+
+ When referencing the provided clock in the DT using phandle
+ and clock specifier, the following mapping applies:
+
+ - 9FGV0241:
+ 0 -- DIF0
+ 1 -- DIF1
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+properties:
+ compatible:
+ enum:
+ - renesas,9fgv0241
+
+ reg:
+ description: I2C device address
+ enum: [ 0x68, 0x6a ]
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: XTal input clock
+
+ renesas,out-amplitude-microvolt:
+ enum: [ 600000, 700000, 800000, 900000 ]
+ description: Output clock signal amplitude
+
+ renesas,out-spread-spectrum:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 100000, 99750, 99500 ]
+ description: Output clock down spread in pcm (1/1000 of percent)
+
+patternProperties:
+ "^DIF[0-19]$":
+ type: object
+ description:
+ Description of one of the outputs (DIF0..DIF19).
+
+ properties:
+ renesas,slew-rate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 2000000, 3000000 ]
+ description: Output clock slew rate select in V/ns
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ /* 25MHz reference crystal */
+ ref25: ref25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ i2c@0 {
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rs9: clock-generator@6a {
+ compatible = "renesas,9fgv0241";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+
+ clocks = <&ref25m>;
+
+ DIF0 {
+ renesas,slew-rate = <3000000>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/clock/renesas,cpg-div6-clock.yaml b/dts/Bindings/clock/renesas,cpg-div6-clock.yaml
index c55a7c494e..2197c952e2 100644
--- a/dts/Bindings/clock/renesas,cpg-div6-clock.yaml
+++ b/dts/Bindings/clock/renesas,cpg-div6-clock.yaml
@@ -51,6 +51,18 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a73a4-clock.h>
+
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a73a4-cpg-clocks";
+ reg = <0xe6150000 0x10000>;
+ clocks = <&extal1_clk>, <&extal2_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "main", "pll0", "pll1", "pll2",
+ "pll2s", "pll2h", "z", "z2",
+ "i", "m3", "b", "m1", "m2",
+ "zx", "zs", "hp";
+ };
+
sdhi2_clk: sdhi2_clk@e615007c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615007c 4>;
diff --git a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml
index 30b2e3d0d2..bd3af8fc61 100644
--- a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,13 +4,13 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
- On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
+ On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
@@ -22,7 +22,9 @@ description: |
properties:
compatible:
- const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ enum:
+ - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ - renesas,r9a07g054-cpg # RZ/V2L
reg:
maxItems: 1
@@ -40,9 +42,9 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- <dt-bindings/clock/r9a07g044-cpg.h>
+ <dt-bindings/clock/r9a07g*-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
- a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
+ a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 2
'#power-domain-cells':
@@ -56,7 +58,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
- the <dt-bindings/clock/r9a07g044-cpg.h>.
+ the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 1
required:
diff --git a/dts/Bindings/clock/starfive,jh7100-audclk.yaml b/dts/Bindings/clock/starfive,jh7100-audclk.yaml
new file mode 100644
index 0000000000..8f49a1ae03
--- /dev/null
+++ b/dts/Bindings/clock/starfive,jh7100-audclk.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 Audio Clock Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7100-audclk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Audio source clock
+ - description: External 12.288MHz clock
+ - description: Domain 7 AHB bus clock
+
+ clock-names:
+ items:
+ - const: audio_src
+ - const: audio_12288
+ - const: dom7ahb_bus
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive-jh7100.h>
+
+ clock-controller@10480000 {
+ compatible = "starfive,jh7100-audclk";
+ reg = <0x10480000 0x10000>;
+ clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
+ <&clkgen JH7100_CLK_AUDIO_12288>,
+ <&clkgen JH7100_CLK_DOM7AHB_BUS>;
+ clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/tesla,fsd-clock.yaml b/dts/Bindings/clock/tesla,fsd-clock.yaml
new file mode 100644
index 0000000000..dc808e2f83
--- /dev/null
+++ b/dts/Bindings/clock/tesla,fsd-clock.yaml
@@ -0,0 +1,198 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD (Full Self-Driving) SoC clock controller
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+ - linux-fsd@tesla.com
+
+description: |
+ FSD clock controller consist of several clock management unit
+ (CMU), which generates clocks for various inteernal SoC blocks.
+ The root clock comes from external OSC clock (24 MHz).
+
+ All available clocks are defined as preprocessor macros in
+ 'dt-bindings/clock/fsd-clk.h' header.
+
+properties:
+ compatible:
+ enum:
+ - tesla,fsd-clock-cmu
+ - tesla,fsd-clock-imem
+ - tesla,fsd-clock-peric
+ - tesla,fsd-clock-fsys0
+ - tesla,fsd-clock-fsys1
+ - tesla,fsd-clock-mfc
+ - tesla,fsd-clock-cam_csi
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+
+ clock-names:
+ minItems: 1
+ maxItems: 6
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-cmu
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-imem
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: IMEM TCU clock (from CMU_CMU)
+ - description: IMEM bus clock (from CMU_CMU)
+ - description: IMEM DMA clock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_imem_tcuclk
+ - const: dout_cmu_imem_aclk
+ - const: dout_cmu_imem_dmaclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-peric
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: Shared0 PLL div4 clock (from CMU_CMU)
+ - description: PERIC shared1 div36 clock (from CMU_CMU)
+ - description: PERIC shared0 div3 TBU clock (from CMU_CMU)
+ - description: PERIC shared0 div20 clock (from CMU_CMU)
+ - description: PERIC shared1 div4 DMAclock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_pll_shared0_div4
+ - const: dout_cmu_peric_shared1div36
+ - const: dout_cmu_peric_shared0div3_tbuclk
+ - const: dout_cmu_peric_shared0div20
+ - const: dout_cmu_peric_shared1div4_dmaclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-fsys0
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: Shared0 PLL div6 clock (from CMU_CMU)
+ - description: FSYS0 shared1 div4 clock (from CMU_CMU)
+ - description: FSYS0 shared0 div4 clock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_pll_shared0_div6
+ - const: dout_cmu_fsys0_shared1div4
+ - const: dout_cmu_fsys0_shared0div4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-fsys1
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: FSYS1 shared0 div8 clock (from CMU_CMU)
+ - description: FSYS1 shared0 div4 clock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_fsys1_shared0div8
+ - const: dout_cmu_fsys1_shared0div4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-mfc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-cam_csi
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ clock-names:
+ items:
+ - const: fin_pll
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_FSYS1
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+
+ clock_fsys1: clock-controller@16810000 {
+ compatible = "tesla,fsd-clock-fsys1";
+ reg = <0x16810000 0x3000>;
+ #clock-cells = <1>;
+
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_fsys1_shared0div8",
+ "dout_cmu_fsys1_shared0div4";
+ };
+
+...
diff --git a/dts/Bindings/clock/ti/ti,clksel.yaml b/dts/Bindings/clock/ti/ti,clksel.yaml
new file mode 100644
index 0000000000..c56f911fff
--- /dev/null
+++ b/dts/Bindings/clock/ti/ti,clksel.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for TI clksel clock
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description: |
+ The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
+ cases also has divider, multiplier and gate bits.
+
+properties:
+ compatible:
+ const: ti,clksel
+
+ reg:
+ maxItems: 1
+ description: The CLKSEL register range
+
+ '#address-cells':
+ enum: [ 0, 1, 2 ]
+
+ '#size-cells':
+ enum: [ 0, 1, 2 ]
+
+ ranges: true
+
+ "#clock-cells":
+ const: 2
+ description: The CLKSEL register and bit offset
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ clksel_gfx_fclk: clock@52c {
+ compatible = "ti,clksel";
+ reg = <0x25c 0x4>;
+ #clock-cells = <2>;
+ };
+...
diff --git a/dts/Bindings/connector/usb-connector.yaml b/dts/Bindings/connector/usb-connector.yaml
index 7eb8659fa6..0420fa5635 100644
--- a/dts/Bindings/connector/usb-connector.yaml
+++ b/dts/Bindings/connector/usb-connector.yaml
@@ -104,8 +104,7 @@ properties:
- "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
Type-C Cable and Connector specification, when Power Delivery is not
supported.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- default
- 1.5A
diff --git a/dts/Bindings/arm/idle-states.yaml b/dts/Bindings/cpu/idle-states.yaml
index 52bce5dbb1..fa4d4142ac 100644
--- a/dts/Bindings/arm/idle-states.yaml
+++ b/dts/Bindings/cpu/idle-states.yaml
@@ -1,25 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/idle-states.yaml#
+$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: ARM idle states binding description
+title: Idle states binding description
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ - Anup Patel <anup@brainfault.org>
description: |+
==========================================
1 - Introduction
==========================================
- ARM systems contain HW capable of managing power consumption dynamically,
- where cores can be put in different low-power states (ranging from simple wfi
- to power gating) according to OS PM policies. The CPU states representing the
- range of dynamic idle states that a processor can enter at run-time, can be
- specified through device tree bindings representing the parameters required to
- enter/exit specific idle states on a given processor.
+ ARM and RISC-V systems contain HW capable of managing power consumption
+ dynamically, where cores can be put in different low-power states (ranging
+ from simple wfi to power gating) according to OS PM policies. The CPU states
+ representing the range of dynamic idle states that a processor can enter at
+ run-time, can be specified through device tree bindings representing the
+ parameters required to enter/exit specific idle states on a given processor.
+
+ ==========================================
+ 2 - ARM idle states
+ ==========================================
According to the Server Base System Architecture document (SBSA, [3]), the
power states an ARM CPU can be put into are identified by the following list:
@@ -43,8 +48,23 @@ description: |+
The device tree binding definition for ARM idle states is the subject of this
document.
+ ==========================================
+ 3 - RISC-V idle states
+ ==========================================
+
+ On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
+ suspend (or idle) states (ranging from simple WFI, power gating, etc). The
+ RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
+ standard mechanism for OS to request HART state transitions.
+
+ The platform specific suspend (or idle) states of a hart can be either
+ retentive or non-rententive in nature. A retentive suspend state will
+ preserve HART registers and CSR values for all privilege modes whereas
+ a non-retentive suspend state will not preserve HART registers and CSR
+ values.
+
===========================================
- 2 - idle-states definitions
+ 4 - idle-states definitions
===========================================
Idle states are characterized for a specific system through a set of
@@ -211,10 +231,10 @@ description: |+
properties specification that is the subject of the following sections.
===========================================
- 3 - idle-states node
+ 5 - idle-states node
===========================================
- ARM processor idle states are defined within the idle-states node, which is
+ The processor idle states are defined within the idle-states node, which is
a direct child of the cpus node [1] and provides a container where the
processor idle states, defined as device tree nodes, are listed.
@@ -223,7 +243,7 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
- 4 - References
+ 6 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@@ -238,9 +258,15 @@ description: |+
[4] ARM Architecture Reference Manuals
http://infocenter.arm.com/help/index.jsp
- [6] ARM Linux Kernel documentation - Booting AArch64 Linux
+ [5] ARM Linux Kernel documentation - Booting AArch64 Linux
Documentation/arm64/booting.rst
+ [6] RISC-V Linux Kernel documentation - CPUs bindings
+ Documentation/devicetree/bindings/riscv/cpus.yaml
+
+ [7] RISC-V Supervisor Binary Interface (SBI)
+ http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
+
properties:
$nodename:
const: idle-states
@@ -253,7 +279,7 @@ properties:
On ARM 32-bit systems this property is optional
This assumes that the "enable-method" property is set to "psci" in the cpu
- node[6] that is responsible for setting up CPU idle management in the OS
+ node[5] that is responsible for setting up CPU idle management in the OS
implementation.
const: psci
@@ -265,8 +291,8 @@ patternProperties:
as follows.
The idle state entered by executing the wfi instruction (idle_standby
- SBSA,[3][4]) is considered standard on all ARM platforms and therefore
- must not be listed.
+ SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
+ therefore must not be listed.
In addition to the properties listed above, a state node may require
additional properties specific to the entry-method defined in the
@@ -275,7 +301,27 @@ patternProperties:
properties:
compatible:
- const: arm,idle-state
+ enum:
+ - arm,idle-state
+ - riscv,idle-state
+
+ arm,psci-suspend-param:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ power_state parameter to pass to the ARM PSCI suspend call.
+
+ Device tree nodes that require usage of PSCI CPU_SUSPEND function
+ (i.e. idle states node with entry-method property is set to "psci")
+ must specify this property.
+
+ riscv,sbi-suspend-param:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
+
+ This property is required in idle state nodes of device tree meant
+ for RISC-V systems. For more details on the suspend_type parameter
+ refer the SBI specifiation v0.3 (or higher) [7].
local-timer-stop:
description:
@@ -317,6 +363,8 @@ patternProperties:
description:
A string used as a descriptive name for the idle state.
+ additionalProperties: false
+
required:
- compatible
- entry-latency-us
@@ -337,8 +385,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@1 {
@@ -346,8 +394,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100 {
@@ -355,8 +403,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@101 {
@@ -364,8 +412,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10000 {
@@ -373,8 +421,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10000>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10001 {
@@ -382,8 +430,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10001>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10100 {
@@ -391,8 +439,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10101 {
@@ -400,8 +448,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100000000 {
@@ -409,8 +457,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x0>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000001 {
@@ -418,8 +466,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x1>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000100 {
@@ -427,8 +475,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000101 {
@@ -436,8 +484,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010000 {
@@ -445,8 +493,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10000>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010001 {
@@ -454,8 +502,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10001>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010100 {
@@ -463,8 +511,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010101 {
@@ -472,8 +520,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
idle-states {
@@ -567,56 +615,56 @@ examples:
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
idle-states {
@@ -658,4 +706,150 @@ examples:
};
};
+ - |
+ // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "riscv";
+ reg = <0x0>;
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
+
+ cpu_intc0: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "riscv";
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
+
+ cpu_intc1: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@10 {
+ device_type = "cpu";
+ compatible = "riscv";
+ reg = <0x10>;
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
+
+ cpu_intc10: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@11 {
+ device_type = "cpu";
+ compatible = "riscv";
+ reg = <0x11>;
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
+
+ cpu_intc11: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ idle-states {
+ CPU_RET_0_0: cpu-retentive-0-0 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x10000000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <80>;
+ };
+
+ CPU_NONRET_0_0: cpu-nonretentive-0-0 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x90000000>;
+ entry-latency-us = <250>;
+ exit-latency-us = <500>;
+ min-residency-us = <950>;
+ };
+
+ CLUSTER_RET_0: cluster-retentive-0 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x11000000>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <250>;
+ wakeup-latency-us = <130>;
+ };
+
+ CLUSTER_NONRET_0: cluster-nonretentive-0 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x91000000>;
+ local-timer-stop;
+ entry-latency-us = <600>;
+ exit-latency-us = <1100>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+
+ CPU_RET_1_0: cpu-retentive-1-0 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x10000010>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <80>;
+ };
+
+ CPU_NONRET_1_0: cpu-nonretentive-1-0 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x90000010>;
+ entry-latency-us = <250>;
+ exit-latency-us = <500>;
+ min-residency-us = <950>;
+ };
+
+ CLUSTER_RET_1: cluster-retentive-1 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x11000010>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <250>;
+ wakeup-latency-us = <130>;
+ };
+
+ CLUSTER_NONRET_1: cluster-nonretentive-1 {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x91000010>;
+ local-timer-stop;
+ entry-latency-us = <600>;
+ exit-latency-us = <1100>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+ };
+
...
diff --git a/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt b/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt
deleted file mode 100644
index 9299028ee7..0000000000
--- a/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt
+++ /dev/null
@@ -1,172 +0,0 @@
-Qualcomm Technologies, Inc. CPUFREQ Bindings
-
-CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
-SoCs to manage frequency in hardware. It is capable of controlling frequency
-for multiple clusters.
-
-Properties:
-- compatible
- Usage: required
- Value type: <string>
- Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
-
-- clocks
- Usage: required
- Value type: <phandle> From common clock binding.
- Definition: clock handle for XO clock and GPLL0 clock.
-
-- clock-names
- Usage: required
- Value type: <string> From common clock binding.
- Definition: must be "xo", "alternate".
-
-- reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Addresses and sizes for the memory of the HW bases in
- each frequency domain.
-- reg-names
- Usage: Optional
- Value type: <string>
- Definition: Frequency domain name i.e.
- "freq-domain0", "freq-domain1".
-
-- #freq-domain-cells:
- Usage: required.
- Definition: Number of cells in a freqency domain specifier.
-
-* Property qcom,freq-domain
-Devices supporting freq-domain must set their "qcom,freq-domain" property with
-phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
-
-
-Example:
-
-Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
-DCVS state together.
-
-/ {
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- CPU0: cpu@0 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_0: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- L3_0: l3-cache {
- compatible = "cache";
- };
- };
- };
-
- CPU1: cpu@100 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x100>;
- enable-method = "psci";
- next-level-cache = <&L2_100>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_100: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU2: cpu@200 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x200>;
- enable-method = "psci";
- next-level-cache = <&L2_200>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_200: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU3: cpu@300 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x300>;
- enable-method = "psci";
- next-level-cache = <&L2_300>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_300: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU4: cpu@400 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x400>;
- enable-method = "psci";
- next-level-cache = <&L2_400>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_400: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU5: cpu@500 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x500>;
- enable-method = "psci";
- next-level-cache = <&L2_500>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_500: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU6: cpu@600 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x600>;
- enable-method = "psci";
- next-level-cache = <&L2_600>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_600: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU7: cpu@700 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x700>;
- enable-method = "psci";
- next-level-cache = <&L2_700>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_700: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
- };
-
- soc {
- cpufreq_hw: cpufreq@17d43000 {
- compatible = "qcom,cpufreq-hw";
- reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
- reg-names = "freq-domain0", "freq-domain1";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
- clock-names = "xo", "alternate";
-
- #freq-domain-cells = <1>;
- };
-}
diff --git a/dts/Bindings/cpufreq/cpufreq-qcom-hw.yaml b/dts/Bindings/cpufreq/cpufreq-qcom-hw.yaml
new file mode 100644
index 0000000000..2f1b8b6852
--- /dev/null
+++ b/dts/Bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUFREQ
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description: |
+
+ CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
+ SoCs to manage frequency in hardware. It is capable of controlling frequency
+ for multiple clusters.
+
+properties:
+ compatible:
+ oneOf:
+ - description: v1 of CPUFREQ HW
+ items:
+ - const: qcom,cpufreq-hw
+
+ - description: v2 of CPUFREQ HW (EPSS)
+ items:
+ - enum:
+ - qcom,sm8250-cpufreq-epss
+ - const: qcom,cpufreq-epss
+
+ reg:
+ minItems: 2
+ items:
+ - description: Frequency domain 0 register region
+ - description: Frequency domain 1 register region
+ - description: Frequency domain 2 register region
+
+ reg-names:
+ minItems: 2
+ items:
+ - const: freq-domain0
+ - const: freq-domain1
+ - const: freq-domain2
+
+ clocks:
+ items:
+ - description: XO Clock
+ - description: GPLL0 Clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: alternate
+
+ '#freq-domain-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#freq-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
+ // switch DCVS state together.
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpufreq@17d43000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
+ reg-names = "freq-domain0", "freq-domain1";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/dts/Bindings/cpufreq/qcom-cpufreq-nvmem.yaml
new file mode 100644
index 0000000000..a9a776da55
--- /dev/null
+++ b/dts/Bindings/cpufreq/qcom-cpufreq-nvmem.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
+
+maintainers:
+ - Ilia Lin <ilia.lin@kernel.org>
+
+description: |
+ In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
+ voltage is dynamically configured by Core Power Reduction (CPR) depending on
+ current CPU frequency and efuse values.
+ CPR provides a power domain with multiple levels that are selected depending
+ on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
+ according to the required OPPs defined in the CPU OPP tables.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs404
+ required:
+ - compatible
+
+properties:
+ cpus:
+ type: object
+
+ patternProperties:
+ 'cpu@[0-9a-f]+':
+ type: object
+
+ properties:
+ power-domains:
+ maxItems: 1
+
+ power-domain-names:
+ items:
+ - const: cpr
+
+ required:
+ - power-domains
+ - power-domain-names
+
+patternProperties:
+ '^opp-table(-[a-z0-9]+)?$':
+ if:
+ properties:
+ compatible:
+ const: operating-points-v2-kryo-cpu
+ then:
+ patternProperties:
+ '^opp-?[0-9]+$':
+ required:
+ - required-opps
+
+additionalProperties: true
+
+examples:
+ - |
+ / {
+ model = "Qualcomm Technologies, Inc. QCS404";
+ compatible = "qcom,qcs404";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+ };
+
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ opp-shared;
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cpr_opp1>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ required-opps = <&cpr_opp2>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ required-opps = <&cpr_opp3>;
+ };
+ };
+
+ cpr_opp_table: opp-table-cpr {
+ compatible = "operating-points-v2-qcom-level";
+
+ cpr_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+ cpr_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+ cpr_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <3>;
+ };
+ };
+ };
diff --git a/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml b/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml
new file mode 100644
index 0000000000..0ccaab16dc
--- /dev/null
+++ b/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator
+
+maintainers:
+ - Tudor Ambarus <tudor.ambarus@microchip.com>
+
+properties:
+ compatible:
+ const: atmel,at91sam9g46-aes
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: aes_clk
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/dma/at91.h>
+
+ aes: crypto@e1810000 {
+ compatible = "atmel,at91sam9g46-aes";
+ reg = <0xe1810000 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
+ clock-names = "aes_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ };
diff --git a/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml b/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml
new file mode 100644
index 0000000000..5163c51b45
--- /dev/null
+++ b/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
+
+maintainers:
+ - Tudor Ambarus <tudor.ambarus@microchip.com>
+
+properties:
+ compatible:
+ const: atmel,at91sam9g46-sha
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: sha_clk
+
+ dmas:
+ maxItems: 1
+ description: TX DMA Channel
+
+ dma-names:
+ const: tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/dma/at91.h>
+
+ sha: crypto@e1814000 {
+ compatible = "atmel,at91sam9g46-sha";
+ reg = <0xe1814000 0x100>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
+ clock-names = "sha_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
+ dma-names = "tx";
+ };
diff --git a/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml b/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml
new file mode 100644
index 0000000000..fcc5adf03c
--- /dev/null
+++ b/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-tdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator
+
+maintainers:
+ - Tudor Ambarus <tudor.ambarus@microchip.com>
+
+properties:
+ compatible:
+ const: atmel,at91sam9g46-tdes
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: tdes_clk
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/dma/at91.h>
+
+ tdes: crypto@e2014000 {
+ compatible = "atmel,at91sam9g46-tdes";
+ reg = <0xe2014000 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
+ clock-names = "tdes_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
+ <&dma0 AT91_XDMAC_DT_PERID(53)>;
+ dma-names = "tx", "rx";
+ };
diff --git a/dts/Bindings/crypto/atmel-crypto.txt b/dts/Bindings/crypto/atmel-crypto.txt
deleted file mode 100644
index f2aab3dc2b..0000000000
--- a/dts/Bindings/crypto/atmel-crypto.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-* Atmel HW cryptographic accelerators
-
-These are the HW cryptographic accelerators found on some Atmel products.
-
-* Advanced Encryption Standard (AES)
-
-Required properties:
-- compatible : Should be "atmel,at91sam9g46-aes".
-- reg: Should contain AES registers location and length.
-- interrupts: Should contain the IRQ line for the AES.
-- dmas: List of two DMA specifiers as described in
- atmel-dma.txt and dma.txt files.
-- dma-names: Contains one identifier string for each DMA specifier
- in the dmas property.
-
-Example:
-aes@f8038000 {
- compatible = "atmel,at91sam9g46-aes";
- reg = <0xf8038000 0x100>;
- interrupts = <43 4 0>;
- dmas = <&dma1 2 18>,
- <&dma1 2 19>;
- dma-names = "tx", "rx";
-
-* Triple Data Encryption Standard (Triple DES)
-
-Required properties:
-- compatible : Should be "atmel,at91sam9g46-tdes".
-- reg: Should contain TDES registers location and length.
-- interrupts: Should contain the IRQ line for the TDES.
-
-Optional properties:
-- dmas: List of two DMA specifiers as described in
- atmel-dma.txt and dma.txt files.
-- dma-names: Contains one identifier string for each DMA specifier
- in the dmas property.
-
-Example:
-tdes@f803c000 {
- compatible = "atmel,at91sam9g46-tdes";
- reg = <0xf803c000 0x100>;
- interrupts = <44 4 0>;
- dmas = <&dma1 2 20>,
- <&dma1 2 21>;
- dma-names = "tx", "rx";
-};
-
-* Secure Hash Algorithm (SHA)
-
-Required properties:
-- compatible : Should be "atmel,at91sam9g46-sha".
-- reg: Should contain SHA registers location and length.
-- interrupts: Should contain the IRQ line for the SHA.
-
-Optional properties:
-- dmas: One DMA specifiers as described in
- atmel-dma.txt and dma.txt files.
-- dma-names: Contains one identifier string for each DMA specifier
- in the dmas property. Only one "tx" string needed.
-
-Example:
-sha@f8034000 {
- compatible = "atmel,at91sam9g46-sha";
- reg = <0xf8034000 0x100>;
- interrupts = <42 4 0>;
- dmas = <&dma1 2 17>;
- dma-names = "tx";
-};
diff --git a/dts/Bindings/crypto/intel,ixp4xx-crypto.yaml b/dts/Bindings/crypto/intel,ixp4xx-crypto.yaml
index 9c53c27bd2..e0fe639578 100644
--- a/dts/Bindings/crypto/intel,ixp4xx-crypto.yaml
+++ b/dts/Bindings/crypto/intel,ixp4xx-crypto.yaml
@@ -22,19 +22,28 @@ properties:
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the NPE this crypto engine
+ - description: the NPE instance number
description: phandle to the NPE this crypto engine is using, the cell
describing the NPE instance to be used.
queue-rx:
$ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the RX queue on the NPE
+ - description: the queue instance number
description: phandle to the RX queue on the NPE, the cell describing
the queue instance to be used.
queue-txready:
$ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the TX READY queue on the NPE
+ - description: the queue instance number
description: phandle to the TX READY queue on the NPE, the cell describing
the queue instance to be used.
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml
index e77523b02f..d4412aea7b 100644
--- a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml
+++ b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml
@@ -69,6 +69,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
+ items:
+ maxItems: 1
description: |
Available display engine frontends (DE 1.0) or mixers (DE
2.0/3.0) available.
diff --git a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml
index a1d5a32660..a9d34dd7bb 100644
--- a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml
+++ b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml
@@ -72,8 +72,7 @@ properties:
- const: hpd-removed
ddc:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description: >
Phandle of the I2C controller used for DDC EDID probing
diff --git a/dts/Bindings/display/bridge/adi,adv7511.yaml b/dts/Bindings/display/bridge/adi,adv7511.yaml
index d3dd7a79b9..f08a01dfed 100644
--- a/dts/Bindings/display/bridge/adi,adv7511.yaml
+++ b/dts/Bindings/display/bridge/adi,adv7511.yaml
@@ -76,9 +76,8 @@ properties:
adi,input-depth:
description: Number of bits per color component at the input.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [ 8, 10, 12 ]
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 8, 10, 12 ]
adi,input-colorspace:
description: Input color space.
diff --git a/dts/Bindings/display/bridge/analogix,anx7625.yaml b/dts/Bindings/display/bridge/analogix,anx7625.yaml
index 25b5ef3f75..35a4851583 100644
--- a/dts/Bindings/display/bridge/analogix,anx7625.yaml
+++ b/dts/Bindings/display/bridge/analogix,anx7625.yaml
@@ -83,6 +83,9 @@ properties:
type: boolean
description: let the driver enable audio HDMI codec function or not.
+ aux-bus:
+ $ref: /schemas/display/dp-aux-bus.yaml#
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -150,5 +153,19 @@ examples:
};
};
};
+
+ aux-bus {
+ panel {
+ compatible = "innolux,n125hce-gn1";
+ power-supply = <&pp3300_disp_x>;
+ backlight = <&backlight_lcd0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&anx7625_out>;
+ };
+ };
+ };
+ };
};
};
diff --git a/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml b/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml
new file mode 100644
index 0000000000..b8219eab44
--- /dev/null
+++ b/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 HDMI Transmitter
+
+maintainers:
+ - H. Nikolaus Schaller <hns@goldelico.com>
+
+description: |
+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
+ TX controller IP with accompanying PHY IP.
+
+allOf:
+ - $ref: synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ const: ingenic,jz4780-dw-hdmi
+
+ reg-io-width:
+ const: 4
+
+ clocks:
+ maxItems: 2
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input from LCD controller output.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Link to the HDMI connector.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - ports
+ - reg-io-width
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
+
+ hdmi: hdmi@10180000 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x10180000 0x8000>;
+ reg-io-width = <4>;
+ ddc-i2c-bus = <&i2c4>;
+ interrupt-parent = <&intc>;
+ interrupts = <3>;
+ clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in: port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <&jz4780_lcd_out>;
+ };
+ };
+ hdmi_out: port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml
index 5079c1cc33..3a8614e0f6 100644
--- a/dts/Bindings/display/bridge/lvds-codec.yaml
+++ b/dts/Bindings/display/bridge/lvds-codec.yaml
@@ -39,6 +39,7 @@ properties:
- const: lvds-encoder # Generic LVDS encoder compatible fallback
- items:
- enum:
+ - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
- const: lvds-decoder # Generic LVDS decoders compatible fallback
- enum:
@@ -67,7 +68,7 @@ properties:
- vesa-24
description: |
The color signals mapping order. See details in
- Documentation/devicetree/bindings/display/panel/lvds.yaml
+ Documentation/devicetree/bindings/display/lvds.yaml
port@1:
$ref: /schemas/graph.yaml#/properties/port
diff --git a/dts/Bindings/display/bridge/renesas,lvds.yaml b/dts/Bindings/display/bridge/renesas,lvds.yaml
index acfc327f70..a51baf8a4c 100644
--- a/dts/Bindings/display/bridge/renesas,lvds.yaml
+++ b/dts/Bindings/display/bridge/renesas,lvds.yaml
@@ -28,6 +28,7 @@ properties:
- renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
- renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
- renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
+ - renesas,r8a77961-lvds # for R-Car M3-W+ compatible LVDS encoders
- renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
- renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
- renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
diff --git a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml
index 9be44a682e..b00246faea 100644
--- a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml
+++ b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -26,9 +26,8 @@ properties:
reg-io-width:
description:
Width (in bytes) of the registers specified by the reg property.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [1, 4]
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 4]
default: 1
clocks:
diff --git a/dts/Bindings/display/bridge/ti,sn65dsi83.yaml b/dts/Bindings/display/bridge/ti,sn65dsi83.yaml
index b446d0f0f1..48a97bb3e2 100644
--- a/dts/Bindings/display/bridge/ti,sn65dsi83.yaml
+++ b/dts/Bindings/display/bridge/ti,sn65dsi83.yaml
@@ -32,6 +32,9 @@ properties:
maxItems: 1
description: GPIO specifier for bridge_en pin (active high).
+ vcc-supply:
+ description: A 1.8V power supply (see regulator/regulator.yaml).
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -91,7 +94,6 @@ properties:
required:
- compatible
- reg
- - enable-gpios
- ports
allOf:
@@ -133,6 +135,7 @@ examples:
reg = <0x2d>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&reg_sn65dsi83_1v8>;
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/display/bridge/toshiba,tc358768.yaml b/dts/Bindings/display/bridge/toshiba,tc358768.yaml
index eacfe71650..3bd670b8e5 100644
--- a/dts/Bindings/display/bridge/toshiba,tc358768.yaml
+++ b/dts/Bindings/display/bridge/toshiba,tc358768.yaml
@@ -77,7 +77,10 @@ required:
- vddio-supply
- ports
-additionalProperties: false
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
+unevaluatedProperties: false
examples:
- |
@@ -87,7 +90,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- dsi_bridge: dsi-bridge@e {
+ dsi_bridge: dsi@e {
compatible = "toshiba,tc358768";
reg = <0xe>;
diff --git a/dts/Bindings/display/exynos/exynos-mic.txt b/dts/Bindings/display/exynos/exynos-mic.txt
deleted file mode 100644
index 0fba2ee644..0000000000
--- a/dts/Bindings/display/exynos/exynos-mic.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-Device-Tree bindings for Samsung Exynos SoC mobile image compressor (MIC)
-
-MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is
-not capable to transfer high resoltuion frame data as decon can send. MIC
-solves this problem by compressing the frame data by 1/2 before it is
-transferred through mipi dsi. The compressed frame data must be uncompressed in
-the panel PCB.
-
-Required properties:
-- compatible: value should be "samsung,exynos5433-mic".
-- reg: physical base address and length of the MIC registers set and system
- register of mic.
-- clocks: must include clock specifiers corresponding to entries in the
- clock-names property.
-- clock-names: list of clock names sorted in the same order as the clocks
- property. Must contain "pclk_mic0", "sclk_rgb_vclk_to_mic0".
-- samsung,disp-syscon: the reference node for syscon for DISP block.
-- ports: contains a port which is connected to decon node and dsi node.
- address-cells and size-cells must 1 and 0, respectively.
-- port: contains an endpoint node which is connected to the endpoint in the
- decon node or dsi node. The reg value must be 0 and 1 respectively.
-
-Example:
-SoC specific DT entry:
-mic: mic@13930000 {
- compatible = "samsung,exynos5433-mic";
- reg = <0x13930000 0x48>;
- clocks = <&cmu_disp CLK_PCLK_MIC0>,
- <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
- clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
- samsung,disp-syscon = <&syscon_disp>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- mic_to_decon: endpoint {
- remote-endpoint = <&decon_to_mic>;
- };
- };
-
- port@1 {
- reg = <1>;
- mic_to_dsi: endpoint {
- remote-endpoint = <&dsi_to_mic>;
- };
- };
- };
-};
diff --git a/dts/Bindings/display/exynos/exynos5433-decon.txt b/dts/Bindings/display/exynos/exynos5433-decon.txt
deleted file mode 100644
index 775193e1c6..0000000000
--- a/dts/Bindings/display/exynos/exynos5433-decon.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-Device-Tree bindings for Samsung Exynos SoC display controller (DECON)
-
-DECON (Display and Enhancement Controller) is the Display Controller for the
-Exynos series of SoCs which transfers the image data from a video memory
-buffer to an external LCD interface.
-
-Required properties:
-- compatible: value should be one of:
- "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
-- reg: physical base address and length of the DECON registers set.
-- interrupt-names: should contain the interrupt names depending on mode of work:
- video mode: "vsync",
- command mode: "lcd_sys",
- command mode with software trigger: "lcd_sys", "te".
-- interrupts or interrupts-extended: list of interrupt specifiers corresponding
- to names privided in interrupt-names, as described in
- interrupt-controller/interrupts.txt
-- clocks: must include clock specifiers corresponding to entries in the
- clock-names property.
-- clock-names: list of clock names sorted in the same order as the clocks
- property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
- "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",
- "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",
- "sclk_decon_eclk"
-- ports: contains a port which is connected to mic node. address-cells and
- size-cells must 1 and 0, respectively.
-- port: contains an endpoint node which is connected to the endpoint in the mic
- node. The reg value muset be 0.
-
-Example:
-SoC specific DT entry:
-decon: decon@13800000 {
- compatible = "samsung,exynos5433-decon";
- reg = <0x13800000 0x2104>;
- clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
- <&cmu_disp CLK_ACLK_XIU_DECON0X>,
- <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
- <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
- <&cmu_disp CLK_ACLK_XIU_DECON1X>,
- <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
- <&cmu_disp CLK_SCLK_DECON_VCLK>,
- <&cmu_disp CLK_SCLK_DECON_ECLK>;
- clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
- "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",
- "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";
- interrupt-names = "vsync", "lcd_sys";
- interrupts = <0 202 0>, <0 203 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- decon_to_mic: endpoint {
- remote-endpoint = <&mic_to_decon>;
- };
- };
- };
-};
diff --git a/dts/Bindings/display/exynos/exynos7-decon.txt b/dts/Bindings/display/exynos/exynos7-decon.txt
deleted file mode 100644
index 53912c99ec..0000000000
--- a/dts/Bindings/display/exynos/exynos7-decon.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
-
-DECON (Display and Enhancement Controller) is the Display Controller for the
-Exynos7 series of SoCs which transfers the image data from a video memory
-buffer to an external LCD interface.
-
-Required properties:
-- compatible: value should be "samsung,exynos7-decon";
-
-- reg: physical base address and length of the DECON registers set.
-
-- interrupts: should contain a list of all DECON IP block interrupts in the
- order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
- format depends on the interrupt controller used.
-
-- interrupt-names: should contain the interrupt names: "fifo", "vsync",
- "lcd_sys", in the same order as they were listed in the interrupts
- property.
-
-- pinctrl-0: pin control group to be used for this controller.
-
-- pinctrl-names: must contain a "default" entry.
-
-- clocks: must include clock specifiers corresponding to entries in the
- clock-names property.
-
-- clock-names: list of clock names sorted in the same order as the clocks
- property. Must contain "pclk_decon0", "aclk_decon0",
- "decon0_eclk", "decon0_vclk".
-- i80-if-timings: timing configuration for lcd i80 interface support.
-
-Optional Properties:
-- power-domains: a phandle to DECON power domain node.
-- display-timings: timing settings for DECON, as described in document [1].
- Can be used in case timings cannot be provided otherwise
- or to override timings provided by the panel.
-
-[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
-
-Example:
-
-SoC specific DT entry:
-
- decon@13930000 {
- compatible = "samsung,exynos7-decon";
- interrupt-parent = <&combiner>;
- reg = <0x13930000 0x1000>;
- interrupt-names = "lcd_sys", "vsync", "fifo";
- interrupts = <0 188 0>, <0 189 0>, <0 190 0>;
- clocks = <&clock_disp PCLK_DECON_INT>,
- <&clock_disp ACLK_DECON_INT>,
- <&clock_disp SCLK_DECON_INT_ECLK>,
- <&clock_disp SCLK_DECON_INT_EXTCLKPLL>;
- clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk",
- "decon0_vclk";
- status = "disabled";
- };
-
-Board specific DT entry:
-
- decon@13930000 {
- pinctrl-0 = <&lcd_clk &pwm1_out>;
- pinctrl-names = "default";
- status = "okay";
- };
diff --git a/dts/Bindings/display/exynos/exynos_hdmi.txt b/dts/Bindings/display/exynos/exynos_hdmi.txt
deleted file mode 100644
index 58b12e25bb..0000000000
--- a/dts/Bindings/display/exynos/exynos_hdmi.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-Device-Tree bindings for drm hdmi driver
-
-Required properties:
-- compatible: value should be one among the following:
- 1) "samsung,exynos4210-hdmi"
- 2) "samsung,exynos4212-hdmi"
- 3) "samsung,exynos5420-hdmi"
- 4) "samsung,exynos5433-hdmi"
-- reg: physical base address of the hdmi and length of memory mapped
- region.
-- interrupts: interrupt number to the cpu.
-- hpd-gpios: following information about the hotplug gpio pin.
- a) phandle of the gpio controller node.
- b) pin number within the gpio controller.
- c) optional flags and pull up/down.
-- ddc: phandle to the hdmi ddc node
-- phy: phandle to the hdmi phy node
-- samsung,syscon-phandle: phandle for system controller node for PMU.
-- #sound-dai-cells: should be 0.
-
-Required properties for Exynos 4210, 4212, 5420 and 5433:
-- clocks: list of clock IDs from SoC clock driver.
- a) hdmi: Gate of HDMI IP bus clock.
- b) sclk_hdmi: Gate of HDMI special clock.
- c) sclk_pixel: Pixel special clock, one of the two possible inputs of
- HDMI clock mux.
- d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of
- HDMI clock mux.
- e) mout_hdmi: It is required by the driver to switch between the 2
- parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
- after configuration, parent is set to sclk_hdmiphy else
- sclk_pixel.
-- clock-names: aliases as per driver requirements for above clock IDs:
- "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
-
-Required properties for Exynos 5433:
-- clocks: list of clock specifiers according to common clock bindings.
- a) hdmi_pclk: Gate of HDMI IP APB bus.
- b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
- d) i_tmds_clk: Gate of HDMI TMDS clock.
- e) i_pixel_clk: Gate of HDMI pixel clock.
- f) i_spdif_clk: Gate of HDMI SPDIF clock.
- g) oscclk: Oscillator clock, used as parent of following *_user clocks
- in case HDMI-PHY is not operational.
- h) tmds_clko: TMDS clock generated by HDMI-PHY.
- i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
- respectively if HDMI-PHY is off and operational.
- j) pixel_clko: Pixel clock generated by HDMI-PHY.
- k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
- respectively if HDMI-PHY is off and operational.
-- clock-names: aliases for above clock specfiers.
-- samsung,sysreg: handle to syscon used to control the system registers.
-
-Example:
-
- hdmi {
- compatible = "samsung,exynos4212-hdmi";
- reg = <0x14530000 0x100000>;
- interrupts = <0 95 0>;
- hpd-gpios = <&gpx3 7 1>;
- ddc = <&hdmi_ddc_node>;
- phy = <&hdmi_phy_node>;
- samsung,syscon-phandle = <&pmu_system_controller>;
- };
diff --git a/dts/Bindings/display/exynos/exynos_hdmiddc.txt b/dts/Bindings/display/exynos/exynos_hdmiddc.txt
deleted file mode 100644
index 41eee97156..0000000000
--- a/dts/Bindings/display/exynos/exynos_hdmiddc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Device-Tree bindings for hdmiddc driver
-
-Required properties:
-- compatible: value should be one of the following
- 1) "samsung,exynos5-hdmiddc" <DEPRECATED>
- 2) "samsung,exynos4210-hdmiddc"
-
-- reg: I2C address of the hdmiddc device.
-
-Example:
-
- hdmiddc {
- compatible = "samsung,exynos4210-hdmiddc";
- reg = <0x50>;
- };
diff --git a/dts/Bindings/display/exynos/exynos_hdmiphy.txt b/dts/Bindings/display/exynos/exynos_hdmiphy.txt
deleted file mode 100644
index 162f641f76..0000000000
--- a/dts/Bindings/display/exynos/exynos_hdmiphy.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Device-Tree bindings for hdmiphy driver
-
-Required properties:
-- compatible: value should be one of the following:
- 1) "samsung,exynos5-hdmiphy" <DEPRECATED>
- 2) "samsung,exynos4210-hdmiphy".
- 3) "samsung,exynos4212-hdmiphy".
-- reg: I2C address of the hdmiphy device.
-
-Example:
-
- hdmiphy {
- compatible = "samsung,exynos4210-hdmiphy";
- reg = <0x38>;
- };
diff --git a/dts/Bindings/display/exynos/exynos_mixer.txt b/dts/Bindings/display/exynos/exynos_mixer.txt
deleted file mode 100644
index 3e38128f86..0000000000
--- a/dts/Bindings/display/exynos/exynos_mixer.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Device-Tree bindings for mixer driver
-
-Required properties:
-- compatible: value should be one of the following:
- 1) "samsung,exynos5-mixer" <DEPRECATED>
- 2) "samsung,exynos4210-mixer"
- 3) "samsung,exynos4212-mixer"
- 4) "samsung,exynos5250-mixer"
- 5) "samsung,exynos5420-mixer"
-
-- reg: physical base address of the mixer and length of memory mapped
- region.
-- interrupts: interrupt number to the cpu.
-- clocks: list of clock IDs from SoC clock driver.
- a) mixer: Gate of Mixer IP bus clock.
- b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of
- mixer mux.
- c) hdmi: Gate of HDMI IP bus clock, needed together with sclk_hdmi.
-
-Example:
-
- mixer {
- compatible = "samsung,exynos5250-mixer";
- reg = <0x14450000 0x10000>;
- interrupts = <0 94 0>;
- };
diff --git a/dts/Bindings/display/exynos/samsung-fimd.txt b/dts/Bindings/display/exynos/samsung-fimd.txt
deleted file mode 100644
index b3096421d4..0000000000
--- a/dts/Bindings/display/exynos/samsung-fimd.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-Device-Tree bindings for Samsung SoC display controller (FIMD)
-
-FIMD (Fully Interactive Mobile Display) is the Display Controller for the
-Samsung series of SoCs which transfers the image data from a video memory
-buffer to an external LCD interface.
-
-Required properties:
-- compatible: value should be one of the following
- "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
- "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
- "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
- "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
- "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
- "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
- "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
-
-- reg: physical base address and length of the FIMD registers set.
-
-- interrupts: should contain a list of all FIMD IP block interrupts in the
- order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
- format depends on the interrupt controller used.
-
-- interrupt-names: should contain the interrupt names: "fifo", "vsync",
- "lcd_sys", in the same order as they were listed in the interrupts
- property.
-
-- pinctrl-0: pin control group to be used for this controller.
-
-- pinctrl-names: must contain a "default" entry.
-
-- clocks: must include clock specifiers corresponding to entries in the
- clock-names property.
-
-- clock-names: list of clock names sorted in the same order as the clocks
- property. Must contain "sclk_fimd" and "fimd".
-
-Optional Properties:
-- power-domains: a phandle to FIMD power domain node.
-- samsung,invert-vden: video enable signal is inverted
-- samsung,invert-vclk: video clock signal is inverted
-- display-timings: timing settings for FIMD, as described in document [1].
- Can be used in case timings cannot be provided otherwise
- or to override timings provided by the panel.
-- samsung,sysreg: handle to syscon used to control the system registers
-- i80-if-timings: timing configuration for lcd i80 interface support.
- - cs-setup: clock cycles for the active period of address signal is enabled
- until chip select is enabled.
- If not specified, the default value(0) will be used.
- - wr-setup: clock cycles for the active period of CS signal is enabled until
- write signal is enabled.
- If not specified, the default value(0) will be used.
- - wr-active: clock cycles for the active period of CS is enabled.
- If not specified, the default value(1) will be used.
- - wr-hold: clock cycles for the active period of CS is disabled until write
- signal is disabled.
- If not specified, the default value(0) will be used.
-
- The parameters are defined as:
-
- VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
- : : : : :
- Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
- | cs-setup+1 | : : :
- |<---------->| : : :
- Chip Select ???????????????|____________:____________:____________|??
- | wr-setup+1 | | wr-hold+1 |
- |<---------->| |<---------->|
- Write Enable ????????????????????????????|____________|???????????????
- | wr-active+1|
- |<---------->|
- Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
-
-The device node can contain 'port' child nodes according to the bindings defined
-in [2]. The following are properties specific to those nodes:
-- reg: (required) port index, can be:
- 0 - for CAMIF0 input,
- 1 - for CAMIF1 input,
- 2 - for CAMIF2 input,
- 3 - for parallel output,
- 4 - for write-back interface
-
-[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
-[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
-
-SoC specific DT entry:
-
- fimd@11c00000 {
- compatible = "samsung,exynos4210-fimd";
- interrupt-parent = <&combiner>;
- reg = <0x11c00000 0x20000>;
- interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <11 0>, <11 1>, <11 2>;
- clocks = <&clock 140>, <&clock 283>;
- clock-names = "sclk_fimd", "fimd";
- power-domains = <&pd_lcd0>;
- status = "disabled";
- };
-
-Board specific DT entry:
-
- fimd@11c00000 {
- pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
- pinctrl-names = "default";
- status = "okay";
- };
diff --git a/dts/Bindings/display/panel/lvds.yaml b/dts/Bindings/display/lvds.yaml
index 49460c9dce..7cd2ce7e9c 100644
--- a/dts/Bindings/display/panel/lvds.yaml
+++ b/dts/Bindings/display/lvds.yaml
@@ -1,10 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/panel/lvds.yaml#
+$id: http://devicetree.org/schemas/display/lvds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: LVDS Display Panel
+title: LVDS Display Common Properties
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
@@ -13,8 +13,8 @@ maintainers:
description: |+
LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
incompatible data link layers have been used over time to transmit image data
- to LVDS panels. This bindings supports display panels compatible with the
- following specifications.
+ to LVDS devices. This bindings supports devices compatible with the following
+ specifications.
[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
@@ -26,18 +26,7 @@ description: |+
Device compatible with those specifications have been marketed under the
FPD-Link and FlatLink brands.
-allOf:
- - $ref: panel-common.yaml#
-
properties:
- compatible:
- contains:
- const: panel-lvds
- description:
- Shall contain "panel-lvds" in addition to a mandatory panel-specific
- compatible string defined in individual panel bindings. The "panel-lvds"
- value shall never be used on its own.
-
data-mapping:
enum:
- jeida-18
@@ -96,22 +85,6 @@ properties:
If set, reverse the bit order described in the data mappings below on all
data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
- port: true
- ports: true
-
-required:
- - compatible
- - data-mapping
- - width-mm
- - height-mm
- - panel-timing
-
-oneOf:
- - required:
- - port
- - required:
- - ports
-
additionalProperties: true
...
diff --git a/dts/Bindings/display/mediatek/mediatek,aal.yaml b/dts/Bindings/display/mediatek/mediatek,aal.yaml
new file mode 100644
index 0000000000..61f0ed1e38
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,aal.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display adaptive ambient light processor
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display adaptive ambient light processor, namely AAL,
+ is responsible for backlight power saving and sunlight visibility improving.
+ AAL device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-aal
+ - items:
+ - enum:
+ - mediatek,mt2712-disp-aal
+ - mediatek,mt8183-disp-aal
+ - mediatek,mt8192-disp-aal
+ - mediatek,mt8195-disp-aal
+ - enum:
+ - mediatek,mt8173-disp-aal
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: AAL Clock
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aal@14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,ccorr.yaml b/dts/Bindings/display/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 0000000000..0ed53b6238
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display color correction
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display color correction, namely CCORR, reproduces correct color
+ on panels with different color gamut.
+ CCORR device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-disp-ccorr
+ - items:
+ - const: mediatek,mt8192-disp-ccorr
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-ccorr
+ - enum:
+ - mediatek,mt8192-disp-ccorr
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: CCORR Clock
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,color.yaml b/dts/Bindings/display/mediatek/mediatek,color.yaml
new file mode 100644
index 0000000000..3ad842eb56
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,color.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display color processor
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display color processor, namely COLOR, provides hue, luma and
+ saturation adjustments to get better picture quality and to have one panel
+ resemble the other in their output characteristics.
+ COLOR device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-color
+ - items:
+ - const: mediatek,mt8167-disp-color
+ - items:
+ - const: mediatek,mt8173-disp-color
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-color
+ - mediatek,mt2712-disp-color
+ - enum:
+ - mediatek,mt2701-disp-color
+ - items:
+ - enum:
+ - mediatek,mt8183-disp-color
+ - mediatek,mt8192-disp-color
+ - mediatek,mt8195-disp-color
+ - enum:
+ - mediatek,mt8173-disp-color
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: COLOR Clock
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ color0: color@14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt
deleted file mode 100644
index 78044c340e..0000000000
--- a/dts/Bindings/display/mediatek/mediatek,disp.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-Mediatek display subsystem
-==========================
-
-The Mediatek display subsystem consists of various DISP function blocks in the
-MMSYS register space. The connections between them can be configured by output
-and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
-of frame signal are distributed to the other function blocks by a DISP_MUTEX
-function block.
-
-All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
-For a description of the MMSYS_CONFIG binding, see
-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
-
-DISP function blocks
-====================
-
-A display stream starts at a source function block that reads pixel data from
-memory and ends with a sink function block that drives pixels on a display
-interface, or writes pixels back to memory. All DISP function blocks have
-their own register space, interrupt, and clock gate. The blocks that can
-access memory additionally have to list the IOMMU and local arbiter they are
-connected to.
-
-For a description of the display interface sink function blocks, see
-Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
-Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
-
-Required properties (all function blocks):
-- compatible: "mediatek,<chip>-disp-<function>", one of
- "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
- "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
- "mediatek,<chip>-disp-rdma" - read DMA / line buffer
- "mediatek,<chip>-disp-wdma" - write DMA
- "mediatek,<chip>-disp-ccorr" - color correction
- "mediatek,<chip>-disp-color" - color processor
- "mediatek,<chip>-disp-dither" - dither
- "mediatek,<chip>-disp-aal" - adaptive ambient light controller
- "mediatek,<chip>-disp-gamma" - gamma correction
- "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
- "mediatek,<chip>-disp-postmask" - control round corner for display frame
- "mediatek,<chip>-disp-split" - split stream to two encoders
- "mediatek,<chip>-disp-ufoe" - data compression engine
- "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
- "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
- "mediatek,<chip>-disp-mutex" - display mutex
- "mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
-- reg: Physical base address and length of the function block register space
-- interrupts: The interrupt signal from the function block (required, except for
- merge and split function blocks).
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- For most function blocks this is just a single clock input. Only the DSI and
- DPI controller nodes have multiple clock inputs. These are documented in
- mediatek,dsi.txt and mediatek,dpi.txt, respectively.
- An exception is that the mt8183 mutex is always free running with no clocks property.
-
-Required properties (DMA function blocks):
-- compatible: Should be one of
- "mediatek,<chip>-disp-ovl"
- "mediatek,<chip>-disp-rdma"
- "mediatek,<chip>-disp-wdma"
- the supported chips are mt2701, mt8167 and mt8173.
-- larb: Should contain a phandle pointing to the local arbiter device as defined
- in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
-- iommus: Should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
- for details.
-
-Optional properties (RDMA function blocks):
-- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
- property to the corresponding rdma
- the value is the Max value which defined in hardware data sheet.
- mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
- mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
- mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
-
-Examples:
-
-mmsys: clock-controller@14000000 {
- compatible = "mediatek,mt8173-mmsys", "syscon";
- reg = <0 0x14000000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- #clock-cells = <1>;
-};
-
-ovl0: ovl@1400c000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400c000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL0>;
- iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
-};
-
-ovl1: ovl@1400d000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400d000 0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL1>;
- iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
-};
-
-rdma0: rdma@1400e000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400e000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA0>;
- iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
- mediatek,rdma-fifosize = <8192>;
-};
-
-rdma1: rdma@1400f000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA1>;
- iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
-};
-
-rdma2: rdma@14010000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x14010000 0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA2>;
- iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
-};
-
-wdma0: wdma@14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
-};
-
-wdma1: wdma@14012000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14012000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA1>;
- iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
-};
-
-color0: color@14013000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14013000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR0>;
-};
-
-color1: color@14014000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14014000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR1>;
-};
-
-aal@14015000 {
- compatible = "mediatek,mt8173-disp-aal";
- reg = <0 0x14015000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_AAL>;
-};
-
-gamma@14016000 {
- compatible = "mediatek,mt8173-disp-gamma";
- reg = <0 0x14016000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_GAMMA>;
-};
-
-ufoe@1401a000 {
- compatible = "mediatek,mt8173-disp-ufoe";
- reg = <0 0x1401a000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_UFOE>;
-};
-
-dsi0: dsi@1401b000 {
- /* See mediatek,dsi.txt for details */
-};
-
-dpi0: dpi@1401d000 {
- /* See mediatek,dpi.txt for details */
-};
-
-mutex: mutex@14020000 {
- compatible = "mediatek,mt8173-disp-mutex";
- reg = <0 0x14020000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --git a/dts/Bindings/display/mediatek/mediatek,dither.yaml b/dts/Bindings/display/mediatek/mediatek,dither.yaml
new file mode 100644
index 0000000000..6657549af1
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,dither.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display dither processor
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display dither processor, namely DITHER, works by approximating
+ unavailable colors with available colors and by mixing and matching available
+ colors to mimic unavailable ones.
+ DITHER device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-disp-dither
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-dither
+ - mediatek,mt8195-disp-dither
+ - enum:
+ - mediatek,mt8183-disp-dither
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: DITHER Clock
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.yaml b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
index dd2896a40f..843f89d605 100644
--- a/dts/Bindings/display/mediatek/mediatek,dpi.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
@@ -70,8 +70,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
+
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
diff --git a/dts/Bindings/display/mediatek/mediatek,dsc.yaml b/dts/Bindings/display/mediatek/mediatek,dsc.yaml
new file mode 100644
index 0000000000..4924886451
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,dsc.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display DSC controller
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ The DSC standard is a specification of the algorithms used for
+ compressing and decompressing image display streams, including
+ the specification of the syntax and semantics of the compressed
+ video bit stream. DSC is designed for real-time systems with
+ real-time compression, transmission, decompression and Display.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-disp-dsc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: DSC Wrapper Clock
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each subsys id is mapping to a base address of display function blocks
+ register which is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,gamma.yaml b/dts/Bindings/display/mediatek/mediatek,gamma.yaml
new file mode 100644
index 0000000000..7844233931
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,gamma.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display gamma correction
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display gamma correction, namely GAMMA, provides a nonlinear
+ operation used to adjust luminance in display system.
+ GAMMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-gamma
+ - items:
+ - const: mediatek,mt8183-disp-gamma
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-gamma
+ - mediatek,mt8195-disp-gamma
+ - enum:
+ - mediatek,mt8183-disp-gamma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: GAMMA Clock
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gamma@14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,hdmi.yaml b/dts/Bindings/display/mediatek/mediatek,hdmi.yaml
index 111967efa9..bdaf0b51e6 100644
--- a/dts/Bindings/display/mediatek/mediatek,hdmi.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,hdmi.yaml
@@ -51,7 +51,10 @@ properties:
mediatek,syscon-hdmi:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to system configuration registers
+ - description: register offset in the system configuration registers
description: |
phandle link and register offset to the system configuration registers.
diff --git a/dts/Bindings/display/mediatek/mediatek,merge.yaml b/dts/Bindings/display/mediatek/mediatek,merge.yaml
new file mode 100644
index 0000000000..d635c5dcb6
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,merge.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display merge
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display merge, namely MERGE, is used to merge two slice-per-line
+ inputs into one side-by-side output.
+ MERGE device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-merge
+ - items:
+ - const: mediatek,mt8195-disp-merge
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: merge
+ - items:
+ - const: merge
+ - const: merge_async
+
+ mediatek,merge-fifo-en:
+ description:
+ The setting of merge fifo is mainly provided for the display latency
+ buffer to ensure that the back-end panel display data will not be
+ underrun, a little more data is needed in the fifo.
+ According to the merge fifo settings, when the water level is detected
+ to be insufficient, it will trigger RDMA sending ultra and preulra
+ command to SMI to speed up the data rate.
+ type: boolean
+
+ mediatek,merge-mute:
+ description: Support mute function. Mute the content of merge output.
+ type: boolean
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+ resets:
+ description: reset controller
+ See Documentation/devicetree/bindings/reset/reset.txt for details.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ merge@14017000 {
+ compatible = "mediatek,mt8173-disp-merge";
+ reg = <0 0x14017000 0 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_MERGE>;
+ clock-names = "merge";
+ };
+ };
+
diff --git a/dts/Bindings/display/mediatek/mediatek,mutex.yaml b/dts/Bindings/display/mediatek/mediatek,mutex.yaml
new file mode 100644
index 0000000000..00e6a1041a
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,mutex.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek mutex
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek mutex, namely MUTEX, is used to send the triggers signals called
+ Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
+ data path or MDP data path.
+ In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
+ the shadow register.
+ MUTEX device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-mutex
+ - items:
+ - const: mediatek,mt2712-disp-mutex
+ - items:
+ - const: mediatek,mt8167-disp-mutex
+ - items:
+ - const: mediatek,mt8173-disp-mutex
+ - items:
+ - const: mediatek,mt8183-disp-mutex
+ - items:
+ - const: mediatek,mt8192-disp-mutex
+ - items:
+ - const: mediatek,mt8195-disp-mutex
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: MUTEX Clock
+
+ mediatek,gce-events:
+ description:
+ The event id which is mapping to the specific hardware event signal
+ to gce. The event id is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mutex: mutex@14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+ <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,od.yaml b/dts/Bindings/display/mediatek/mediatek,od.yaml
new file mode 100644
index 0000000000..853fcb9db2
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,od.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overdirve
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display overdrive, namely OD, increases the transition values
+ of pixels between consecutive frames to make LCD rotate faster.
+ OD device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2712-disp-od
+ - items:
+ - const: mediatek,mt8173-disp-od
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: OD Clock
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ od@14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml b/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml
new file mode 100644
index 0000000000..da999ba53b
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overlay 2 layer
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
+ for OVL.
+ OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-disp-ovl-2l
+ - items:
+ - const: mediatek,mt8192-disp-ovl-2l
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: OVL-2L Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/Bindings/display/mediatek/mediatek,ovl.yaml
new file mode 100644
index 0000000000..f77094e614
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overlay
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display overlay, namely OVL, can do alpha blending from
+ the memory.
+ OVL device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-ovl
+ - items:
+ - const: mediatek,mt8173-disp-ovl
+ - items:
+ - const: mediatek,mt8183-disp-ovl
+ - items:
+ - const: mediatek,mt8192-disp-ovl
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-ovl
+ - mediatek,mt2712-disp-ovl
+ - enum:
+ - mediatek,mt2701-disp-ovl
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-ovl
+ - enum:
+ - mediatek,mt8183-disp-ovl
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: OVL Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,postmask.yaml b/dts/Bindings/display/mediatek/mediatek,postmask.yaml
new file mode 100644
index 0000000000..2d769422e2
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,postmask.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display postmask
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display postmask, namely POSTMASK, provides round corner pattern
+ generation.
+ POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8192-disp-postmask
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: POSTMASK Clock
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8192-clk.h>
+ #include <dt-bindings/power/mt8192-power.h>
+ #include <dt-bindings/gce/mt8192-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,rdma.yaml b/dts/Bindings/display/mediatek/mediatek,rdma.yaml
new file mode 100644
index 0000000000..e8c72afa06
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,rdma.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek Read Direct Memory Access(RDMA) component used to read the
+ data into DMA. It provides real time data to the back-end panel
+ driver, such as DSI, DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-rdma
+ - items:
+ - const: mediatek,mt8173-disp-rdma
+ - items:
+ - const: mediatek,mt8183-disp-rdma
+ - items:
+ - const: mediatek,mt8195-disp-rdma
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-rdma
+ - mediatek,mt2712-disp-rdma
+ - enum:
+ - mediatek,mt2701-disp-rdma
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-rdma
+ - enum:
+ - mediatek,mt8183-disp-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,rdma-fifo-size:
+ description:
+ rdma fifo size may be different even in same SOC, add this property to the
+ corresponding rdma.
+ The value below is the Max value which defined in hardware data sheet
+ mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+ mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+ mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8192, 5120, 2048]
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,rdma-fifo-size = <8192>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,split.yaml b/dts/Bindings/display/mediatek/mediatek,split.yaml
new file mode 100644
index 0000000000..35ace1f322
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,split.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display split
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display split, namely SPLIT, is used to split stream to two
+ encoders.
+ SPLIT device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-split
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: SPLIT Clock
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ split0: split@14018000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14018000 0 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,ufoe.yaml b/dts/Bindings/display/mediatek/mediatek,ufoe.yaml
new file mode 100644
index 0000000000..b8bb135fe9
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,ufoe.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display UFOe
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek display UFOe stands for Unified Frame Optimization engine.
+ UFOe can cut the data rate for DSI port which may lead to reduce power
+ consumption.
+ UFOe device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-ufoe
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: UFOe Clock
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ufoe@1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,wdma.yaml b/dts/Bindings/display/mediatek/mediatek,wdma.yaml
new file mode 100644
index 0000000000..7d7cc1ab52
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ Mediatek Write Direct Memory Access(WDMA) component used to write
+ the data into DMA.
+ WDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-wdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: WDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ };
+ };
diff --git a/dts/Bindings/display/msm/dp-controller.yaml b/dts/Bindings/display/msm/dp-controller.yaml
index 5457612ab1..cd05cfd765 100644
--- a/dts/Bindings/display/msm/dp-controller.yaml
+++ b/dts/Bindings/display/msm/dp-controller.yaml
@@ -21,6 +21,7 @@ properties:
- qcom,sc7280-edp
- qcom,sc8180x-dp
- qcom,sc8180x-edp
+ - qcom,sm8350-dp
reg:
items:
diff --git a/dts/Bindings/display/msm/dpu-msm8998.yaml b/dts/Bindings/display/msm/dpu-msm8998.yaml
new file mode 100644
index 0000000000..2df64afb76
--- /dev/null
+++ b/dts/Bindings/display/msm/dpu-msm8998.yaml
@@ -0,0 +1,219 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for MSM8998 target
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for MSM8998 target.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,msm8998-mdss
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Display AXI clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+
+ ranges: true
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ description: Node containing the properties of DPU.
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,msm8998-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for regdma register set
+ - description: Address offset and size for vbif register set
+ - description: Address offset and size for non-realtime vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: regdma
+ - const: vbif
+ - const: vbif_nrt
+
+ clocks:
+ items:
+ - description: Display ahb clock
+ - description: Display axi clock
+ - description: Display mem-noc clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: mnoc
+ - const: core
+ - const: vsync
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2: true
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF1 (DSI1)
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF2 (DSI2)
+
+ required:
+ - port@0
+ - port@1
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - interrupts
+ - power-domains
+ - operating-points-v2
+ - ports
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ mdss: display-subsystem@c900000 {
+ compatible = "qcom,msm8998-mdss";
+ reg = <0x0c900000 0x1000>;
+ reg-names = "mdss";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ #address-cells = <1>;
+ #interrupt-cells = <1>;
+ #size-cells = <1>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ iommus = <&mmss_smmu 0>;
+
+ power-domains = <&mmcc MDSS_GDSC>;
+ ranges;
+
+ display-controller@c901000 {
+ compatible = "qcom,msm8998-dpu";
+ reg = <0x0c901000 0x8f000>,
+ <0x0c9a8e00 0xf0>,
+ <0x0c9b0000 0x2008>,
+ <0x0c9b8000 0x1040>;
+ reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MNOC_AHB_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "mnoc", "core", "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd MSM8998_VDDMX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/msm/dpu-qcm2290.yaml b/dts/Bindings/display/msm/dpu-qcm2290.yaml
new file mode 100644
index 0000000000..d31483a78e
--- /dev/null
+++ b/dts/Bindings/display/msm/dpu-qcm2290.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for QCM2290 target
+
+maintainers:
+ - Loic Poulain <loic.poulain@linaro.org>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
+ and DPU are mentioned for QCM2290 target.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,qcm2290-mdss
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
+
+ ranges: true
+
+ interconnects:
+ items:
+ - description: Interconnect path specifying the port ids for data bus
+
+ interconnect-names:
+ const: mdp0-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ description: Node containing the properties of DPU.
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,qcm2290-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display AXI clock from gcc
+ - description: Display AHB clock from dispcc
+ - description: Display core clock from dispcc
+ - description: Display lut clock from dispcc
+ - description: Display vsync clock from dispcc
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: core
+ - const: lut
+ - const: vsync
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2: true
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF1 (DSI1)
+
+ required:
+ - port@0
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - interrupts
+ - power-domains
+ - operating-points-v2
+ - ports
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
+ #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,qcm2290.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ mdss: mdss@5e00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,qcm2290-mdss", "qcom,mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
+ interconnect-names = "mdp0-mem";
+
+ iommus = <&apps_smmu 0x420 0x2>,
+ <&apps_smmu 0x421 0x0>;
+ ranges;
+
+ mdss_mdp: mdp@5e01000 {
+ compatible = "qcom,qcm2290-dpu";
+ reg = <0x05e01000 0x8f000>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "core", "lut", "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd QCM2290_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/msm/dsi-controller-main.yaml b/dts/Bindings/display/msm/dsi-controller-main.yaml
index 35426fde86..7095ec3c89 100644
--- a/dts/Bindings/display/msm/dsi-controller-main.yaml
+++ b/dts/Bindings/display/msm/dsi-controller-main.yaml
@@ -14,8 +14,9 @@ allOf:
properties:
compatible:
- items:
- - const: qcom,mdss-dsi-ctrl
+ enum:
+ - qcom,mdss-dsi-ctrl
+ - qcom,dsi-ctrl-6g-qcm2290
reg:
maxItems: 1
diff --git a/dts/Bindings/display/msm/dsi-phy-10nm.yaml b/dts/Bindings/display/msm/dsi-phy-10nm.yaml
index 4399715953..2d5a766d02 100644
--- a/dts/Bindings/display/msm/dsi-phy-10nm.yaml
+++ b/dts/Bindings/display/msm/dsi-phy-10nm.yaml
@@ -35,6 +35,38 @@ properties:
Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
+ qcom,phy-rescode-offset-top:
+ $ref: /schemas/types.yaml#/definitions/int8-array
+ minItems: 5
+ maxItems: 5
+ description:
+ Integer array of offset for pull-up legs rescode for all five lanes.
+ To offset the drive strength from the calibrated value in an increasing
+ manner, -32 is the weakest and +31 is the strongest.
+ items:
+ minimum: -32
+ maximum: 31
+
+ qcom,phy-rescode-offset-bot:
+ $ref: /schemas/types.yaml#/definitions/int8-array
+ minItems: 5
+ maxItems: 5
+ description:
+ Integer array of offset for pull-down legs rescode for all five lanes.
+ To offset the drive strength from the calibrated value in a decreasing
+ manner, -32 is the weakest and +31 is the strongest.
+ items:
+ minimum: -32
+ maximum: 31
+
+ qcom,phy-drive-ldo-level:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description:
+ The PHY LDO has an amplitude tuning feature to adjust the LDO output
+ for the HSTX drive. Use supported levels (mV) to offset the drive level
+ from the default value.
+ enum: [ 375, 400, 425, 450, 475, 500 ]
+
required:
- compatible
- reg
@@ -64,5 +96,9 @@ examples:
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
+
+ qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
+ qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
+ qcom,phy-drive-ldo-level = <400>;
};
...
diff --git a/dts/Bindings/display/msm/gpu.yaml b/dts/Bindings/display/msm/gpu.yaml
index 99a1ba3ada..3397bc31d0 100644
--- a/dts/Bindings/display/msm/gpu.yaml
+++ b/dts/Bindings/display/msm/gpu.yaml
@@ -64,6 +64,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
+ items:
+ maxItems: 1
description: |
phandles to one or more reserved on-chip SRAM regions.
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
diff --git a/dts/Bindings/display/msm/mdp4.txt b/dts/Bindings/display/msm/mdp4.txt
deleted file mode 100644
index b07eeb38f7..0000000000
--- a/dts/Bindings/display/msm/mdp4.txt
+++ /dev/null
@@ -1,114 +0,0 @@
-Qualcomm adreno/snapdragon MDP4 display controller
-
-Description:
-
-This is the bindings documentation for the MDP4 display controller found in
-SoCs like MSM8960, APQ8064 and MSM8660.
-
-Required properties:
-- compatible:
- * "qcom,mdp4" - mdp4
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The interrupt signal from the display controller.
-- clocks: device clocks
- See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required.
- * "core_clk"
- * "iface_clk"
- * "bus_clk"
- * "lut_clk"
- * "hdmi_clk"
- * "tv_clk"
-- ports: contains the list of output ports from MDP. These connect to interfaces
- that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
- special case since it is a part of the MDP block itself).
-
- Each output port contains an endpoint that describes how it is connected to an
- external interface. These are described by the standard properties documented
- here:
- Documentation/devicetree/bindings/graph.txt
- Documentation/devicetree/bindings/media/video-interfaces.txt
-
- The output port mappings are:
- Port 0 -> LCDC/LVDS
- Port 1 -> DSI1 Cmd/Video
- Port 2 -> DSI2 Cmd/Video
- Port 3 -> DTV
-
-Optional properties:
-- clock-names: the following clocks are optional:
- * "lut_clk"
-- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be
- used for LCDC. This is only valid for 18bpp panels.
-
-Example:
-
-/ {
- ...
-
- hdmi: hdmi@4a00000 {
- ...
- ports {
- ...
- port@0 {
- reg = <0>;
- hdmi_in: endpoint {
- remote-endpoint = <&mdp_dtv_out>;
- };
- };
- ...
- };
- ...
- };
-
- ...
-
- mdp: mdp@5100000 {
- compatible = "qcom,mdp4";
- reg = <0x05100000 0xf0000>;
- interrupts = <GIC_SPI 75 0>;
- clock-names =
- "core_clk",
- "iface_clk",
- "lut_clk",
- "hdmi_clk",
- "tv_clk";
- clocks =
- <&mmcc MDP_CLK>,
- <&mmcc MDP_AHB_CLK>,
- <&mmcc MDP_AXI_CLK>,
- <&mmcc MDP_LUT_CLK>,
- <&mmcc HDMI_TV_CLK>,
- <&mmcc MDP_TV_CLK>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- mdp_lvds_out: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
- mdp_dsi1_out: endpoint {
- };
- };
-
- port@2 {
- reg = <2>;
- mdp_dsi2_out: endpoint {
- };
- };
-
- port@3 {
- reg = <3>;
- mdp_dtv_out: endpoint {
- remote-endpoint = <&hdmi_in>;
- };
- };
- };
- };
-};
diff --git a/dts/Bindings/display/msm/mdp4.yaml b/dts/Bindings/display/msm/mdp4.yaml
new file mode 100644
index 0000000000..f63f60fea2
--- /dev/null
+++ b/dts/Bindings/display/msm/mdp4.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Adreno/Snapdragon MDP4 display controller
+
+description: >
+ MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
+
+maintainers:
+ - Rob Clark <robdclark@gmail.com>
+
+properties:
+ compatible:
+ const: qcom,mdp4
+
+ clocks:
+ minItems: 6
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: core_clk
+ - const: iface_clk
+ - const: bus_clk
+ - const: lut_clk
+ - const: hdmi_clk
+ - const: tv_clk
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: LCDC/LVDS
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DSI1 Cmd / Video
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DSI2 Cmd / Video
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Digital TV
+
+ qcom,lcdc-align-lsb:
+ type: boolean
+ description: >
+ Indication that LSB alignment should be used for LCDC.
+ This is only valid for 18bpp panels.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ mdp: mdp@5100000 {
+ compatible = "qcom,mdp4";
+ reg = <0x05100000 0xf0000>;
+ interrupts = <0 75 0>;
+ clock-names =
+ "core_clk",
+ "iface_clk",
+ "bus_clk",
+ "lut_clk",
+ "hdmi_clk",
+ "tv_clk";
+ clocks =
+ <&mmcc 77>,
+ <&mmcc 86>,
+ <&mmcc 102>,
+ <&mmcc 75>,
+ <&mmcc 97>,
+ <&mmcc 12>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp_lvds_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdp_dsi1_out: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ mdp_dsi2_out: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ mdp_dtv_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/advantech,idk-1110wr.yaml b/dts/Bindings/display/panel/advantech,idk-1110wr.yaml
index 93878c2cd3..3a8c2c11f9 100644
--- a/dts/Bindings/display/panel/advantech,idk-1110wr.yaml
+++ b/dts/Bindings/display/panel/advantech,idk-1110wr.yaml
@@ -11,13 +11,23 @@ maintainers:
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- - $ref: lvds.yaml#
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/display/lvds.yaml/#
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: advantech,idk-1110wr
+
+ required:
+ - compatible
properties:
compatible:
items:
- const: advantech,idk-1110wr
- - {} # panel-lvds, but not listed here to avoid false select
+ - const: panel-lvds
data-mapping:
const: jeida-24
@@ -35,6 +45,11 @@ additionalProperties: false
required:
- compatible
+ - data-mapping
+ - width-mm
+ - height-mm
+ - panel-timing
+ - port
examples:
- |+
diff --git a/dts/Bindings/display/panel/display-timings.yaml b/dts/Bindings/display/panel/display-timings.yaml
index 56903ded00..6d30575819 100644
--- a/dts/Bindings/display/panel/display-timings.yaml
+++ b/dts/Bindings/display/panel/display-timings.yaml
@@ -31,8 +31,7 @@ properties:
patternProperties:
"^timing":
type: object
- allOf:
- - $ref: panel-timing.yaml#
+ $ref: panel-timing.yaml#
additionalProperties: false
diff --git a/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml b/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml
index a69681e724..566e11f6bf 100644
--- a/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml
+++ b/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml
@@ -11,15 +11,26 @@ maintainers:
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- - $ref: lvds.yaml#
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/display/lvds.yaml/#
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: innolux,ee101ia-01d
+
+ required:
+ - compatible
properties:
compatible:
items:
- const: innolux,ee101ia-01d
- - {} # panel-lvds, but not listed here to avoid false select
+ - const: panel-lvds
backlight: true
+ data-mapping: true
enable-gpios: true
power-supply: true
width-mm: true
@@ -27,5 +38,13 @@ properties:
panel-timing: true
port: true
+required:
+ - compatible
+ - data-mapping
+ - width-mm
+ - height-mm
+ - panel-timing
+ - port
+
additionalProperties: false
...
diff --git a/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml b/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml
index 3715882b63..3f6efbb942 100644
--- a/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml
+++ b/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Leadtek LTK050H3146W 5.0in 720x1280 DSI panel
maintainers:
- - Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
+ - Quentin Schulz <quentin.schulz@theobroma-systems.com>
allOf:
- $ref: panel-common.yaml#
diff --git a/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml b/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml
index b5e7ee230f..5cf3c588f4 100644
--- a/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml
+++ b/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml
@@ -11,13 +11,23 @@ maintainers:
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- - $ref: lvds.yaml#
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/display/lvds.yaml/#
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: mitsubishi,aa104xd12
+
+ required:
+ - compatible
properties:
compatible:
items:
- const: mitsubishi,aa104xd12
- - {} # panel-lvds, but not listed here to avoid false select
+ - const: panel-lvds
vcc-supply:
description: Reference to the regulator powering the panel VCC pins.
@@ -39,6 +49,11 @@ additionalProperties: false
required:
- compatible
- vcc-supply
+ - data-mapping
+ - width-mm
+ - height-mm
+ - panel-timing
+ - port
examples:
- |+
diff --git a/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml b/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml
index 977c50a85b..54750cc544 100644
--- a/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml
+++ b/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml
@@ -11,13 +11,23 @@ maintainers:
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- - $ref: lvds.yaml#
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/display/lvds.yaml/#
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: mitsubishi,aa121td01
+
+ required:
+ - compatible
properties:
compatible:
items:
- const: mitsubishi,aa121td01
- - {} # panel-lvds, but not listed here to avoid false select
+ - const: panel-lvds
vcc-supply:
description: Reference to the regulator powering the panel VCC pins.
@@ -39,6 +49,11 @@ additionalProperties: false
required:
- compatible
- vcc-supply
+ - data-mapping
+ - width-mm
+ - height-mm
+ - panel-timing
+ - port
examples:
- |+
diff --git a/dts/Bindings/display/panel/panel-lvds.yaml b/dts/Bindings/display/panel/panel-lvds.yaml
new file mode 100644
index 0000000000..fcc50db6a8
--- /dev/null
+++ b/dts/Bindings/display/panel/panel-lvds.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic LVDS Display Panel Device Tree Bindings
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/display/lvds.yaml/#
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: panel-lvds
+
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - advantech,idk-1110wr
+ - advantech,idk-2121wr
+ - innolux,ee101ia-01d
+ - mitsubishi,aa104xd12
+ - mitsubishi,aa121td01
+ - sgd,gktw70sdae4se
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - auo,b101ew05
+ - tbs,a711-panel
+
+ - const: panel-lvds
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - data-mapping
+ - width-mm
+ - height-mm
+ - panel-timing
+ - port
+
+...
diff --git a/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml b/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml
new file mode 100644
index 0000000000..f29789994b
--- /dev/null
+++ b/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPI DBI SPI Panel
+
+maintainers:
+ - Noralf Trønnes <noralf@tronnes.org>
+
+description: |
+ This binding is for display panels using a MIPI DBI compatible controller
+ in SPI mode.
+
+ The MIPI Alliance Standard for Display Bus Interface defines the electrical
+ and logical interfaces for display controllers historically used in mobile
+ phones. The standard defines 4 display architecture types and this binding is
+ for type 1 which has full frame memory. There are 3 interface types in the
+ standard and type C is the serial interface.
+
+ The standard defines the following interface signals for type C:
+ - Power:
+ - Vdd: Power supply for display module
+ - Vddi: Logic level supply for interface signals
+ Combined into one in this binding called: power-supply
+ - Interface:
+ - CSx: Chip select
+ - SCL: Serial clock
+ - Dout: Serial out
+ - Din: Serial in
+ - SDA: Bidrectional in/out
+ - D/CX: Data/command selection, high=data, low=command
+ Called dc-gpios in this binding.
+ - RESX: Reset when low
+ Called reset-gpios in this binding.
+
+ The type C interface has 3 options:
+
+ - Option 1: 9-bit mode and D/CX as the 9th bit
+ | Command | the next command or following data |
+ |<0><D7><D6><D5><D4><D3><D2><D1><D0>|<D/CX><D7><D6><D5><D4><D3><D2><D1><D0>|
+
+ - Option 2: 16-bit mode and D/CX as a 9th bit
+ | Command or data |
+ |<X><X><X><X><X><X><X><D/CX><D7><D6><D5><D4><D3><D2><D1><D0>|
+
+ - Option 3: 8-bit mode and D/CX as a separate interface line
+ | Command or data |
+ |<D7><D6><D5><D4><D3><D2><D1><D0>|
+
+ The panel resolution is specified using the panel-timing node properties
+ hactive (width) and vactive (height). The other mandatory panel-timing
+ properties should be set to zero except clock-frequency which can be
+ optionally set to inform about the actual pixel clock frequency.
+
+ If the panel is wired to the controller at an offset specify this using
+ hback-porch (x-offset) and vback-porch (y-offset).
+
+allOf:
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sainsmart18
+ - const: panel-mipi-dbi-spi
+
+ write-only:
+ type: boolean
+ description:
+ Controller is not readable (ie. Din (MISO on the SPI interface) is not
+ wired up).
+
+ dc-gpios:
+ maxItems: 1
+ description: |
+ Controller data/command selection (D/CX) in 4-line SPI mode.
+ If not set, the controller is in 3-line SPI mode.
+
+required:
+ - compatible
+ - reg
+ - panel-timing
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0{
+ compatible = "sainsmart18", "panel-mipi-dbi-spi";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+
+ dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ write-only;
+
+ backlight = <&backlight>;
+
+ width-mm = <35>;
+ height-mm = <28>;
+
+ panel-timing {
+ hactive = <160>;
+ vactive = <128>;
+ hback-porch = <0>;
+ vback-porch = <0>;
+ clock-frequency = <0>;
+ hfront-porch = <0>;
+ hsync-len = <0>;
+ vfront-porch = <0>;
+ vsync-len = <0>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml
index 62f5f050c1..1eb9dd4f8f 100644
--- a/dts/Bindings/display/panel/panel-simple.yaml
+++ b/dts/Bindings/display/panel/panel-simple.yaml
@@ -222,6 +222,8 @@ properties:
- logictechno,lttd800480070-l6wh-rt
# Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
- mitsubishi,aa070mc01-ca1
+ # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module
+ - multi-inno,mi0700s4t-6
# Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
- multi-inno,mi1010ait-1cp
# NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
@@ -282,6 +284,8 @@ properties:
- sharp,lq101k1ly04
# Sharp 12.3" (2400x1600 pixels) TFT LCD panel
- sharp,lq123p1jx31
+ # Sharp 14" (1920x1080 pixels) TFT LCD panel
+ - sharp,lq140m1jw46
# Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel
- sharp,ls020b1dd01d
# Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel
diff --git a/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml b/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml
index e63a570ae5..44e02decdf 100644
--- a/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml
+++ b/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml
@@ -11,13 +11,23 @@ maintainers:
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- - $ref: lvds.yaml#
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/display/lvds.yaml/#
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: sgd,gktw70sdae4se
+
+ required:
+ - compatible
properties:
compatible:
items:
- const: sgd,gktw70sdae4se
- - {} # panel-lvds, but not listed here to avoid false select
+ - const: panel-lvds
data-mapping:
const: jeida-18
@@ -35,6 +45,11 @@ additionalProperties: false
required:
- compatible
+ - port
+ - data-mapping
+ - width-mm
+ - height-mm
+ - panel-timing
examples:
- |+
diff --git a/dts/Bindings/display/panel/sony,acx424akp.yaml b/dts/Bindings/display/panel/sony,acx424akp.yaml
index 78d0600970..059cc6dbcf 100644
--- a/dts/Bindings/display/panel/sony,acx424akp.yaml
+++ b/dts/Bindings/display/panel/sony,acx424akp.yaml
@@ -4,7 +4,12 @@
$id: http://devicetree.org/schemas/display/panel/sony,acx424akp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Sony ACX424AKP 4" 480x864 AMOLED panel
+title: Sony ACX424AKP/ACX424AKM 4" 480x864/480x854 AMOLED panel
+
+description: The Sony ACX424AKP and ACX424AKM are panels built around
+ the Novatek NT35560 display controller. The only difference is that
+ the AKM is configured to use 10 pixels less in the Y axis than the
+ AKP.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
@@ -14,7 +19,9 @@ allOf:
properties:
compatible:
- const: sony,acx424akp
+ enum:
+ - sony,acx424akp
+ - sony,acx424akm
reg: true
reset-gpios: true
vddi-supply:
diff --git a/dts/Bindings/display/renesas,du.yaml b/dts/Bindings/display/renesas,du.yaml
index 13efea5745..56cedcd6d5 100644
--- a/dts/Bindings/display/renesas,du.yaml
+++ b/dts/Bindings/display/renesas,du.yaml
@@ -76,17 +76,21 @@ properties:
renesas,cmms:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ maxItems: 1
description:
A list of phandles to the CMM instances present in the SoC, one for each
available DU channel.
renesas,vsps:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ items:
+ - description: phandle to VSP instance that serves the DU channel
+ - description: Channel index identifying the LIF instance in that VSP
description:
A list of phandle and channel index tuples to the VSPs that handle the
- memory interfaces for the DU channels. The phandle identifies the VSP
- instance that serves the DU channel, and the channel index identifies
- the LIF instance in that VSP.
+ memory interfaces for the DU channels.
required:
- compatible
diff --git a/dts/Bindings/display/rockchip/rockchip-drm.yaml b/dts/Bindings/display/rockchip/rockchip-drm.yaml
index 7204da5eb4..a8d18a37cb 100644
--- a/dts/Bindings/display/rockchip/rockchip-drm.yaml
+++ b/dts/Bindings/display/rockchip/rockchip-drm.yaml
@@ -21,6 +21,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
Should contain a list of phandles pointing to display interface port
of vop devices. vop definitions as defined in
diff --git a/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml b/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
new file mode 100644
index 0000000000..f998a3a5b7
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC HDMI DDC
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: samsung,exynos4210-hdmiddc
+ - const: samsung,exynos5-hdmiddc
+ deprecated: true
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddc@50 {
+ compatible = "samsung,exynos4210-hdmiddc";
+ reg = <0x50>;
+ };
+ };
diff --git a/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml b/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml
new file mode 100644
index 0000000000..cb8e735ce3
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml
@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC HDMI
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos4210-hdmi
+ - samsung,exynos4212-hdmi
+ - samsung,exynos5420-hdmi
+ - samsung,exynos5433-hdmi
+
+ clocks:
+ minItems: 5
+ maxItems: 10
+
+ clock-names:
+ minItems: 5
+ maxItems: 10
+
+ ddc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the HDMI DDC node.
+
+ hdmi-en-supply:
+ description:
+ Provides voltage source for DCC lines available on HDMI connector. When
+ there is no power provided for DDC epprom, some TV-sets do not pulls up
+ HPD (hot plug detect) line, what causes HDMI block to stay turned off.
+ When provided, the regulator allows TV-set correctly signal HPD event.
+
+ hpd-gpios:
+ maxItems: 1
+ description:
+ A GPIO line connected to HPD
+
+ interrupts:
+ maxItems: 1
+
+ phy:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the HDMI PHY node.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description:
+ Contains a port which is connected to mic node.
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ samsung,syscon-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the PMU system controller node.
+
+ samsung,sysreg-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to DISP system controller interface.
+
+ '#sound-dai-cells':
+ const: 0
+
+ vdd-supply:
+ description:
+ VDD 1.0V HDMI TX.
+
+ vdd_osc-supply:
+ description:
+ VDD 1.8V HDMI OSC.
+
+ vdd_pll-supply:
+ description:
+ VDD 1.0V HDMI PLL.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - ddc
+ - hpd-gpios
+ - interrupts
+ - phy
+ - reg
+ - samsung,syscon-phandle
+ - '#sound-dai-cells'
+ - vdd-supply
+ - vdd_osc-supply
+ - vdd_pll-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-hdmi
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Gate of HDMI IP APB bus.
+ - description: Gate of HDMI-PHY IP APB bus.
+ - description: Gate of HDMI TMDS clock.
+ - description: Gate of HDMI pixel clock.
+ - description: TMDS clock generated by HDMI-PHY.
+ - description: MUX used to switch between oscclk and tmds_clko,
+ respectively if HDMI-PHY is off and operational.
+ - description: Pixel clock generated by HDMI-PHY.
+ - description: MUX used to switch between oscclk and pixel_clko,
+ respectively if HDMI-PHY is off and operational.
+ - description: Oscillator clock, used as parent of following *_user
+ clocks in case HDMI-PHY is not operational.
+ - description: Gate of HDMI SPDIF clock.
+ clock-names:
+ items:
+ - const: hdmi_pclk
+ - const: hdmi_i_pclk
+ - const: i_tmds_clk
+ - const: i_pixel_clk
+ - const: tmds_clko
+ - const: tmds_clko_user
+ - const: pixel_clko
+ - const: pixel_clko_user
+ - const: oscclk
+ - const: i_spdif_clk
+ required:
+ - samsung,sysreg-phandle
+ else:
+ properties:
+ clocks:
+ items:
+ - description: Gate of HDMI IP bus clock.
+ - description: Gate of HDMI special clock.
+ - description: Pixel special clock, one of the two possible inputs
+ of HDMI clock mux.
+ - description: HDMI PHY clock output, one of two possible inputs of
+ HDMI clock mux.
+ - description: It is required by the driver to switch between the 2
+ parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
+ after configuration, parent is set to sclk_hdmiphy else
+ sclk_pixel.
+ clock-names:
+ items:
+ - const: hdmi
+ - const: sclk_hdmi
+ - const: sclk_pixel
+ - const: sclk_hdmiphy
+ - const: mout_hdmi
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ hdmi@13970000 {
+ compatible = "samsung,exynos5433-hdmi";
+ reg = <0x13970000 0x70000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_disp CLK_PCLK_HDMI>,
+ <&cmu_disp CLK_PCLK_HDMIPHY>,
+ <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
+ <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
+ <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
+ <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
+ <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
+ <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
+ <&xxti>,
+ <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
+ clock-names = "hdmi_pclk",
+ "hdmi_i_pclk",
+ "i_tmds_clk",
+ "i_pixel_clk",
+ "tmds_clko",
+ "tmds_clko_user",
+ "pixel_clko",
+ "pixel_clko_user",
+ "oscclk",
+ "i_spdif_clk";
+ phy = <&hdmiphy>;
+ ddc = <&hsi2c_11>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,sysreg-phandle = <&syscon_disp>;
+ #sound-dai-cells = <0>;
+
+ hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&ldo6_reg>;
+ vdd_osc-supply = <&ldo7_reg>;
+ vdd_pll-supply = <&ldo6_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi_to_tv: endpoint {
+ remote-endpoint = <&tv_to_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_to_mhl: endpoint {
+ remote-endpoint = <&mhl_to_hdmi>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml b/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml
new file mode 100644
index 0000000000..ba40284ac6
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC Mixer
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description:
+ Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data
+ inputs before passing it to an output device. The output is passed to HDMI.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - samsung,exynos4210-mixer
+ - samsung,exynos4212-mixer
+ - samsung,exynos5250-mixer
+ - samsung,exynos5420-mixer
+ - const: samsung,exynos5-mixer
+ deprecated: true
+
+ clocks:
+ minItems: 3
+ items:
+ - description: Gate of Mixer IP bus clock.
+ - description: Gate of HDMI IP bus clock, needed together with sclk_hdmi.
+ - description: HDMI Special clock, one of the two possible inputs of
+ mixer mux.
+ - description: Video Processor clock.
+ - description: Mixer mux clock.
+ - description: Mixer Special clock.
+
+ clock-names:
+ minItems: 3
+ items:
+ - const: mixer
+ - const: hdmi
+ - const: sclk_hdmi
+ - const: vp
+ - const: mout_mixer
+ - const: sclk_mixer
+
+ interconnects:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ minItems: 1
+ items:
+ - description: Mixer memory region.
+ - description: Video Processor memory region.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos4210-mixer
+ - samsung,exynos4212-mixer
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ maxItems: 6
+ regs:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos4212-mixer
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ regs:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5-mixer
+ - samsung,exynos5250-mixer
+ - samsung,exynos5420-mixer
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ regs:
+ minItems: 1
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5250.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mixer@14450000 {
+ compatible = "samsung,exynos5250-mixer";
+ reg = <0x14450000 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MIXER>,
+ <&clock CLK_HDMI>,
+ <&clock CLK_SCLK_HDMI>;
+ clock-names = "mixer",
+ "hdmi",
+ "sclk_hdmi";
+ iommus = <&sysmmu_tv>;
+ power-domains = <&pd_disp1>;
+ };
diff --git a/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml b/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml
new file mode 100644
index 0000000000..6f796835ea
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ DECON (Display and Enhancement Controller) is the Display Controller for the
+ Exynos5433 series of SoCs which transfers the image data from a video memory
+ buffer to an external LCD interface.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos5433-decon
+ - samsung,exynos5433-decon-tv
+
+ clocks:
+ minItems: 11
+ maxItems: 11
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: aclk_decon
+ - const: aclk_smmu_decon0x
+ - const: aclk_xiu_decon0x
+ - const: pclk_smmu_decon0x
+ - const: aclk_smmu_decon1x
+ - const: aclk_xiu_decon1x
+ - const: pclk_smmu_decon1x
+ - const: sclk_decon_vclk
+ - const: sclk_decon_eclk
+ - const: dsd
+
+ interrupts:
+ minItems: 3
+ maxItems: 4
+ description: |
+ Interrupts depend on mode of work:
+ - video mode: vsync
+ - command mode: lcd_sys
+ - command mode with software trigger: lcd_sys, te
+
+ interrupt-names:
+ minItems: 3
+ items:
+ - const: fifo
+ - const: vsync
+ - const: lcd_sys
+ - const: te
+
+ iommus:
+ minItems: 2
+ maxItems: 2
+
+ iommu-names:
+ items:
+ - const: m0
+ - const: m1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description:
+ Contains a port which is connected to mic node.
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ samsung,disp-sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to DISP system controller interface.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - ports
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display-controller@13800000 {
+ compatible = "samsung,exynos5433-decon";
+ reg = <0x13800000 0x2104>;
+ clocks = <&cmu_disp CLK_PCLK_DECON>,
+ <&cmu_disp CLK_ACLK_DECON>,
+ <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
+ <&cmu_disp CLK_ACLK_XIU_DECON0X>,
+ <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
+ <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
+ <&cmu_disp CLK_ACLK_XIU_DECON1X>,
+ <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
+ <&cmu_disp CLK_SCLK_DECON_VCLK>,
+ <&cmu_disp CLK_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_SCLK_DSD>;
+ clock-names = "pclk",
+ "aclk_decon",
+ "aclk_smmu_decon0x",
+ "aclk_xiu_decon0x",
+ "pclk_smmu_decon0x",
+ "aclk_smmu_decon1x",
+ "aclk_xiu_decon1x",
+ "pclk_smmu_decon1x",
+ "sclk_decon_vclk",
+ "sclk_decon_eclk",
+ "dsd";
+ power-domains = <&pd_disp>;
+ interrupt-names = "fifo", "vsync", "lcd_sys";
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,disp-sysreg = <&syscon_disp>;
+ iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
+ iommu-names = "m0", "m1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ decon_to_mic: endpoint {
+ remote-endpoint = <&mic_to_decon>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml b/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml
new file mode 100644
index 0000000000..01fccb138e
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is
+ not capable of transferring high resoltuion frame data as DECON can send. MIC
+ solves this problem by compressing the frame data by 1/2 before it is
+ transferred through MIPI DSI. The compressed frame data must be uncompressed
+ in the panel PCB.
+
+properties:
+ compatible:
+ const: samsung,exynos5433-mic
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pclk_mic0
+ - const: sclk_rgb_vclk_to_mic0
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description:
+ Contains a port which is connected to mic node.
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ samsung,disp-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to DISP system controller interface.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - ports
+ - reg
+ - samsung,disp-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ image-processor@13930000 {
+ compatible = "samsung,exynos5433-mic";
+ reg = <0x13930000 0x48>;
+ clocks = <&cmu_disp CLK_PCLK_MIC0>,
+ <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
+ clock-names = "pclk_mic0",
+ "sclk_rgb_vclk_to_mic0";
+ power-domains = <&pd_disp>;
+ samsung,disp-syscon = <&syscon_disp>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mic_to_decon: endpoint {
+ remote-endpoint = <&decon_to_mic>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mic_to_dsi: endpoint {
+ remote-endpoint = <&dsi_to_mic>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml b/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml
new file mode 100644
index 0000000000..afa137d479
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ DECON (Display and Enhancement Controller) is the Display Controller for the
+ Exynos7 series of SoCs which transfers the image data from a video memory
+ buffer to an external LCD interface.
+
+properties:
+ compatible:
+ const: samsung,exynos7-decon
+
+ clocks:
+ minItems: 4
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: pclk_decon0
+ - const: aclk_decon0
+ - const: decon0_eclk
+ - const: decon0_vclk
+
+ display-timings:
+ $ref: ../panel/display-timings.yaml#
+
+ i80-if-timings:
+ type: object
+ description: timing configuration for lcd i80 interface support
+ properties:
+ cs-setup:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of address signal is enabled until
+ chip select is enabled.
+ default: 0
+
+ wr-active:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of CS is enabled.
+ default: 1
+
+ wr-hold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of CS is disabled until write
+ signal is disabled.
+ default: 0
+
+ wr-setup:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of CS signal is enabled until
+ write signal is enabled.
+ default: 0
+
+ interrupts:
+ items:
+ - description: FIFO level
+ - description: VSYNC
+ - description: LCD system
+
+ interrupt-names:
+ items:
+ - const: fifo
+ - const: vsync
+ - const: lcd_sys
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display-controller@13930000 {
+ compatible = "samsung,exynos7-decon";
+ reg = <0x13930000 0x1000>;
+ interrupt-names = "fifo", "vsync", "lcd_sys";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
+ <&clock_disp 101>, /* ACLK_DECON_INT */
+ <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
+ <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
+ clock-names = "pclk_decon0",
+ "aclk_decon0",
+ "decon0_eclk",
+ "decon0_vclk";
+ pinctrl-0 = <&lcd_clk &pwm1_out>;
+ pinctrl-names = "default";
+ };
diff --git a/dts/Bindings/display/samsung/samsung,fimd.yaml b/dts/Bindings/display/samsung/samsung,fimd.yaml
new file mode 100644
index 0000000000..9cf5f120d5
--- /dev/null
+++ b/dts/Bindings/display/samsung/samsung,fimd.yaml
@@ -0,0 +1,198 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Joonyoung Shim <jy0922.shim@samsung.com>
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
+ - Kyungmin Park <kyungmin.park@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,s3c2443-fimd
+ - samsung,s3c6400-fimd
+ - samsung,s5pv210-fimd
+ - samsung,exynos3250-fimd
+ - samsung,exynos4210-fimd
+ - samsung,exynos5250-fimd
+ - samsung,exynos5420-fimd
+
+ '#address-cells':
+ const: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: sclk_fimd
+ - const: fimd
+
+ display-timings:
+ $ref: ../panel/display-timings.yaml#
+
+ i80-if-timings:
+ type: object
+ description: |
+ Timing configuration for lcd i80 interface support.
+ The parameters are defined as::
+ VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
+ : : : : :
+ Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
+ | cs-setup+1 | : : :
+ |<---------->| : : :
+ Chip Select ???????????????|____________:____________:____________|??
+ | wr-setup+1 | | wr-hold+1 |
+ |<---------->| |<---------->|
+ Write Enable ????????????????????????????|____________|???????????????
+ | wr-active+1|
+ |<---------->|
+ Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
+
+ properties:
+ cs-setup:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of address signal is enabled until
+ chip select is enabled.
+ default: 0
+
+ wr-active:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of CS is enabled.
+ default: 1
+
+ wr-hold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of CS is disabled until write
+ signal is disabled.
+ default: 0
+
+ wr-setup:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock cycles for the active period of CS signal is enabled until
+ write signal is enabled.
+ default: 0
+
+ iommus:
+ minItems: 1
+ maxItems: 2
+
+ iommu-names:
+ items:
+ - const: m0
+ - const: m1
+
+ interrupts:
+ items:
+ - description: FIFO level
+ - description: VSYNC
+ - description: LCD system
+
+ interrupt-names:
+ items:
+ - const: fifo
+ - const: vsync
+ - const: lcd_sys
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ samsung,invert-vden:
+ type: boolean
+ description:
+ Video enable signal is inverted.
+
+ samsung,invert-vclk:
+ type: boolean
+ description:
+ Video clock signal is inverted.
+
+ samsung,sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to System Register syscon.
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^port@[0-4]+$":
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ Contains ports with port with index::
+ 0 - for CAMIF0 input,
+ 1 - for CAMIF1 input,
+ 2 - for CAMIF2 input,
+ 3 - for parallel output,
+ 4 - for write-back interface
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5420-fimd
+ then:
+ properties:
+ iommus:
+ minItems: 2
+ maxItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos4.h>
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos4210-fimd";
+ interrupt-parent = <&combiner>;
+ reg = <0x11c00000 0x20000>;
+ interrupt-names = "fifo", "vsync", "lcd_sys";
+ interrupts = <11 0>, <11 1>, <11 2>;
+ clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
+ clock-names = "sclk_fimd", "fimd";
+ power-domains = <&pd_lcd0>;
+ iommus = <&sysmmu_fimd0>;
+ samsung,sysreg = <&sys_reg>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ samsung,invert-vden;
+ samsung,invert-vclk;
+
+ pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
+ pinctrl-names = "default";
+
+ port@3 {
+ reg = <3>;
+
+ fimd_dpi_ep: endpoint {
+ remote-endpoint = <&lcd_ep>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/simple-framebuffer.yaml b/dts/Bindings/display/simple-framebuffer.yaml
index 44a29d813f..27ba4323d2 100644
--- a/dts/Bindings/display/simple-framebuffer.yaml
+++ b/dts/Bindings/display/simple-framebuffer.yaml
@@ -52,11 +52,13 @@ description: |+
properties:
compatible:
- items:
- - enum:
- - apple,simple-framebuffer
- - allwinner,simple-framebuffer
- - amlogic,simple-framebuffer
+ oneOf:
+ - items:
+ - enum:
+ - apple,simple-framebuffer
+ - allwinner,simple-framebuffer
+ - amlogic,simple-framebuffer
+ - const: simple-framebuffer
- const: simple-framebuffer
reg:
diff --git a/dts/Bindings/display/solomon,ssd1307fb.yaml b/dts/Bindings/display/solomon,ssd1307fb.yaml
index 2ed2a7d0ca..9baafd0c42 100644
--- a/dts/Bindings/display/solomon,ssd1307fb.yaml
+++ b/dts/Bindings/display/solomon,ssd1307fb.yaml
@@ -8,6 +8,7 @@ title: Solomon SSD1307 OLED Controller Framebuffer
maintainers:
- Maxime Ripard <mripard@kernel.org>
+ - Javier Martinez Canillas <javierm@redhat.com>
properties:
compatible:
diff --git a/dts/Bindings/display/sprd/sprd,display-subsystem.yaml b/dts/Bindings/display/sprd/sprd,display-subsystem.yaml
index 3d107e9434..d0a5592bd8 100644
--- a/dts/Bindings/display/sprd/sprd,display-subsystem.yaml
+++ b/dts/Bindings/display/sprd/sprd,display-subsystem.yaml
@@ -45,6 +45,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Should contain a list of phandles pointing to display interface port
of DPU devices.
diff --git a/dts/Bindings/display/ste,mcde.yaml b/dts/Bindings/display/ste,mcde.yaml
index de0c678b3c..564ea845c8 100644
--- a/dts/Bindings/display/ste,mcde.yaml
+++ b/dts/Bindings/display/ste,mcde.yaml
@@ -58,8 +58,8 @@ patternProperties:
"^dsi@[0-9a-f]+$":
description: subnodes for the three DSI host adapters
type: object
- allOf:
- - $ref: dsi-controller.yaml#
+ $ref: dsi-controller.yaml#
+
properties:
compatible:
const: ste,mcde-dsi
diff --git a/dts/Bindings/display/ti/ti,am65x-dss.yaml b/dts/Bindings/display/ti/ti,am65x-dss.yaml
index 781c1868b0..5c7d2cbc4a 100644
--- a/dts/Bindings/display/ti/ti,am65x-dss.yaml
+++ b/dts/Bindings/display/ti/ti,am65x-dss.yaml
@@ -88,8 +88,7 @@ properties:
The DSS DPI output port node from video port 2
ti,am65x-oldi-io-ctrl:
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ $ref: "/schemas/types.yaml#/definitions/phandle"
description:
phandle to syscon device node mapping OLDI IO_CTRL registers.
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
diff --git a/dts/Bindings/dma/dma-router.yaml b/dts/Bindings/dma/dma-router.yaml
index e72748496f..4b817f5dc3 100644
--- a/dts/Bindings/dma/dma-router.yaml
+++ b/dts/Bindings/dma/dma-router.yaml
@@ -24,6 +24,8 @@ properties:
dma-masters:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Array of phandles to the DMA controllers the router can direct
the signal to.
diff --git a/dts/Bindings/dma/mediatek,uart-dma.yaml b/dts/Bindings/dma/mediatek,uart-dma.yaml
new file mode 100644
index 0000000000..54d68fc688
--- /dev/null
+++ b/dts/Bindings/dma/mediatek,uart-dma.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek UART APDMA controller
+
+maintainers:
+ - Long Cheng <long.cheng@mediatek.com>
+
+description: |
+ The MediaTek UART APDMA controller provides DMA capabilities
+ for the UART peripheral bus.
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2712-uart-dma
+ - mediatek,mt8516-uart-dma
+ - const: mediatek,mt6577-uart-dma
+ - enum:
+ - mediatek,mt6577-uart-dma
+
+ reg:
+ minItems: 1
+ maxItems: 16
+
+ interrupts:
+ description: |
+ TX, RX interrupt lines for each UART APDMA channel
+ minItems: 1
+ maxItems: 16
+
+ clocks:
+ description: Must contain one entry for the APDMA main clock
+ maxItems: 1
+
+ clock-names:
+ const: apdma
+
+ "#dma-cells":
+ const: 1
+ description: |
+ The first cell specifies the UART APDMA channel number
+
+ dma-requests:
+ description: |
+ Number of virtual channels of the UART APDMA controller
+ maximum: 16
+
+ mediatek,dma-33bits:
+ type: boolean
+ description: Enable 33-bits UART APDMA support
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+if:
+ not:
+ required:
+ - dma-requests
+then:
+ properties:
+ interrupts:
+ maxItems: 8
+ reg:
+ maxItems: 8
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt2712-clk.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ apdma: dma-controller@11000400 {
+ compatible = "mediatek,mt2712-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000400 0 0x80>,
+ <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000680 0 0x80>,
+ <0 0x11000700 0 0x80>,
+ <0 0x11000780 0 0x80>,
+ <0 0x11000800 0 0x80>,
+ <0 0x11000880 0 0x80>,
+ <0 0x11000900 0 0x80>,
+ <0 0x11000980 0 0x80>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <12>;
+ clocks = <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "apdma";
+ mediatek,dma-33bits;
+ #dma-cells = <1>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/dma/mtk-uart-apdma.txt b/dts/Bindings/dma/mtk-uart-apdma.txt
deleted file mode 100644
index fef9c1eeb2..0000000000
--- a/dts/Bindings/dma/mtk-uart-apdma.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-* Mediatek UART APDMA Controller
-
-Required properties:
-- compatible should contain:
- * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
- * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
- * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC
-
-- reg: The base address of the APDMA register bank.
-
-- interrupts: A single interrupt specifier.
- One interrupt per dma-requests, or 8 if no dma-requests property is present
-
-- dma-requests: The number of DMA channels
-
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: The APDMA clock for register accesses
-
-- mediatek,dma-33bits: Present if the DMA requires support
-
-Examples:
-
- apdma: dma-controller@11000400 {
- compatible = "mediatek,mt2712-uart-dma",
- "mediatek,mt6577-uart-dma";
- reg = <0 0x11000400 0 0x80>,
- <0 0x11000480 0 0x80>,
- <0 0x11000500 0 0x80>,
- <0 0x11000580 0 0x80>,
- <0 0x11000600 0 0x80>,
- <0 0x11000680 0 0x80>,
- <0 0x11000700 0 0x80>,
- <0 0x11000780 0 0x80>,
- <0 0x11000800 0 0x80>,
- <0 0x11000880 0 0x80>,
- <0 0x11000900 0 0x80>,
- <0 0x11000980 0 0x80>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
- dma-requests = <12>;
- clocks = <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "apdma";
- mediatek,dma-33bits;
- #dma-cells = <1>;
- };
diff --git a/dts/Bindings/dma/nvidia,tegra210-adma.yaml b/dts/Bindings/dma/nvidia,tegra210-adma.yaml
index 5c2e2f156e..fef804565b 100644
--- a/dts/Bindings/dma/nvidia,tegra210-adma.yaml
+++ b/dts/Bindings/dma/nvidia,tegra210-adma.yaml
@@ -23,7 +23,9 @@ properties:
- nvidia,tegra210-adma
- nvidia,tegra186-adma
- items:
- - const: nvidia,tegra194-adma
+ - enum:
+ - nvidia,tegra234-adma
+ - nvidia,tegra194-adma
- const: nvidia,tegra186-adma
reg:
diff --git a/dts/Bindings/dma/renesas,rz-dmac.yaml b/dts/Bindings/dma/renesas,rz-dmac.yaml
index 7a4f415d74..1e25c5b0fb 100644
--- a/dts/Bindings/dma/renesas,rz-dmac.yaml
+++ b/dts/Bindings/dma/renesas,rz-dmac.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/G2L DMA Controller
+title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
@@ -16,7 +16,9 @@ properties:
compatible:
items:
- enum:
+ - renesas,r9a07g043-dmac # RZ/G2UL
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
+ - renesas,r9a07g054-dmac # RZ/V2L
- const: renesas,rz-dmac
reg:
diff --git a/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml b/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml
index 75ad898c59..47c46af255 100644
--- a/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml
+++ b/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml
@@ -22,6 +22,9 @@ description: |
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
+allOf:
+ - $ref: "dma-controller.yaml#"
+
properties:
compatible:
items:
@@ -41,13 +44,12 @@ required:
- compatible
- reg
- interrupts
- - '#dma-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- dma@3000000 {
+ dma-controller@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x3000000 0x8000>;
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
diff --git a/dts/Bindings/dma/st,stm32-dmamux.yaml b/dts/Bindings/dma/st,stm32-dmamux.yaml
index f751796531..7b1833d6ca 100644
--- a/dts/Bindings/dma/st,stm32-dmamux.yaml
+++ b/dts/Bindings/dma/st,stm32-dmamux.yaml
@@ -46,7 +46,7 @@ examples:
#dma-cells = <3>;
dma-requests = <128>;
dma-channels = <16>;
- dma-masters = <&dma1 &dma2>;
+ dma-masters = <&dma1>, <&dma2>;
clocks = <&timer_clk>;
};
diff --git a/dts/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/dts/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
new file mode 100644
index 0000000000..c0a1408b12
--- /dev/null
+++ b/dts/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP DMA Engine
+
+description: |
+ The Xilinx ZynqMP DMA engine supports memory to memory transfers,
+ memory to device and device to memory transfers. It also has flow
+ control and rate control support for slave/peripheral dma access.
+
+maintainers:
+ - Michael Tretter <m.tretter@pengutronix.de>
+
+allOf:
+ - $ref: "../dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 1
+
+ compatible:
+ const: xlnx,zynqmp-dma-1.0
+
+ reg:
+ description: memory map for gdma/adma module access
+ maxItems: 1
+
+ interrupts:
+ description: DMA channel interrupt
+ maxItems: 1
+
+ clocks:
+ description: input clocks
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: clk_main
+ - const: clk_apb
+
+ xlnx,bus-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 64
+ - 128
+ description: AXI bus width in bits
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ dma-coherent:
+ description: present if dma operations are coherent
+
+required:
+ - "#dma-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+
+ fpd_dma_chan1: dma-controller@fd500000 {
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0xfd500000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 117 0x4>;
+ #dma-cells = <1>;
+ clock-names = "clk_main", "clk_apb";
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+ xlnx,bus-width = <128>;
+ dma-coherent;
+ };
diff --git a/dts/Bindings/dma/xilinx/zynqmp_dma.txt b/dts/Bindings/dma/xilinx/zynqmp_dma.txt
deleted file mode 100644
index 07a5a7aa9e..0000000000
--- a/dts/Bindings/dma/xilinx/zynqmp_dma.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
-memory to device and device to memory transfers. It also has flow
-control and rate control support for slave/peripheral dma access.
-
-Required properties:
-- compatible : Should be "xlnx,zynqmp-dma-1.0"
-- reg : Memory map for gdma/adma module access.
-- interrupts : Should contain DMA channel interrupt.
-- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
-- clock-names : List of input clocks "clk_main", "clk_apb"
- (see clock bindings for details)
-
-Optional properties:
-- dma-coherent : Present if dma operations are coherent.
-
-Example:
-++++++++
-fpd_dma_chan1: dma@fd500000 {
- compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xFD500000 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <0 117 4>;
- clock-names = "clk_main", "clk_apb";
- xlnx,bus-width = <128>;
- dma-coherent;
-};
diff --git a/dts/Bindings/dvfs/performance-domain.yaml b/dts/Bindings/dvfs/performance-domain.yaml
index c8b91207f3..1dcb85a02a 100644
--- a/dts/Bindings/dvfs/performance-domain.yaml
+++ b/dts/Bindings/dvfs/performance-domain.yaml
@@ -43,7 +43,6 @@ properties:
performance-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
description:
A phandle and performance domain specifier as defined by bindings of the
performance controller/provider specified by phandle.
@@ -52,10 +51,16 @@ additionalProperties: true
examples:
- |
- performance: performance-controller@12340000 {
- compatible = "qcom,cpufreq-hw";
- reg = <0x12340000 0x1000>;
- #performance-domain-cells = <1>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ performance: performance-controller@11bc00 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+
+ #performance-domain-cells = <1>;
+ };
};
// The node above defines a performance controller that is a performance
diff --git a/dts/Bindings/example-schema.yaml b/dts/Bindings/example-schema.yaml
index c078796ae1..80a2878184 100644
--- a/dts/Bindings/example-schema.yaml
+++ b/dts/Bindings/example-schema.yaml
@@ -162,6 +162,16 @@ properties:
don't need a type.
enum: [ 100, 200, 300 ]
+ vendor,int-array-variable-length-and-constrained-values:
+ description: Array might define what type of elements might be used (e.g.
+ their range).
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 3
+ items:
+ minimum: 0
+ maximum: 8
+
child-node:
description: Child nodes are just another property from a json-schema
perspective.
@@ -207,6 +217,10 @@ allOf:
then:
required:
- foo-supply
+ else:
+ # If otherwise the property is not allowed:
+ properties:
+ foo-supply: false
# Altering schema depending on presence of properties is usually done by
# dependencies (see above), however some adjustments might require if:
- if:
diff --git a/dts/Bindings/extcon/maxim,max77843.yaml b/dts/Bindings/extcon/maxim,max77843.yaml
new file mode 100644
index 0000000000..f9ffe3d6f9
--- /dev/null
+++ b/dts/Bindings/extcon/maxim,max77843.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/maxim,max77843.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX77843 MicroUSB and Companion Power Management IC Extcon
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ This is a part of device tree bindings for Maxim MAX77843 MicroUSB
+ Integrated Circuit (MUIC).
+
+ See also Documentation/devicetree/bindings/mfd/maxim,max77843.yaml for
+ additional information and example.
+
+properties:
+ compatible:
+ const: maxim,max77843-muic
+
+ connector:
+ $ref: /schemas/connector/usb-connector.yaml#
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Any connector to the data bus of this controller should be modelled using
+ the OF graph bindings specified
+ properties:
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - connector
+
+additionalProperties: false
diff --git a/dts/Bindings/firmware/arm,scmi.yaml b/dts/Bindings/firmware/arm,scmi.yaml
index 5c4c6782e0..948e2a38be 100644
--- a/dts/Bindings/firmware/arm,scmi.yaml
+++ b/dts/Bindings/firmware/arm,scmi.yaml
@@ -38,6 +38,9 @@ properties:
The virtio transport only supports a single device.
items:
- const: arm,scmi-virtio
+ - description: SCMI compliant firmware with OP-TEE transport
+ items:
+ - const: linaro,scmi-optee
interrupts:
description:
@@ -78,11 +81,24 @@ properties:
'#size-cells':
const: 0
+ atomic-threshold-us:
+ description:
+ An optional time value, expressed in microseconds, representing, on this
+ platform, the threshold above which any SCMI command, advertised to have
+ an higher-than-threshold execution latency, should not be considered for
+ atomic mode of operation, even if requested.
+ default: 0
+
arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
SMC id required when using smc or hvc transports
+ linaro,optee-channel-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Channel specifier required when using OP-TEE transport.
+
protocol@11:
type: object
properties:
@@ -195,6 +211,12 @@ patternProperties:
minItems: 1
maxItems: 2
+ linaro,optee-channel-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Channel specifier required when using OP-TEE transport and
+ protocol has a dedicated communication channel.
+
required:
- reg
@@ -226,6 +248,16 @@ else:
- arm,smc-id
- shmem
+ else:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: linaro,scmi-optee
+ then:
+ required:
+ - linaro,optee-channel-id
+
examples:
- |
firmware {
@@ -240,6 +272,8 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
+ atomic-threshold-us = <10000>;
+
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
@@ -330,7 +364,7 @@ examples:
firmware {
scmi {
compatible = "arm,scmi-smc";
- shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
+ shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
arm,smc-id = <0xc3000001>;
#address-cells = <1>;
@@ -340,7 +374,48 @@ examples:
reg = <0x11>;
#power-domain-cells = <1>;
};
+ };
+ };
+
+ - |
+ firmware {
+ scmi {
+ compatible = "linaro,scmi-optee";
+ linaro,optee-channel-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_dvfs1: protocol@13 {
+ reg = <0x13>;
+ linaro,optee-channel-id = <1>;
+ shmem = <&cpu_optee_lpri0>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk0: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sram@51000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x51000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x51000000 0x10000>;
+
+ cpu_optee_lpri0: optee-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
};
};
diff --git a/dts/Bindings/firmware/arm,scpi.yaml b/dts/Bindings/firmware/arm,scpi.yaml
index 23b346bd12..1f9322925e 100644
--- a/dts/Bindings/firmware/arm,scpi.yaml
+++ b/dts/Bindings/firmware/arm,scpi.yaml
@@ -43,6 +43,7 @@ properties:
by remote SCP firmware for use by SCPI message protocol should be
specified in any order.
minItems: 1
+ maxItems: 4
shmem:
description:
@@ -51,6 +52,7 @@ properties:
be any memory reserved for the purpose of this communication between the
processors.
minItems: 1
+ maxItems: 4
power-controller:
type: object
@@ -235,8 +237,8 @@ examples:
firmware {
scpi {
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
- mboxes = <&mailbox 1 &mailbox 2>;
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+ mboxes = <&mailbox 1>, <&mailbox 2>;
+ shmem = <&cpu_scp_lpri>, <&cpu_scp_hpri>;
scpi_sensors1: sensors {
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
diff --git a/dts/Bindings/firmware/qemu,fw-cfg-mmio.yaml b/dts/Bindings/firmware/qemu,fw-cfg-mmio.yaml
new file mode 100644
index 0000000000..fcf0011b8e
--- /dev/null
+++ b/dts/Bindings/firmware/qemu,fw-cfg-mmio.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/qemu,fw-cfg-mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QEMU Firmware Configuration bindings
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |
+ Various QEMU emulation / virtualization targets provide the following
+ Firmware Configuration interface on the "virt" machine type:
+
+ - A write-only, 16-bit wide selector (or control) register,
+ - a read-write, 64-bit wide data register.
+
+ QEMU exposes the control and data register to guests as memory mapped
+ registers; their location is communicated to the guest's UEFI firmware in the
+ DTB that QEMU places at the bottom of the guest's DRAM.
+
+ The authoritative guest-side hardware interface documentation to the fw_cfg
+ device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
+
+
+properties:
+ compatible:
+ const: qemu,fw-cfg-mmio
+
+ reg:
+ maxItems: 1
+ description: |
+ * Bytes 0x0 to 0x7 cover the data register.
+ * Bytes 0x8 to 0x9 cover the selector register.
+ * Further registers may be appended to the region in case of future interface
+ revisions / feature bits.
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+
+ fw-cfg@9020000 {
+ compatible = "qemu,fw-cfg-mmio";
+ reg = <0x9020000 0xa>;
+ };
+...
diff --git a/dts/Bindings/gnss/gnss-common.yaml b/dts/Bindings/gnss/gnss-common.yaml
new file mode 100644
index 0000000000..963b926e30
--- /dev/null
+++ b/dts/Bindings/gnss/gnss-common.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gnss/gnss-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common Properties for Global Navigation Satellite Systems (GNSS)
+ receiver devices
+
+maintainers:
+ - Johan Hovold <johan@kernel.org>
+
+description: |
+ This document defines device tree properties common to Global Navigation
+ Satellite System receivers.
+
+properties:
+ $nodename:
+ pattern: "^gnss(@.*)?$"
+
+ lna-supply:
+ description: A separate regulator supplying power for the Low Noise
+ Amplifier (LNA). This is an amplifier connected between the GNSS
+ device and the receiver antenna.
+
+ enable-gpios:
+ description: A GPIO line that will enable the GNSS receiver when
+ asserted. If this line is active low, the GPIO phandle should
+ consequently be tagged with the GPIO_ACTIVE_LOW flag so the operating
+ system can rely on asserting the line to enable the GNSS device.
+ maxItems: 1
+
+ timepulse-gpios:
+ description: When a timepulse is provided to the GNSS device using a
+ GPIO line, this is used.
+ maxItems: 1
+
+ current-speed:
+ description: The baudrate in bits per second of the device as it comes
+ online, current active speed.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ serial {
+ gnss {
+ compatible = "u-blox,neo-8";
+ vcc-supply = <&gnss_reg>;
+ timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ current-speed = <4800>;
+ };
+ };
diff --git a/dts/Bindings/gnss/gnss.txt b/dts/Bindings/gnss/gnss.txt
deleted file mode 100644
index d6dc9c0d82..0000000000
--- a/dts/Bindings/gnss/gnss.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-GNSS Receiver DT binding
-
-This documents the binding structure and common properties for GNSS receiver
-devices.
-
-A GNSS receiver node is a node named "gnss" and typically resides on a serial
-bus (e.g. UART, I2C or SPI).
-
-Please refer to the following documents for generic properties:
-
- Documentation/devicetree/bindings/serial/serial.yaml
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Required properties:
-
-- compatible : A string reflecting the vendor and specific device the node
- represents
-
-Optional properties:
-- lna-supply : Separate supply for an LNA
-- enable-gpios : GPIO used to enable the device
-- timepulse-gpios : Time pulse GPIO
-
-Example:
-
-serial@1234 {
- compatible = "ns16550a";
-
- gnss {
- compatible = "u-blox,neo-8";
-
- vcc-supply = <&gnss_reg>;
- timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
-
- current-speed = <4800>;
- };
-};
diff --git a/dts/Bindings/gnss/sirfstar.txt b/dts/Bindings/gnss/sirfstar.txt
deleted file mode 100644
index f4252b6b66..0000000000
--- a/dts/Bindings/gnss/sirfstar.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-SiRFstar-based GNSS Receiver DT binding
-
-SiRFstar chipsets are used in GNSS-receiver modules produced by several
-vendors and can use UART, SPI or I2C interfaces.
-
-Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
-properties.
-
-Required properties:
-
-- compatible : Must be one of
-
- "fastrax,uc430"
- "linx,r4"
- "wi2wi,w2sg0004"
- "wi2wi,w2sg0008i"
- "wi2wi,w2sg0084i"
-
-- vcc-supply : Main voltage regulator (pin name: 3V3_IN, VCC, VDD)
-
-Required properties (I2C):
-- reg : I2C slave address
-
-Required properties (SPI):
-- reg : SPI chip select address
-
-Optional properties:
-
-- sirf,onoff-gpios : GPIO used to power on and off device (pin name: ON_OFF)
-- sirf,wakeup-gpios : GPIO used to determine device power state
- (pin name: RFPWRUP, WAKEUP)
-- timepulse-gpios : Time pulse GPIO (pin name: 1PPS, TM)
-
-Example:
-
-serial@1234 {
- compatible = "ns16550a";
-
- gnss {
- compatible = "wi2wi,w2sg0084i";
-
- vcc-supply = <&gnss_reg>;
- sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
- sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
- };
-};
diff --git a/dts/Bindings/gnss/sirfstar.yaml b/dts/Bindings/gnss/sirfstar.yaml
new file mode 100644
index 0000000000..991599cdaa
--- /dev/null
+++ b/dts/Bindings/gnss/sirfstar.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gnss/sirfstar.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiRFstar GNSS Receiver Device Tree Bindings
+
+maintainers:
+ - Johan Hovold <johan@kernel.org>
+
+description:
+ The SiRFstar GNSS receivers have incarnated over the years in different
+ chips, starting from the SiRFstarIII which was a chip that was introduced in
+ 2004 and used in a lot of dedicated GPS devices. In 2009 SiRF was acquired
+ by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
+ acquired by Samsung, while some products remained with CSR. In 2014 CSR
+ was acquired by Qualcomm who still sell some of the SiRF products.
+
+ SiRF chips can be used over UART, I2C or SPI buses.
+
+allOf:
+ - $ref: gnss-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - csr,gsd4t
+ - csr,csrg05ta03-icje-r
+ - fastrax,uc430
+ - linx,r4
+ - wi2wi,w2sg0004
+ - wi2wi,w2sg0008i
+ - wi2wi,w2sg0084i
+
+ reg:
+ description:
+ The I2C Address, SPI chip select address. Not required on UART buses.
+
+ vcc-supply:
+ description:
+ Main voltage regulator, pin names such as 3V3_IN, VCC, VDD.
+
+ reset-gpios:
+ maxItems: 1
+ description: An optional active low reset line, should be flagged with
+ GPIO_ACTIVE_LOW.
+
+ sirf,onoff-gpios:
+ maxItems: 1
+ description: GPIO used to power on and off device, pin name ON_OFF.
+
+ sirf,wakeup-gpios:
+ maxItems: 1
+ description: GPIO used to determine device power state, pin names such
+ as RFPWRUP, WAKEUP.
+
+required:
+ - compatible
+ - vcc-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ serial {
+ gnss {
+ compatible = "wi2wi,w2sg0084i";
+ vcc-supply = <&gnss_vcc_reg>;
+ reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+ sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ current-speed = <38400>;
+ };
+ };
diff --git a/dts/Bindings/gnss/u-blox,neo-6m.yaml b/dts/Bindings/gnss/u-blox,neo-6m.yaml
index 396101a223..35a760cfd3 100644
--- a/dts/Bindings/gnss/u-blox,neo-6m.yaml
+++ b/dts/Bindings/gnss/u-blox,neo-6m.yaml
@@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: U-blox GNSS Receiver Device Tree Bindings
+allOf:
+ - $ref: gnss-common.yaml#
+
maintainers:
- Johan Hovold <johan@kernel.org>
@@ -29,27 +32,20 @@ properties:
description: >
Main voltage regulator
- timepulse-gpios:
- maxItems: 1
- description: >
- Time pulse GPIO
-
u-blox,extint-gpios:
maxItems: 1
description: >
GPIO connected to the "external interrupt" input pin
-
+
v-bckp-supply:
description: >
Backup voltage regulator
- current-speed: true
-
required:
- compatible
- vcc-supply
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/Bindings/gpio/airoha,en7523-gpio.yaml b/dts/Bindings/gpio/airoha,en7523-gpio.yaml
new file mode 100644
index 0000000000..7c41d8e814
--- /dev/null
+++ b/dts/Bindings/gpio/airoha,en7523-gpio.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/airoha,en7523-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7523 GPIO controller
+
+maintainers:
+ - John Crispin <john@phrozen.org>
+
+description: |
+ Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
+ GPIOs.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - const: airoha,en7523-gpio
+
+ reg:
+ description: |
+ The first tuple points to the input register.
+ The second and third tuple point to the direction registers
+ The fourth tuple points to the output register
+ maxItems: 4
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio0: gpio@1fbf0200 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0204 0x4>,
+ <0x1fbf0200 0x4>,
+ <0x1fbf0220 0x4>,
+ <0x1fbf0214 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: gpio@1fbf0270 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0270 0x4>,
+ <0x1fbf0260 0x4>,
+ <0x1fbf0264 0x4>,
+ <0x1fbf0278 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+...
diff --git a/dts/Bindings/gpio/delta,tn48m-gpio.yaml b/dts/Bindings/gpio/delta,tn48m-gpio.yaml
new file mode 100644
index 0000000000..e3e668a120
--- /dev/null
+++ b/dts/Bindings/gpio/delta,tn48m-gpio.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/delta,tn48m-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Delta Networks TN48M CPLD GPIO controller
+
+maintainers:
+ - Robert Marko <robert.marko@sartura.hr>
+
+description: |
+ This module is part of the Delta TN48M multi-function device. For more
+ details see ../mfd/delta,tn48m-cpld.yaml.
+
+ Delta TN48M has an onboard Lattice CPLD that is used as an GPIO expander.
+ It provides 12 pins in total, they are input-only or ouput-only type.
+
+properties:
+ compatible:
+ enum:
+ - delta,tn48m-gpo
+ - delta,tn48m-gpi
+
+ reg:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
diff --git a/dts/Bindings/gpio/faraday,ftgpio010.txt b/dts/Bindings/gpio/faraday,ftgpio010.txt
deleted file mode 100644
index d042365586..0000000000
--- a/dts/Bindings/gpio/faraday,ftgpio010.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Faraday Technology FTGPIO010 GPIO Controller
-
-Required properties:
-
-- compatible : Should be one of
- "cortina,gemini-gpio", "faraday,ftgpio010"
- "moxa,moxart-gpio", "faraday,ftgpio010"
- "faraday,ftgpio010"
-- reg : Should contain registers location and length
-- interrupts : Should contain the interrupt line for the GPIO block
-- gpio-controller : marks this as a GPIO controller
-- #gpio-cells : Should be 2, see gpio/gpio.txt
-- interrupt-controller : marks this as an interrupt controller
-- #interrupt-cells : a standard two-cell interrupt flag, see
- interrupt-controller/interrupts.txt
-
-Example:
-
-gpio@4d000000 {
- compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
- reg = <0x4d000000 0x100>;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
-};
diff --git a/dts/Bindings/gpio/faraday,ftgpio010.yaml b/dts/Bindings/gpio/faraday,ftgpio010.yaml
new file mode 100644
index 0000000000..640da5b9b0
--- /dev/null
+++ b/dts/Bindings/gpio/faraday,ftgpio010.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/faraday,ftgpio010.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Faraday Technology FTGPIO010 GPIO Controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: cortina,gemini-gpio
+ - const: faraday,ftgpio010
+ - items:
+ - const: moxa,moxart-gpio
+ - const: faraday,ftgpio010
+ - const: faraday,ftgpio010
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: Should contain the interrupt line for the GPIO block
+
+ gpio-controller: true
+ "#gpio-cells":
+ const: 2
+
+ interrupt-controller: true
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ gpio@4d000000 {
+ compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
+ reg = <0x4d000000 0x100>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/Bindings/gpio/gpio-pca95xx.yaml b/dts/Bindings/gpio/gpio-pca95xx.yaml
index b6a6e742b6..dc0fc8fc48 100644
--- a/dts/Bindings/gpio/gpio-pca95xx.yaml
+++ b/dts/Bindings/gpio/gpio-pca95xx.yaml
@@ -190,14 +190,6 @@ examples:
"chg-status+red", "green", "blue", "en-esata",
"fault1", "p26", "p27";
};
-
- ts3a227@3b {
- compatible = "ti,ts3a227e";
- reg = <0x3b>;
- interrupt-parent = <&gpio99>;
- interrupts = <14 IRQ_TYPE_EDGE_RISING>;
- ti,micbias = <0>; /* 2.1V */
- };
};
- |
diff --git a/dts/Bindings/gpio/gpio-vf610.yaml b/dts/Bindings/gpio/gpio-vf610.yaml
index e1359391d3..d2c39dba56 100644
--- a/dts/Bindings/gpio/gpio-vf610.yaml
+++ b/dts/Bindings/gpio/gpio-vf610.yaml
@@ -25,7 +25,9 @@ properties:
- const: fsl,imx7ulp-gpio
- const: fsl,vf610-gpio
- items:
- - const: fsl,imx8ulp-gpio
+ - enum:
+ - fsl,imx93-gpio
+ - fsl,imx8ulp-gpio
- const: fsl,imx7ulp-gpio
reg:
diff --git a/dts/Bindings/gpio/gpio.txt b/dts/Bindings/gpio/gpio.txt
index a8895d339b..5663e71b75 100644
--- a/dts/Bindings/gpio/gpio.txt
+++ b/dts/Bindings/gpio/gpio.txt
@@ -213,7 +213,7 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
gpio-controller;
#gpio-cells = <2>;
- line_b {
+ line_b-hog {
gpio-hog;
gpios = <6 0>;
output-low;
diff --git a/dts/Bindings/gpio/microchip,mpfs-gpio.yaml b/dts/Bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 0000000000..110651eafa
--- /dev/null
+++ b/dts/Bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 1
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x20122000 0x1000>;
+ clocks = <&clkcfg 25>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ };
+...
diff --git a/dts/Bindings/gpio/sifive,gpio.yaml b/dts/Bindings/gpio/sifive,gpio.yaml
index 427c5873f9..939e31c480 100644
--- a/dts/Bindings/gpio/sifive,gpio.yaml
+++ b/dts/Bindings/gpio/sifive,gpio.yaml
@@ -79,7 +79,7 @@ examples:
interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>,
<17>, <18>, <19>, <20>, <21>, <22>;
reg = <0x10060000 0x1000>;
- clocks = <&tlclk PRCI_CLK_TLCLK>;
+ clocks = <&tlclk FU540_PRCI_CLK_TLCLK>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
diff --git a/dts/Bindings/gpu/arm,mali-bifrost.yaml b/dts/Bindings/gpu/arm,mali-bifrost.yaml
index 63a08f3f32..4d6bfae065 100644
--- a/dts/Bindings/gpu/arm,mali-bifrost.yaml
+++ b/dts/Bindings/gpu/arm,mali-bifrost.yaml
@@ -159,6 +159,21 @@ allOf:
power-domains:
maxItems: 1
sram-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3568-mali
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ items:
+ - const: gpu
+ - const: bus
+ required:
+ - clock-names
examples:
- |
diff --git a/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml b/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml
index ae1b37dbee..0a955c7b97 100644
--- a/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml
+++ b/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml
@@ -39,39 +39,8 @@ additionalProperties: false
examples:
- |
- /* OMAP4 SoCs */
- hwspinlock: spinlock@4a0f6000 {
+ spinlock@4a0f6000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x4a0f6000 0x1000>;
#hwlock-cells = <1>;
};
-
- - |
- / {
- /* K3 AM65x SoCs */
- model = "Texas Instruments K3 AM654 SoC";
- compatible = "ti,am654-evm", "ti,am654";
- #address-cells = <2>;
- #size-cells = <2>;
-
- bus@100000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
- <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>; /* Main NavSS */
-
- bus@30800000 {
- compatible = "simple-mfd";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>;
-
- spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
- };
- };
- };
diff --git a/dts/Bindings/hwmon/adi,adm1275.yaml b/dts/Bindings/hwmon/adi,adm1275.yaml
index 223393d7ca..ab87f51c5a 100644
--- a/dts/Bindings/hwmon/adi,adm1275.yaml
+++ b/dts/Bindings/hwmon/adi,adm1275.yaml
@@ -37,6 +37,72 @@ properties:
description:
Shunt resistor value in micro-Ohm.
+ adi,volt-curr-sample-average:
+ description: |
+ Number of samples to be used to report voltage and current values.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 16, 32, 64, 128]
+
+ adi,power-sample-average:
+ description: |
+ Number of samples to be used to report power values.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 16, 32, 64, 128]
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adm1075
+ - adi,adm1276
+ then:
+ properties:
+ adi,volt-curr-sample-average:
+ default: 128
+ adi,power-sample-average: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adm1275
+ then:
+ properties:
+ adi,volt-curr-sample-average:
+ default: 16
+ adi,power-sample-average: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adm1272
+ then:
+ properties:
+ adi,volt-curr-sample-average:
+ default: 128
+ adi,power-sample-average:
+ default: 128
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adm1278
+ - adi,adm1293
+ - adi,adm1294
+ then:
+ properties:
+ adi,volt-curr-sample-average:
+ default: 128
+ adi,power-sample-average:
+ default: 1
+
required:
- compatible
- reg
@@ -53,5 +119,7 @@ examples:
compatible = "adi,adm1272";
reg = <0x10>;
shunt-resistor-micro-ohms = <500>;
+ adi,volt-curr-sample-average = <128>;
+ adi,power-sample-average = <128>;
};
};
diff --git a/dts/Bindings/hwmon/national,lm90.yaml b/dts/Bindings/hwmon/national,lm90.yaml
index 6e1d54ff5d..30db929779 100644
--- a/dts/Bindings/hwmon/national,lm90.yaml
+++ b/dts/Bindings/hwmon/national,lm90.yaml
@@ -60,7 +60,6 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
@@ -71,8 +70,7 @@ examples:
compatible = "onnn,nct1008";
reg = <0x4c>;
vcc-supply = <&palmas_ldo6_reg>;
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
};
diff --git a/dts/Bindings/hwmon/ti,tmp464.yaml b/dts/Bindings/hwmon/ti,tmp464.yaml
new file mode 100644
index 0000000000..801ca9ba7d
--- /dev/null
+++ b/dts/Bindings/hwmon/ti,tmp464.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/ti,tmp464.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TMP464 and TMP468 temperature sensors
+
+maintainers:
+ - Agathe Porte <agathe.porte@nokia.com>
+
+description: |
+ ±0.0625°C Remote and Local temperature sensor
+ https://www.ti.com/lit/ds/symlink/tmp464.pdf
+ https://www.ti.com/lit/ds/symlink/tmp468.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,tmp464
+ - ti,tmp468
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+patternProperties:
+ "^channel@([0-8])$":
+ type: object
+ description: |
+ Represents channels of the device and their specific configuration.
+
+ properties:
+ reg:
+ description: |
+ The channel number. 0 is local channel, 1-8 are remote channels.
+ items:
+ minimum: 0
+ maximum: 8
+
+ label:
+ description: |
+ A descriptive name for this channel, like "ambient" or "psu".
+
+ ti,n-factor:
+ description: |
+ The value (two's complement) to be programmed in the channel specific N correction register.
+ For remote channels only.
+ $ref: /schemas/types.yaml#/definitions/int32
+ items:
+ minimum: -128
+ maximum: 127
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@4b {
+ compatible = "ti,tmp464";
+ reg = <0x4b>;
+ };
+ };
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@4b {
+ compatible = "ti,tmp464";
+ reg = <0x4b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ label = "local";
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ ti,n-factor = <(-10)>;
+ label = "external";
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ ti,n-factor = <0x10>;
+ label = "somelabel";
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ status = "disabled";
+ };
+ };
+ };
diff --git a/dts/Bindings/i2c/atmel,at91sam-i2c.yaml b/dts/Bindings/i2c/atmel,at91sam-i2c.yaml
new file mode 100644
index 0000000000..ea2303c0e1
--- /dev/null
+++ b/dts/Bindings/i2c/atmel,at91sam-i2c.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/atmel,at91sam-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I2C for Atmel/Microchip platforms
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - atmel,at91rm9200-i2c
+ - atmel,at91sam9261-i2c
+ - atmel,at91sam9260-i2c
+ - atmel,at91sam9g20-i2c
+ - atmel,at91sam9g10-i2c
+ - atmel,at91sam9x5-i2c
+ - atmel,sama5d4-i2c
+ - atmel,sama5d2-i2c
+ - microchip,sam9x60-i2c
+ - items:
+ - const: microchip,sama7g5-i2c
+ - const: microchip,sam9x60-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ default: 100000
+
+ dmas:
+ items:
+ - description: TX DMA Channel Specifier
+ - description: RX DMA Channel Specifier
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ atmel,fifo-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Maximum number of data the RX and TX FIFOs can store for
+ FIFO capable I2C controllers.
+
+ scl-gpios: true
+
+ sda-gpios: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+
+allOf:
+ - $ref: "i2c-controller.yaml"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - atmel,sama5d4-i2c
+ - atmel,sama5d2-i2c
+ - microchip,sam9x60-i2c
+ - microchip,sama7g5-i2c
+ then:
+ properties:
+ i2c-sda-hold-time-ns:
+ description:
+ TWD hold time
+ maxItems: 1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/dma/at91.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c0: i2c@fff84000 {
+ compatible = "atmel,at91sam9g20-i2c";
+ reg = <0xfff84000 0x100>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+ };
+
+ i2c1: i2c@f8034600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0xf8034600 0x100>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+ AT91_XDMAC_DT_PERID(11)>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+ AT91_XDMAC_DT_PERID(12)>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx0>;
+ atmel,fifo-size = <16>;
+ i2c-sda-hold-time-ns = <336>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ eeprom@54 {
+ compatible = "atmel,24c02";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+ };
diff --git a/dts/Bindings/i2c/i2c-at91.txt b/dts/Bindings/i2c/i2c-at91.txt
deleted file mode 100644
index 2015f50aed..0000000000
--- a/dts/Bindings/i2c/i2c-at91.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-I2C for Atmel platforms
-
-Required properties :
-- compatible : Must be one of:
- "atmel,at91rm9200-i2c",
- "atmel,at91sam9261-i2c",
- "atmel,at91sam9260-i2c",
- "atmel,at91sam9g20-i2c",
- "atmel,at91sam9g10-i2c",
- "atmel,at91sam9x5-i2c",
- "atmel,sama5d4-i2c",
- "atmel,sama5d2-i2c",
- "microchip,sam9x60-i2c".
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: interrupt number to the cpu.
-- #address-cells = <1>;
-- #size-cells = <0>;
-- clocks: phandles to input clocks.
-
-Optional properties:
-- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
-- dmas: A list of two dma specifiers, one for each entry in dma-names.
-- dma-names: should contain "tx" and "rx".
-- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
- capable I2C controllers.
-- i2c-sda-hold-time-ns: TWD hold time, only available for:
- "atmel,sama5d4-i2c",
- "atmel,sama5d2-i2c",
- "microchip,sam9x60-i2c".
-- scl-gpios: specify the gpio related to SCL pin
-- sda-gpios: specify the gpio related to SDA pin
-- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
- bus recovery, call it "gpio" state
-- Child nodes conforming to i2c bus binding
-
-
-Examples :
-
-i2c0: i2c@fff84000 {
- compatible = "atmel,at91sam9g20-i2c";
- reg = <0xfff84000 0x100>;
- interrupts = <12 4 6>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&twi0_clk>;
- clock-frequency = <400000>;
-
- 24c512@50 {
- compatible = "atmel,24c512";
- reg = <0x50>;
- pagesize = <128>;
- }
-}
-
-i2c0: i2c@f8034600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0xf8034600 0x100>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- dmas = <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
- AT91_XDMAC_DT_PERID(11)>,
- <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
- AT91_XDMAC_DT_PERID(12)>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&flx0>;
- atmel,fifo-size = <16>;
- i2c-sda-hold-time-ns = <336>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c0>;
- pinctrl-1 = <&pinctrl_i2c0_gpio>;
- sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
- scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- wm8731: wm8731@1a {
- compatible = "wm8731";
- reg = <0x1a>;
- };
-};
diff --git a/dts/Bindings/i2c/i2c-imx.yaml b/dts/Bindings/i2c/i2c-imx.yaml
index c167958ae2..01720e338b 100644
--- a/dts/Bindings/i2c/i2c-imx.yaml
+++ b/dts/Bindings/i2c/i2c-imx.yaml
@@ -88,9 +88,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
- #include <dt-bindings/clock/vf610-clock.h>
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
i2c@83fc4000 {
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
@@ -99,6 +97,9 @@ examples:
clocks = <&clks IMX5_CLK_I2C2_GATE>;
};
+ - |
+ #include <dt-bindings/clock/vf610-clock.h>
+
i2c@40066000 {
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
diff --git a/dts/Bindings/i2c/i2c-mpc.yaml b/dts/Bindings/i2c/i2c-mpc.yaml
index 98c6fcf7bf..018e1b9444 100644
--- a/dts/Bindings/i2c/i2c-mpc.yaml
+++ b/dts/Bindings/i2c/i2c-mpc.yaml
@@ -73,6 +73,7 @@ examples:
clock-frequency = <100000>;
};
+ - |
/* MPC5200B based board */
i2c@3d00 {
#address-cells = <1>;
@@ -84,6 +85,7 @@ examples:
fsl,preserve-clocking;
};
+ - |
/* MPC8544 base board */
i2c@3100 {
#address-cells = <1>;
diff --git a/dts/Bindings/i2c/i2c-mt65xx.txt b/dts/Bindings/i2c/i2c-mt65xx.txt
index 5ea216ae70..026985b8f6 100644
--- a/dts/Bindings/i2c/i2c-mt65xx.txt
+++ b/dts/Bindings/i2c/i2c-mt65xx.txt
@@ -12,8 +12,10 @@ Required properties:
"mediatek,mt7622-i2c": for MediaTek MT7622
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
+ "mediatek,mt8168-i2c": for MediaTek MT8168
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8186-i2c": for MediaTek MT8186
"mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
diff --git a/dts/Bindings/i2c/i2c-qcom-cci.txt b/dts/Bindings/i2c/i2c-qcom-cci.txt
index 7b9fc0c22e..924ad8c034 100644
--- a/dts/Bindings/i2c/i2c-qcom-cci.txt
+++ b/dts/Bindings/i2c/i2c-qcom-cci.txt
@@ -10,6 +10,7 @@ PROPERTIES:
"qcom,msm8996-cci"
"qcom,sdm845-cci"
"qcom,sm8250-cci"
+ "qcom,sm8450-cci"
- reg
Usage: required
@@ -43,7 +44,8 @@ PROPERTIES:
SUBNODES:
The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996,
-sdm845 and sm8250), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
+sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and
+"i2c-bus@1".
PROPERTIES:
diff --git a/dts/Bindings/i2c/i2c-s3c2410.txt b/dts/Bindings/i2c/i2c-s3c2410.txt
deleted file mode 100644
index 66ae46d3bc..0000000000
--- a/dts/Bindings/i2c/i2c-s3c2410.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Samsung's I2C controller
-
-The Samsung's I2C controller is used to interface with I2C devices.
-
-Required properties:
- - compatible: value should be either of the following.
- (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
- (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
- (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
- inside HDMIPHY block found on several samsung SoCs
- (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
- a host to SATA PHY controller on an internal bus.
- - reg: physical base address of the controller and length of memory mapped
- region.
- - interrupts: interrupt number to the cpu.
- - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
-
-Required for all cases except "samsung,s3c2440-hdmiphy-i2c":
- - Samsung GPIO variant (deprecated):
- - gpios: The order of the gpios should be the following: <SDA, SCL>.
- The gpio specifier depends on the gpio controller. Required in all
- cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output
- lines are permanently wired to the respective clienta
- - Pinctrl variant (preferred, if available):
- - pinctrl-0: Pin control group to be used for this controller.
- - pinctrl-names: Should contain only one value - "default".
-
-Optional properties:
- - samsung,i2c-slave-addr: Slave address in multi-master environment. If not
- specified, default value is 0.
- - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
- specified, the default value in Hz is 100000.
- - samsung,sysreg-phandle - handle to syscon used to control the system registers
-
-Example:
-
- i2c@13870000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <345>;
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <100000>;
- /* Samsung GPIO variant begins here */
- gpios = <&gpd1 2 0 /* SDA */
- &gpd1 3 0 /* SCL */>;
- /* Samsung GPIO variant ends here */
- /* Pinctrl variant begins here */
- pinctrl-0 = <&i2c3_bus>;
- pinctrl-names = "default";
- /* Pinctrl variant ends here */
- #address-cells = <1>;
- #size-cells = <0>;
-
- wm8994@1a {
- compatible = "wlf,wm8994";
- reg = <0x1a>;
- };
- };
diff --git a/dts/Bindings/i2c/i2c.txt b/dts/Bindings/i2c/i2c.txt
index b864916e08..fc3dd7ec04 100644
--- a/dts/Bindings/i2c/i2c.txt
+++ b/dts/Bindings/i2c/i2c.txt
@@ -95,6 +95,10 @@ wants to support one of the below features, it should adapt these bindings.
- smbus-alert
states that the optional SMBus-Alert feature apply to this bus.
+- mctp-controller
+ indicates that the system is accessible via this bus as an endpoint for
+ MCTP over I2C transport.
+
Required properties (per child device)
--------------------------------------
diff --git a/dts/Bindings/i2c/ingenic,i2c.yaml b/dts/Bindings/i2c/ingenic,i2c.yaml
index febde6cc5f..af6d64a6da 100644
--- a/dts/Bindings/i2c/ingenic,i2c.yaml
+++ b/dts/Bindings/i2c/ingenic,i2c.yaml
@@ -69,8 +69,7 @@ examples:
#size-cells = <0>;
reg = <0x10054000 0x1000>;
- interrupt-parent = <&intc>;
- interrupts = <56>;
+ interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cgu JZ4780_CLK_SMB4>;
pinctrl-names = "default";
@@ -86,7 +85,6 @@ examples:
compatible = "nxp,pcf8563";
reg = <0x51>;
- interrupt-parent = <&gpf>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/dts/Bindings/i2c/microchip,corei2c.yaml b/dts/Bindings/i2c/microchip,corei2c.yaml
new file mode 100644
index 0000000000..7bad4b946a
--- /dev/null
+++ b/dts/Bindings/i2c/microchip,corei2c.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS I2C Controller Device Tree Bindings
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
+ - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+ - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: |
+ Desired I2C bus clock frequency in Hz. As only Standard and Fast
+ modes are supported, possible values are 100000 and 400000.
+ enum: [100000, 400000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+ reg = <0x2010a000 0x1000>;
+ clocks = <&clkcfg 15>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clock-frequency = <100000>;
+ };
+...
diff --git a/dts/Bindings/i2c/renesas,rcar-i2c.yaml b/dts/Bindings/i2c/renesas,rcar-i2c.yaml
index 052aad44e7..c30107833a 100644
--- a/dts/Bindings/i2c/renesas,rcar-i2c.yaml
+++ b/dts/Bindings/i2c/renesas,rcar-i2c.yaml
@@ -49,6 +49,11 @@ properties:
- renesas,i2c-r8a779a0 # R-Car V3U
- const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2
+ - items:
+ - enum:
+ - renesas,i2c-r8a779f0 # R-Car S4-8
+ - const: renesas,rcar-gen4-i2c # R-Car Gen4
+
reg:
maxItems: 1
@@ -132,6 +137,7 @@ allOf:
enum:
- renesas,rcar-gen2-i2c
- renesas,rcar-gen3-i2c
+ - renesas,rcar-gen4-i2c
then:
required:
- resets
diff --git a/dts/Bindings/i2c/renesas,riic.yaml b/dts/Bindings/i2c/renesas,riic.yaml
index 402fd125e0..f4b235a87a 100644
--- a/dts/Bindings/i2c/renesas,riic.yaml
+++ b/dts/Bindings/i2c/renesas,riic.yaml
@@ -20,6 +20,7 @@ properties:
- renesas,riic-r7s72100 # RZ/A1H
- renesas,riic-r7s9210 # RZ/A2M
- renesas,riic-r9a07g044 # RZ/G2{L,LC}
+ - renesas,riic-r9a07g054 # RZ/V2L
- const: renesas,riic-rz # RZ/A or RZ/G2L
reg:
@@ -75,6 +76,7 @@ if:
contains:
enum:
- renesas,riic-r9a07g044
+ - renesas,riic-r9a07g054
then:
required:
- resets
diff --git a/dts/Bindings/i2c/samsung,s3c2410-i2c.yaml b/dts/Bindings/i2c/samsung,s3c2410-i2c.yaml
new file mode 100644
index 0000000000..84051b0129
--- /dev/null
+++ b/dts/Bindings/i2c/samsung,s3c2410-i2c.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S3C/S5P/Exynos SoC I2C Controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,s3c2410-i2c
+ - samsung,s3c2440-i2c
+ # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
+ - samsung,s3c2440-hdmiphy-i2c
+ # For s3c2440-like I2C used as a host to SATA PHY controller on an
+ # internal bus:
+ - samsung,exynos5-sata-phy-i2c
+
+ '#address-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: i2c
+
+ gpios:
+ description: |
+ The order of the GPIOs should be the following:: <SDA, SCL>. The GPIO
+ specifier depends on the gpio controller. Required in all cases except
+ for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are
+ permanently wired to the respective client.
+ This property is deprecated. Use "pinctrl-0" and "pinctrl-names" instead.
+ deprecated: yes
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ samsung,i2c-max-bus-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Desired frequency in Hz of the bus.
+ default: 100000
+
+ samsung,i2c-sda-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay (in ns) applied to data line (SDA) edges.
+ default: 0
+
+ samsung,i2c-slave-addr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Slave address in multi-master environment.
+ default: 0
+
+ samsung,sysreg-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Pandle to syscon used to control the system registers.
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,s3c2440-hdmiphy-i2c
+ - samsung,exynos5-sata-phy-i2c
+ then:
+ properties:
+ gpios: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,s3c2410-i2c
+ - samsung,s3c2440-i2c
+ - samsung,s3c2440-hdmiphy-i2c
+ then:
+ required:
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5250.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ i2c@12c60000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C60000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_I2C0>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_bus>;
+
+ samsung,sysreg-phandle = <&sysreg_system_controller>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <20000>;
+ samsung,i2c-slave-addr = <0x66>;
+
+ eeprom@50 {
+ compatible = "samsung,s524ad0xd1";
+ reg = <0x50>;
+ };
+ };
+
+ i2c@12ce0000 {
+ compatible = "samsung,s3c2440-hdmiphy-i2c";
+ reg = <0x12CE0000 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_I2C_HDMI>;
+ clock-names = "i2c";
+
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <66000>;
+
+ phy-i2c@38 {
+ compatible = "samsung,exynos4212-hdmiphy";
+ reg = <0x38>;
+ };
+ };
+
+ i2c@121d0000 {
+ compatible = "samsung,exynos5-sata-phy-i2c";
+ reg = <0x121D0000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_SATA_PHYI2C>;
+ clock-names = "i2c";
+
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <40000>;
+
+ phy-i2c@38 {
+ compatible = "samsung,exynos-sataphy-i2c";
+ reg = <0x38>;
+ };
+ };
diff --git a/dts/Bindings/i2c/st,stm32-i2c.yaml b/dts/Bindings/i2c/st,stm32-i2c.yaml
index 46b62e1c92..dccbb18b6d 100644
--- a/dts/Bindings/i2c/st,stm32-i2c.yaml
+++ b/dts/Bindings/i2c/st,stm32-i2c.yaml
@@ -25,16 +25,9 @@ allOf:
i2c-scl-falling-time-ns:
default: 10
-
- st,syscfg-fmp:
- description: Use to set Fast Mode Plus bit within SYSCFG when
- Fast Mode Plus speed is selected by slave.
- Format is phandle to syscfg / register offset within
- syscfg / register bitmask for FMP bit.
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- items:
- minItems: 3
- maxItems: 3
+ else:
+ properties:
+ st,syscfg-fmp: false
- if:
properties:
@@ -87,6 +80,16 @@ properties:
minimum: 1
maximum: 1000000
+ st,syscfg-fmp:
+ description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
+ Plus speed is selected by slave.
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ - items:
+ - description: phandle to syscfg
+ - description: register offset within syscfg
+ - description: register bitmask for FMP bit
+
required:
- compatible
- reg
@@ -147,4 +150,3 @@ examples:
i2c-scl-falling-time-ns = <20>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
};
-...
diff --git a/dts/Bindings/iio/accel/adi,adxl367.yaml b/dts/Bindings/iio/accel/adi,adxl367.yaml
new file mode 100644
index 0000000000..d259e796c1
--- /dev/null
+++ b/dts/Bindings/iio/accel/adi,adxl367.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/adi,adxl367.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADXL367 3-Axis Digital Accelerometer
+
+maintainers:
+ - Cosmin Tanislav <cosmin.tanislav@analog.com>
+
+description: |
+ The ADXL367 is an ultralow power, 3-axis MEMS accelerometer.
+
+ The ADXL367 does not alias input signals by to achieve ultralow power
+ consumption, it samples the full bandwidth of the sensor at all
+ data rates. Measurement ranges of +-2g, +-4g, and +-8g are available,
+ with a resolution of 0.25mg/LSB on the +-2 g range.
+
+ In addition to its ultralow power consumption, the ADXL367
+ has many features to enable true system level power reduction.
+ It includes a deep multimode output FIFO, a built-in micropower
+ temperature sensor, and an internal ADC for synchronous conversion
+ of an additional analog input.
+ https://www.analog.com/en/products/adxl367.html
+
+properties:
+ compatible:
+ enum:
+ - adi,adxl367
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vdd-supply: true
+ vddio-supply: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@53 {
+ compatible = "adi,adxl367";
+ reg = <0x53>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@0 {
+ compatible = "adi,adxl367";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
diff --git a/dts/Bindings/iio/adc/adi,ad7280a.yaml b/dts/Bindings/iio/adc/adi,ad7280a.yaml
new file mode 100644
index 0000000000..a694d5794d
--- /dev/null
+++ b/dts/Bindings/iio/adc/adi,ad7280a.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7280a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7280a Lithium Ion Battery Monitoring System
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Bindings for the Analog Devices AD7280a Battery Monitoring System.
+ Used in devices such as hybrid electric cars, battery backup and power tools.
+ Multiple chips can be daisy chained and accessed via a single SPI interface.
+ Data sheet found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7280A.pdf
+
+properties:
+ compatible:
+ const: adi,ad7280a
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: IRQ line for the ADC
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ adi,voltage-alert-last-chan:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Allows limiting of scope of which channels are considered for voltage
+ alerts, typically because not all are wired to anything. Only applies to
+ last device in the daisy chain.
+ default: 5
+ enum: [3, 4, 5]
+
+ adi,acquisition-time-ns:
+ description:
+ Additional time may be needed to charge the sampling capacitors depending
+ on external writing.
+ default: 400
+ enum: [400, 800, 1200, 1600]
+
+ adi,thermistor-termination:
+ type: boolean
+ description:
+ Enable the thermistor termination function.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7280a";
+ reg = <0>;
+ spi-max-frequency = <700000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 2>;
+ adi,thermistor-termination;
+ adi,acquisition-time-ns = <800>;
+ adi,voltage-alert-last-chan = <5>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml b/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml
index efed361215..31f840d593 100644
--- a/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml
+++ b/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml
@@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
maintainers:
- - Ludovic Desroches <ludovic.desroches@atmel.com>
- Eugen Hristev <eugen.hristev@microchip.com>
properties:
@@ -72,7 +71,6 @@ required:
- atmel,min-sample-rate-hz
- atmel,max-sample-rate-hz
- atmel,startup-time-ms
- - atmel,trigger-edge-type
examples:
- |
diff --git a/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
index b939f9652e..65581ad4b8 100644
--- a/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+++ b/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -34,6 +34,7 @@ properties:
- items:
- enum:
- mediatek,mt8183-auxadc
+ - mediatek,mt8186-auxadc
- mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
- const: mediatek,mt8173-auxadc
diff --git a/dts/Bindings/iio/adc/microchip,mcp3201.yaml b/dts/Bindings/iio/adc/microchip,mcp3201.yaml
index cbbac4ce56..fcc1ba53b2 100644
--- a/dts/Bindings/iio/adc/microchip,mcp3201.yaml
+++ b/dts/Bindings/iio/adc/microchip,mcp3201.yaml
@@ -10,7 +10,7 @@ maintainers:
- Oskar Andero <oskar.andero@gmail.com>
description: |
- Family of simple ADCs with an I2C inteface.
+ Family of simple ADCs with a SPI interface.
properties:
compatible:
diff --git a/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml
index 27e3108661..2a94db6888 100644
--- a/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml
+++ b/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml
@@ -51,7 +51,7 @@ examples:
#size-cells = <0>;
pmic_iadc: adc@3600 {
compatible = "qcom,spmi-iadc";
- reg = <0x3600 0x100>;
+ reg = <0x3600>;
interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
qcom,external-resistor-micro-ohms = <10000>;
#io-channel-cells = <1>;
diff --git a/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml b/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml
index 7b895784e0..57a3135608 100644
--- a/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml
+++ b/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml
@@ -74,9 +74,9 @@ examples:
compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
adc {
compatible = "ti,palmas-gpadc";
- interrupts = <18 0
- 16 0
- 17 0>;
+ interrupts = <18 0>,
+ <16 0>,
+ <17 0>;
#io-channel-cells = <1>;
ti,channel0-current-microamp = <5>;
ti,channel3-current-microamp = <10>;
diff --git a/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml b/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml
index 87992db389..3698b4b090 100644
--- a/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml
+++ b/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml
@@ -92,6 +92,10 @@ properties:
description: AMS Controller register space
maxItems: 1
+ clocks:
+ items:
+ - description: AMS reference clock
+
ranges:
description:
Maps the child address space for PS and/or PL.
@@ -181,12 +185,15 @@ properties:
required:
- compatible
- reg
+ - clocks
- ranges
additionalProperties: false
examples:
- |
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+
bus {
#address-cells = <2>;
#size-cells = <2>;
@@ -196,6 +203,7 @@ examples:
interrupt-parent = <&gic>;
interrupts = <0 56 4>;
reg = <0x0 0xffa50000 0x0 0x800>;
+ clocks = <&zynqmp_clk AMS_REF>;
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
diff --git a/dts/Bindings/iio/afe/temperature-sense-rtd.yaml b/dts/Bindings/iio/afe/temperature-sense-rtd.yaml
new file mode 100644
index 0000000000..336ce96371
--- /dev/null
+++ b/dts/Bindings/iio/afe/temperature-sense-rtd.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/afe/temperature-sense-rtd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Temperature Sense RTD
+
+maintainers:
+ - Liam Beguin <liambeguin@gmail.com>
+
+description: |
+ RTDs (Resistance Temperature Detectors) are a kind of temperature sensors
+ used to get a linear voltage to temperature reading within a give range
+ (usually 0 to 100 degrees Celsius).
+
+ When an io-channel measures the output voltage across an RTD such as a
+ PT1000, the interesting measurement is almost always the corresponding
+ temperature, not the voltage output. This binding describes such a circuit.
+
+ The general transfer function here is (using SI units)
+
+ V = R(T) * iexc
+ R(T) = r0 * (1 + alpha * T)
+ T = 1 / (alpha * r0 * iexc) * (V - r0 * iexc)
+
+ The following circuit matches what's in the examples section.
+
+ 5V0
+ -----
+ |
+ +---+----+
+ | R 5k |
+ +---+----+
+ |
+ V 1mA
+ |
+ +---- Vout
+ |
+ +---+----+
+ | PT1000 |
+ +---+----+
+ |
+ -----
+ GND
+
+properties:
+ compatible:
+ const: temperature-sense-rtd
+
+ io-channels:
+ maxItems: 1
+ description: |
+ Channel node of a voltage io-channel.
+
+ '#io-channel-cells':
+ const: 0
+
+ excitation-current-microamp:
+ description: The current fed through the RTD sensor.
+
+ alpha-ppm-per-celsius:
+ description: |
+ alpha can also be expressed in micro-ohms per ohm Celsius. It's a linear
+ approximation of the resistance versus temperature relationship
+ between 0 and 100 degrees Celsius.
+
+ alpha = (R_100 - R_0) / (100 * R_0)
+
+ Where, R_100 is the resistance of the sensor at 100 degrees Celsius, and
+ R_0 (or r-naught-ohms) is the resistance of the sensor at 0 degrees
+ Celsius.
+
+ Pure platinum has an alpha of 3925. Industry standards such as IEC60751
+ and ASTM E-1137 specify an alpha of 3850.
+
+ r-naught-ohms:
+ description: |
+ Resistance of the sensor at 0 degrees Celsius.
+ Common values are 100 for PT100, 500 for PT500, and 1000 for PT1000
+
+additionalProperties: false
+required:
+ - compatible
+ - io-channels
+ - excitation-current-microamp
+ - alpha-ppm-per-celsius
+ - r-naught-ohms
+
+examples:
+ - |
+ pt1000_1: temperature-sensor0 {
+ compatible = "temperature-sense-rtd";
+ #io-channel-cells = <0>;
+ io-channels = <&temp_adc1 0>;
+
+ excitation-current-microamp = <1000>; /* i = U/R = 5 / 5000 */
+ alpha-ppm-per-celsius = <3908>;
+ r-naught-ohms = <1000>;
+ };
+...
diff --git a/dts/Bindings/iio/afe/temperature-transducer.yaml b/dts/Bindings/iio/afe/temperature-transducer.yaml
new file mode 100644
index 0000000000..cfbf5350db
--- /dev/null
+++ b/dts/Bindings/iio/afe/temperature-transducer.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/afe/temperature-transducer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Temperature Transducer
+
+maintainers:
+ - Liam Beguin <liambeguin@gmail.com>
+
+description: |
+ A temperature transducer is a device that converts a thermal quantity
+ into any other physical quantity. This binding applies to temperature to
+ voltage (like the LTC2997), and temperature to current (like the AD590)
+ linear transducers.
+ In both cases these are assumed to be connected to a voltage ADC.
+
+ When an io-channel measures the output voltage of a temperature analog front
+ end such as a temperature transducer, the interesting measurement is almost
+ always the corresponding temperature, not the voltage output. This binding
+ describes such a circuit.
+
+ The general transfer function here is (using SI units)
+ V(T) = Rsense * Isense(T)
+ T = (Isense(T) / alpha) + offset
+ T = 1 / (Rsense * alpha) * (V + offset * Rsense * alpha)
+
+ When using a temperature to voltage transducer, Rsense is set to 1.
+
+ The following circuits show a temperature to current and a temperature to
+ voltage transducer that can be used with this binding.
+
+ VCC
+ -----
+ |
+ +---+---+
+ | AD590 | VCC
+ +---+---+ -----
+ | |
+ V proportional to T +----+----+
+ | D+ --+ |
+ +---- Vout | LTC2997 +--- Vout
+ | D- --+ |
+ +---+----+ +---------+
+ | Rsense | |
+ +---+----+ -----
+ | GND
+ -----
+ GND
+
+properties:
+ compatible:
+ const: temperature-transducer
+
+ io-channels:
+ maxItems: 1
+ description: |
+ Channel node of a voltage io-channel.
+
+ '#io-channel-cells':
+ const: 0
+
+ sense-offset-millicelsius:
+ description: |
+ Temperature offset.
+ This offset is commonly used to convert from Kelvins to degrees Celsius.
+ In that case, sense-offset-millicelsius would be set to <(-273150)>.
+ default: 0
+
+ sense-resistor-ohms:
+ description: |
+ The sense resistor.
+ By default sense-resistor-ohms cancels out the resistor making the
+ circuit behave like a temperature transducer.
+ default: 1
+
+ alpha-ppm-per-celsius:
+ description: |
+ Sometimes referred to as output gain, slope, or temperature coefficient.
+
+ alpha is expressed in parts per million which can be micro-amps per
+ degrees Celsius or micro-volts per degrees Celsius. The is the main
+ characteristic of a temperature transducer and should be stated in the
+ datasheet.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - io-channels
+ - alpha-ppm-per-celsius
+
+examples:
+ - |
+ ad950: temperature-sensor-0 {
+ compatible = "temperature-transducer";
+ #io-channel-cells = <0>;
+ io-channels = <&temp_adc 3>;
+
+ sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
+ sense-resistor-ohms = <8060>;
+ alpha-ppm-per-celsius = <1>; /* 1 uA/K */
+ };
+ - |
+ znq_tmp: temperature-sensor-1 {
+ compatible = "temperature-transducer";
+ #io-channel-cells = <0>;
+ io-channels = <&temp_adc 2>;
+
+ sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
+ alpha-ppm-per-celsius = <4000>; /* 4 mV/K */
+ };
+...
diff --git a/dts/Bindings/iio/amplifiers/adi,ada4250.yaml b/dts/Bindings/iio/amplifiers/adi,ada4250.yaml
new file mode 100644
index 0000000000..5277479be3
--- /dev/null
+++ b/dts/Bindings/iio/amplifiers/adi,ada4250.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/amplifiers/adi,ada4250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADA4250 Programmable Gain Instrumentation Amplifier
+
+maintainers:
+ - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description: |
+ Precision Low Power, 110kHz, 26uA, Programmable Gain Instrumentation Amplifier.
+
+properties:
+ compatible:
+ enum:
+ - adi,ada4250
+
+ reg:
+ maxItems: 1
+
+ avdd-supply: true
+
+ adi,refbuf-enable:
+ description:
+ Enable internal buffer to drive the reference pin.
+ type: boolean
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ amplifier@0 {
+ compatible = "adi,ada4250";
+ reg = <0>;
+ avdd-supply = <&avdd>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/adi,ltc2688.yaml b/dts/Bindings/iio/dac/adi,ltc2688.yaml
new file mode 100644
index 0000000000..48f9e7d294
--- /dev/null
+++ b/dts/Bindings/iio/dac/adi,ltc2688.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ltc2688.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices LTC2688 DAC
+
+maintainers:
+ - Nuno Sá <nuno.sa@analog.com>
+
+description: |
+ Analog Devices LTC2688 16 channel, 16 bit, +-15V DAC
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2688.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ltc2688
+
+ reg:
+ maxItems: 1
+
+ vcc-supply:
+ description: Analog Supply Voltage Input.
+
+ iovcc-supply:
+ description: Digital Input/Output Supply Voltage.
+
+ vref-supply:
+ description:
+ Reference Input/Output. The voltage at the REF pin sets the full-scale
+ range of all channels. If not provided the internal reference is used and
+ also provided on the VREF pin".
+
+ clr-gpios:
+ description:
+ If specified, it will be asserted during driver probe. As the line is
+ active low, it should be marked GPIO_ACTIVE_LOW.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^channel@([0-9]|1[0-5])$":
+ type: object
+
+ properties:
+ reg:
+ description: The channel number representing the DAC output channel.
+ maximum: 15
+
+ adi,toggle-mode:
+ description:
+ Set the channel as a toggle enabled channel. Toggle operation enables
+ fast switching of a DAC output between two different DAC codes without
+ any SPI transaction.
+ type: boolean
+
+ adi,output-range-microvolt:
+ description: Specify the channel output full scale range.
+ oneOf:
+ - items:
+ - const: 0
+ - enum: [5000000, 10000000]
+ - items:
+ - const: -5000000
+ - const: 5000000
+ - items:
+ - const: -10000000
+ - const: 10000000
+ - items:
+ - const: -15000000
+ - const: 15000000
+
+ adi,overrange:
+ description: Enable 5% overrange over the selected full scale range.
+ type: boolean
+
+ clocks:
+ maxItems: 1
+
+ adi,toggle-dither-input:
+ description:
+ Selects the TGPx pin to be associated with this channel. This setting
+ only makes sense for toggle or dither enabled channels. If
+ @adi,toggle-mode is not set and this property is given, the channel is
+ assumed to be a dither capable channel. Note that multiple channels
+ can be mapped to the same pin. If this setting is given, the
+ respective @clock must also be provided. Mappings between this and
+ input pins
+ 0 - TGP1
+ 1 - TGP2
+ 2 - TGP3
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ dependencies:
+ adi,toggle-dither-input: [ clocks ]
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ltc2688: ltc2688@0 {
+ compatible = "adi,ltc2688";
+ reg = <0>;
+
+ vcc-supply = <&vcc>;
+ iovcc-supply = <&vcc>;
+ vref-supply = <&vref>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ adi,toggle-mode;
+ adi,overrange;
+ };
+
+ channel@1 {
+ reg = <1>;
+ adi,output-range-microvolt = <0 10000000>;
+
+ clocks = <&clock_tgp3>;
+ adi,toggle-dither-input = <2>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/iio/frequency/adi,admv1014.yaml b/dts/Bindings/iio/frequency/adi,admv1014.yaml
new file mode 100644
index 0000000000..2716c1e8fe
--- /dev/null
+++ b/dts/Bindings/iio/frequency/adi,admv1014.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADMV1014 Microwave Downconverter
+
+maintainers:
+ - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description: |
+ Wideband, microwave downconverter optimized for point to point microwave
+ radio designs operating in the 24 GHz to 44 GHz frequency range.
+
+ https://www.analog.com/en/products/admv1014.html
+
+properties:
+ compatible:
+ enum:
+ - adi,admv1014
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 1000000
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: lo_in
+ description:
+ External clock that provides the Local Oscilator input.
+
+ vcm-supply:
+ description:
+ Common-mode voltage regulator.
+
+ vcc-if-bb-supply:
+ description:
+ BB and IF supply voltage regulator.
+
+ vcc-vga-supply:
+ description:
+ RF Amplifier supply voltage regulator.
+
+ vcc-vva-supply:
+ description:
+ VVA Control Circuit supply voltage regulator.
+
+ vcc-lna-3p3-supply:
+ description:
+ Low Noise Amplifier 3.3V supply voltage regulator.
+
+ vcc-lna-1p5-supply:
+ description:
+ Low Noise Amplifier 1.5V supply voltage regulator.
+
+ vcc-bg-supply:
+ description:
+ Band Gap Circuit supply voltage regulator.
+
+ vcc-quad-supply:
+ description:
+ Quadruple supply voltage regulator.
+
+ vcc-mixer-supply:
+ description:
+ Mixer supply voltage regulator.
+
+ adi,input-mode:
+ description:
+ Select the input mode.
+ iq - in-phase quadrature (I/Q) input
+ if - complex intermediate frequency (IF) input
+ enum: [iq, if]
+
+ adi,detector-enable:
+ description:
+ Digital Rx Detector Enable. The Square Law Detector output is
+ available at output pin VDET.
+ type: boolean
+
+ adi,p1db-compensation-enable:
+ description:
+ Turn on bits to optimize P1dB.
+ type: boolean
+
+ adi,quad-se-mode:
+ description:
+ Switch the LO path from differential to single-ended operation.
+ se-neg - Single-Ended Mode, Negative Side Disabled.
+ se-pos - Single-Ended Mode, Positive Side Disabled.
+ diff - Differential Mode.
+ enum: [se-neg, se-pos, diff]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - vcm-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ converter@0 {
+ compatible = "adi,admv1014";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ clocks = <&admv1014_lo>;
+ clock-names = "lo_in";
+ vcm-supply = <&vcm>;
+ vcc-if-bb-supply = <&vcc_if_bb>;
+ vcc-vga-supply = <&vcc_vga>;
+ vcc-vva-supply = <&vcc_vva>;
+ vcc-lna-3p3-supply = <&vcc_lna_3p3>;
+ vcc-lna-1p5-supply = <&vcc_lna_1p5>;
+ vcc-bg-supply = <&vcc_bg>;
+ vcc-quad-supply = <&vcc_quad>;
+ vcc-mixer-supply = <&vcc_mixer>;
+ adi,quad-se-mode = "diff";
+ adi,detector-enable;
+ adi,p1db-compensation-enable;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/frequency/adi,admv4420.yaml b/dts/Bindings/iio/frequency/adi,admv4420.yaml
new file mode 100644
index 0000000000..da7fe85ec9
--- /dev/null
+++ b/dts/Bindings/iio/frequency/adi,admv4420.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,admv4420.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADMV4420 K Band Downconverter
+
+maintainers:
+ - Cristian Pop <cristian.pop@analog.com>
+
+description:
+ The ADMV4420 is a highly integrated, double balanced, active
+ mixer with an integrated fractional-N synthesizer, ideally suited
+ for next generation K band satellite communications
+
+properties:
+ compatible:
+ enum:
+ - adi,admv4420
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 1000000
+
+ adi,lo-freq-khz:
+ description: LO Frequency
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ adi,ref-ext-single-ended-en:
+ description: External reference selected.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mixer@0 {
+ compatible = "adi,admv4420";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ adi,lo-freq-khz = <16750000>;
+ adi,ref-ext-single-ended-en;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/proximity/semtech,sx9324.yaml b/dts/Bindings/iio/proximity/semtech,sx9324.yaml
new file mode 100644
index 0000000000..b8a6ee1685
--- /dev/null
+++ b/dts/Bindings/iio/proximity/semtech,sx9324.yaml
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/proximity/semtech,sx9324.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Semtech's SX9324 capacitive proximity sensor
+
+maintainers:
+ - Gwendal Grignou <gwendal@chromium.org>
+ - Daniel Campello <campello@chromium.org>
+
+description: |
+ Semtech's SX9324 proximity sensor.
+
+properties:
+ compatible:
+ const: semtech,sx9324
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Generated by device to announce preceding read request has finished
+ and data is available or that a close/far proximity event has happened.
+ maxItems: 1
+
+ vdd-supply:
+ description: Main power supply
+
+ svdd-supply:
+ description: Host interface power supply
+
+ "#io-channel-cells":
+ const: 1
+
+ semtech,ph0-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of 3 entries. Index represent the id of the CS pin.
+ Value indicates how each CS pin is used during phase 0.
+ Each of the 3 pins have the following value -
+ 0 : unused (high impedance)
+ 1 : measured input
+ 2 : dynamic shield
+ 3 : grounded.
+ For instance, CS0 measured, CS1 shield and CS2 ground is [1, 2, 3]
+ items:
+ enum: [ 0, 1, 2, 3 ]
+ minItems: 3
+ maxItems: 3
+
+ semtech,ph1-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Same as ph0-pin for phase 1.
+ items:
+ enum: [ 0, 1, 2, 3 ]
+ minItems: 3
+ maxItems: 3
+
+ semtech,ph2-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Same as ph0-pin for phase 2.
+ items:
+ enum: [ 0, 1, 2, 3 ]
+ minItems: 3
+ maxItems: 3
+
+ semtech,ph3-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Same as ph0-pin for phase 3.
+ items:
+ enum: [ 0, 1, 2, 3 ]
+ minItems: 3
+ maxItems: 3
+
+
+ semtech,ph01-resolution:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8, 16, 32, 64, 128, 256, 512, 1024]
+ description:
+ Capacitance measurement resolution. For phase 0 and 1.
+ Higher the number, higher the resolution.
+ default: 128
+
+ semtech,ph23-resolution:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8, 16, 32, 64, 128, 256, 512, 1024]
+ description:
+ Capacitance measurement resolution. For phase 2 and 3
+ default: 128
+
+ semtech,startup-sensor:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Phase used for start-up proximity detection.
+ It is used when we enable a phase to remove static offset and measure
+ only capacitance changes introduced by the user.
+
+ semtech,ph01-proxraw-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ default: 1
+ description:
+ PROXRAW filter strength for phase 0 and 1. A value of 0 represents off,
+ and other values represent 1-1/2^N.
+
+ semtech,ph23-proxraw-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ default: 1
+ description:
+ Same as proxraw-strength01, for phase 2 and 3.
+
+ semtech,avg-pos-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 16, 64, 128, 256, 512, 1024, 4294967295]
+ default: 16
+ description: |
+ Average positive filter strength. A value of 0 represents off and
+ UINT_MAX (4294967295) represents infinite. Other values
+ represent 1-1/N.
+
+required:
+ - compatible
+ - reg
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ proximity@28 {
+ compatible = "semtech,sx9324";
+ reg = <0x28>;
+ interrupt-parent = <&pio>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW 5>;
+ vdd-supply = <&pp3300_a>;
+ svdd-supply = <&pp1800_prox>;
+ #io-channel-cells = <1>;
+ semtech,ph0-pin = <1 2 3>;
+ semtech,ph1-pin = <3 2 1>;
+ semtech,ph2-pin = <1 2 3>;
+ semtech,ph3-pin = <3 2 1>;
+ semtech,ph01-resolution = <256>;
+ semtech,ph23-resolution = <256>;
+ semtech,startup-sensor = <1>;
+ semtech,ph01-proxraw-strength = <2>;
+ semtech,ph23-proxraw-strength = <2>;
+ semtech,avg-pos-strength = <64>;
+ };
+ };
diff --git a/dts/Bindings/iio/proximity/semtech,sx9360.yaml b/dts/Bindings/iio/proximity/semtech,sx9360.yaml
new file mode 100644
index 0000000000..63e1a1fd00
--- /dev/null
+++ b/dts/Bindings/iio/proximity/semtech,sx9360.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/proximity/semtech,sx9360.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Semtech's SX9360 capacitive proximity sensor
+
+maintainers:
+ - Gwendal Grignou <gwendal@chromium.org>
+ - Daniel Campello <campello@chromium.org>
+
+description: |
+ Semtech's SX9360 proximity sensor.
+
+properties:
+ compatible:
+ const: semtech,sx9360
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Generated by device to announce preceding read request has finished
+ and data is available or that a close/far proximity event has happened.
+ maxItems: 1
+
+ vdd-supply:
+ description: Main power supply
+
+ svdd-supply:
+ description: Host interface power supply
+
+ "#io-channel-cells":
+ const: 1
+
+ semtech,resolution:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ enum: [8, 16, 32, 64, 128, 256, 512, 1024]
+ description:
+ Capacitance measurement resolution. For both phases, "reference" and
+ "measurement". Higher the number, higher the resolution.
+ default: 128
+
+ semtech,proxraw-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ default: 1
+ description:
+ PROXRAW filter strength for both phases. A value of 0 represents off,
+ and other values represent 1-1/2^N.
+
+ semtech,avg-pos-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 16, 64, 128, 256, 512, 1024, 4294967295]
+ default: 16
+ description: |
+ Average positive filter strength. A value of 0 represents off and
+ UINT_MAX (4294967295) represents infinite. Other values
+ represent 1-1/N.
+
+required:
+ - compatible
+ - reg
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ proximity@28 {
+ compatible = "semtech,sx9360";
+ reg = <0x28>;
+ interrupt-parent = <&pio>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW 5>;
+ vdd-supply = <&pp3300_a>;
+ svdd-supply = <&pp1800_prox>;
+ #io-channel-cells = <1>;
+ semtech,resolution = <256>;
+ semtech,proxraw-strength = <2>;
+ semtech,avg-pos-strength = <64>;
+ };
+ };
diff --git a/dts/Bindings/iio/st,st-sensors.yaml b/dts/Bindings/iio/st,st-sensors.yaml
index 71de5631eb..9735a20482 100644
--- a/dts/Bindings/iio/st,st-sensors.yaml
+++ b/dts/Bindings/iio/st,st-sensors.yaml
@@ -46,6 +46,9 @@ properties:
- st,lsm330d-accel
- st,lsm330dl-accel
- st,lsm330dlc-accel
+ - description: Silan Accelerometers
+ enum:
+ - silan,sc7a20
- description: STMicroelectronics Gyroscopes
enum:
- st,l3g4200d-gyro
diff --git a/dts/Bindings/input/adc-joystick.yaml b/dts/Bindings/input/adc-joystick.yaml
index 721878d5b7..2ee04e03bc 100644
--- a/dts/Bindings/input/adc-joystick.yaml
+++ b/dts/Bindings/input/adc-joystick.yaml
@@ -61,11 +61,10 @@ patternProperties:
description: EV_ABS specific event code generated by the axis.
abs-range:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32-array
- - items:
- - description: minimum value
- - description: maximum value
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: minimum value
+ - description: maximum value
description: >
Minimum and maximum values produced by the axis.
For an ABS_X axis this will be the left-most and right-most
diff --git a/dts/Bindings/input/mediatek,mt6779-keypad.yaml b/dts/Bindings/input/mediatek,mt6779-keypad.yaml
new file mode 100644
index 0000000000..b1770640f9
--- /dev/null
+++ b/dts/Bindings/input/mediatek,mt6779-keypad.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/mediatek,mt6779-keypad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek's Keypad Controller device tree bindings
+
+maintainers: