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authorSascha Hauer <s.hauer@pengutronix.de>2016-06-13 07:31:05 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-06-13 07:31:05 +0200
commitc672e87588a9db0b2f23938964d882c38cb21f2c (patch)
treee8d54ee83c1bfed55681bd94e5827f248ab8de42 /dts/Bindings
parentad85fd3b3173b72eda09114ec6722639a4b33c25 (diff)
downloadbarebox-c672e87588a9db0b2f23938964d882c38cb21f2c.tar.gz
barebox-c672e87588a9db0b2f23938964d882c38cb21f2c.tar.xz
dts: update to v4.6-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/net/mediatek-net.txt7
-rw-r--r--dts/Bindings/phy/rockchip-dp-phy.txt18
-rw-r--r--dts/Bindings/phy/rockchip-emmc-phy.txt22
-rw-r--r--dts/Bindings/rtc/s3c-rtc.txt7
4 files changed, 34 insertions, 20 deletions
diff --git a/dts/Bindings/net/mediatek-net.txt b/dts/Bindings/net/mediatek-net.txt
index 5ca79290e..32eaaca04 100644
--- a/dts/Bindings/net/mediatek-net.txt
+++ b/dts/Bindings/net/mediatek-net.txt
@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
Required properties:
- compatible: Should be "mediatek,mt7623-eth"
- reg: Address and length of the register set for the device
-- interrupts: Should contain the frame engines interrupt
+- interrupts: Should contain the three frame engines interrupts in numeric
+ order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
"ethif", "esw", "gp2", "gp1"
@@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
<&ethsys CLK_ETHSYS_GP2>,
<&ethsys CLK_ETHSYS_GP1>;
clock-names = "ethif", "esw", "gp2", "gp1";
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
+ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
+ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
reset-names = "eth";
diff --git a/dts/Bindings/phy/rockchip-dp-phy.txt b/dts/Bindings/phy/rockchip-dp-phy.txt
index 50c4f9b00..e3b4809fb 100644
--- a/dts/Bindings/phy/rockchip-dp-phy.txt
+++ b/dts/Bindings/phy/rockchip-dp-phy.txt
@@ -8,15 +8,19 @@ Required properties:
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "24m"
-- rockchip,grf: phandle to the syscon managing the "general register files"
- #phy-cells : from the generic PHY bindings, must be 0;
Example:
-edp_phy: edp-phy {
- compatible = "rockchip,rk3288-dp-phy";
- rockchip,grf = <&grf>;
- clocks = <&cru SCLK_EDP_24M>;
- clock-names = "24m";
- #phy-cells = <0>;
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
+
+...
+
+ edp_phy: edp-phy {
+ compatible = "rockchip,rk3288-dp-phy";
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
+ };
};
diff --git a/dts/Bindings/phy/rockchip-emmc-phy.txt b/dts/Bindings/phy/rockchip-emmc-phy.txt
index 61916f15a..555cb0f40 100644
--- a/dts/Bindings/phy/rockchip-emmc-phy.txt
+++ b/dts/Bindings/phy/rockchip-emmc-phy.txt
@@ -3,17 +3,23 @@ Rockchip EMMC PHY
Required properties:
- compatible: rockchip,rk3399-emmc-phy
- - rockchip,grf : phandle to the syscon managing the "general
- register files"
- #phy-cells: must be 0
- - reg: PHY configure reg address offset in "general
+ - reg: PHY register address offset and length in "general
register files"
Example:
-emmcphy: phy {
- compatible = "rockchip,rk3399-emmc-phy";
- rockchip,grf = <&grf>;
- reg = <0xf780>;
- #phy-cells = <0>;
+
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+...
+
+ emmcphy: phy@f780 {
+ compatible = "rockchip,rk3399-emmc-phy";
+ reg = <0xf780 0x20>;
+ #phy-cells = <0>;
+ };
};
diff --git a/dts/Bindings/rtc/s3c-rtc.txt b/dts/Bindings/rtc/s3c-rtc.txt
index 1068ffce9..fdde63a54 100644
--- a/dts/Bindings/rtc/s3c-rtc.txt
+++ b/dts/Bindings/rtc/s3c-rtc.txt
@@ -15,9 +15,10 @@ Required properties:
is the rtc tick interrupt. The number of cells representing a interrupt
depends on the parent interrupt controller.
- clocks: Must contain a list of phandle and clock specifier for the rtc
- and source clocks.
-- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the
- same order as the clocks property.
+ clock and in the case of a s3c6410 compatible controller, also
+ a source clock.
+- clock-names: Must contain "rtc" and for a s3c6410 compatible controller,
+ a "rtc_src" sorted in the same order as the clocks property.
Example: