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authorSascha Hauer <s.hauer@pengutronix.de>2016-09-29 14:38:07 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-09-29 14:38:07 +0200
commitd9a15385467936649b6c2cfeb7ab377002ddce0f (patch)
tree39175107fc884a29fbba83f47d104f493833fe19 /dts/Bindings
parentbfe946c9593513b0ad1b440bcd997b263487b945 (diff)
downloadbarebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.gz
dts: update to v4.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/arm/altera/socfpga-eccmgr.txt38
-rw-r--r--dts/Bindings/arm/arm,scpi.txt34
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt6
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt36
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm23550.txt15
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--dts/Bindings/arm/coresight.txt35
-rw-r--r--dts/Bindings/arm/cpus.txt3
-rw-r--r--dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt14
-rw-r--r--dts/Bindings/arm/l2c2x0.txt4
-rw-r--r--dts/Bindings/arm/mediatek.txt4
-rw-r--r--dts/Bindings/arm/olimex.txt8
-rw-r--r--dts/Bindings/arm/pmu.txt4
-rw-r--r--dts/Bindings/arm/rockchip.txt3
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt1
-rw-r--r--dts/Bindings/arm/shmobile.txt6
-rw-r--r--dts/Bindings/arm/tegra.txt4
-rw-r--r--dts/Bindings/arm/xen.txt35
-rw-r--r--dts/Bindings/ata/ahci-platform.txt1
-rw-r--r--dts/Bindings/ata/brcm,sata-brcm.txt (renamed from dts/Bindings/ata/brcm,sata-brcmstb.txt)9
-rw-r--r--dts/Bindings/bus/nvidia,tegra210-aconnect.txt45
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-clkc.txt36
-rw-r--r--dts/Bindings/clock/clps711x-clock.txt4
-rw-r--r--dts/Bindings/clock/fixed-factor-clock.txt4
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt7
-rw-r--r--dts/Bindings/clock/renesas,cpg-mstp-clocks.txt1
-rw-r--r--dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt1
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt24
-rw-r--r--dts/Bindings/display/arm,malidp.txt65
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.txt26
-rw-r--r--dts/Bindings/display/bridge/analogix_dp.txt1
-rw-r--r--dts/Bindings/display/bridge/sii902x.txt35
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358767.txt53
-rw-r--r--dts/Bindings/display/cirrus,clps711x-fb.txt4
-rw-r--r--dts/Bindings/display/connector/hdmi-connector.txt1
-rw-r--r--dts/Bindings/display/fsl,dcu.txt9
-rw-r--r--dts/Bindings/display/mediatek/mediatek,hdmi.txt148
-rw-r--r--dts/Bindings/display/msm/dsi.txt117
-rw-r--r--dts/Bindings/display/msm/mdp.txt59
-rw-r--r--dts/Bindings/display/msm/mdp4.txt112
-rw-r--r--dts/Bindings/display/msm/mdp5.txt160
-rw-r--r--dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt7
-rw-r--r--dts/Bindings/display/panel/lg,lp097qx1-spa1.txt7
-rw-r--r--dts/Bindings/display/panel/panel-dpi.txt2
-rw-r--r--dts/Bindings/display/panel/samsung,lsn122dl01-c01.txt7
-rw-r--r--dts/Bindings/display/panel/sharp,lq101k1ly04.txt7
-rw-r--r--dts/Bindings/display/panel/sharp,lq123p1jx31.txt7
-rw-r--r--dts/Bindings/display/panel/starry,kr122ea0sra.txt7
-rw-r--r--dts/Bindings/display/rockchip/analogix_dp-rockchip.txt9
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt13
-rw-r--r--dts/Bindings/dma/mv-xor-v2.txt24
-rw-r--r--dts/Bindings/dma/ti-edma.txt4
-rw-r--r--dts/Bindings/dma/xilinx/xilinx_dma.txt94
-rw-r--r--dts/Bindings/dma/xilinx/xilinx_vdma.txt107
-rw-r--r--dts/Bindings/dma/xilinx/zynqmp_dma.txt27
-rw-r--r--dts/Bindings/extcon/extcon-arizona.txt3
-rw-r--r--dts/Bindings/firmware/qcom,scm.txt28
-rw-r--r--dts/Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt4
-rw-r--r--dts/Bindings/gpio/gpio-clps711x.txt4
-rw-r--r--dts/Bindings/gpio/gpio-max77620.txt25
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt1
-rw-r--r--dts/Bindings/gpio/gpio_oxnas.txt47
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt1
-rw-r--r--dts/Bindings/hwmon/apm-xgene-hwmon.txt14
-rw-r--r--dts/Bindings/hwmon/jc42.txt42
-rw-r--r--dts/Bindings/i2c/i2c-rk3x.txt16
-rw-r--r--dts/Bindings/i2c/i2c.txt7
-rw-r--r--dts/Bindings/i2c/trivial-devices.txt73
-rw-r--r--dts/Bindings/iio/adc/at91_adc.txt12
-rw-r--r--dts/Bindings/iio/adc/brcm,iproc-static-adc.txt41
-rw-r--r--dts/Bindings/iio/adc/max1363.txt63
-rw-r--r--dts/Bindings/iio/chemical/atlas,ec-sm.txt22
-rw-r--r--dts/Bindings/iio/dac/ad5755.txt124
-rw-r--r--dts/Bindings/iio/pressure/bmp085.txt15
-rw-r--r--dts/Bindings/iio/st-sensors.txt1
-rw-r--r--dts/Bindings/input/atmel,captouch.txt36
-rw-r--r--dts/Bindings/input/clps711x-keypad.txt4
-rw-r--r--dts/Bindings/input/raydium_i2c_ts.txt20
-rw-r--r--dts/Bindings/input/rmi4/rmi_i2c.txt9
-rw-r--r--dts/Bindings/input/rotary-encoder.txt4
-rw-r--r--dts/Bindings/input/touchscreen/silead_gsl1680.txt36
-rw-r--r--dts/Bindings/input/touchscreen/sis_i2c.txt33
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.txt3
-rw-r--r--dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt22
-rw-r--r--dts/Bindings/interrupt-controller/cirrus,clps711x-intc.txt4
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt1
-rw-r--r--dts/Bindings/iommu/arm,smmu-v3.txt2
-rw-r--r--dts/Bindings/iommu/mediatek,iommu.txt13
-rw-r--r--dts/Bindings/iommu/msm,iommu-v0.txt64
-rw-r--r--dts/Bindings/leds/backlight/lp855x.txt2
-rw-r--r--dts/Bindings/leds/common.txt4
-rw-r--r--dts/Bindings/leds/leds-gpio.txt4
-rw-r--r--dts/Bindings/leds/leds-pca9532.txt39
-rw-r--r--dts/Bindings/mailbox/brcm,iproc-pdc-mbox.txt23
-rw-r--r--dts/Bindings/media/mediatek-vcodec.txt59
-rw-r--r--dts/Bindings/media/mediatek-vpu.txt31
-rw-r--r--dts/Bindings/media/nokia,n900-ir20
-rw-r--r--dts/Bindings/media/renesas,fcp.txt32
-rw-r--r--dts/Bindings/media/renesas,vsp1.txt5
-rw-r--r--dts/Bindings/media/s5p-cec.txt31
-rw-r--r--dts/Bindings/media/s5p-mfc.txt39
-rw-r--r--dts/Bindings/memory-controllers/atmel,ebi.txt136
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-common.txt21
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt4
-rw-r--r--dts/Bindings/memory-controllers/omap-gpmc.txt7
-rw-r--r--dts/Bindings/mfd/axp20x.txt6
-rw-r--r--dts/Bindings/mfd/da9052-i2c.txt22
-rw-r--r--dts/Bindings/mfd/rn5t618.txt19
-rw-r--r--dts/Bindings/mfd/twl6040.txt4
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt35
-rw-r--r--dts/Bindings/mmc/brcm,bcm2835-sdhci.txt18
-rw-r--r--dts/Bindings/mmc/brcm,bcm7425-sdhci.txt36
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.txt2
-rw-r--r--dts/Bindings/mmc/mmc.txt4
-rw-r--r--dts/Bindings/mtd/atmel-quadspi.txt32
-rw-r--r--dts/Bindings/mtd/brcm,brcmnand.txt1
-rw-r--r--dts/Bindings/mtd/cadence-quadspi.txt56
-rw-r--r--dts/Bindings/mtd/gpmc-nand.txt2
-rw-r--r--dts/Bindings/mtd/hisilicon,fmc-spi-nor.txt24
-rw-r--r--dts/Bindings/mtd/mtk-nand.txt160
-rw-r--r--dts/Bindings/mtd/sunxi-nand.txt6
-rw-r--r--dts/Bindings/net/apm-xgene-enet.txt4
-rw-r--r--dts/Bindings/net/apm-xgene-mdio.txt37
-rw-r--r--dts/Bindings/net/brcm,mdio-mux-iproc.txt59
-rw-r--r--dts/Bindings/net/can/rcar_canfd.txt96
-rw-r--r--dts/Bindings/net/cavium-pip.txt6
-rw-r--r--dts/Bindings/net/cirrus,cs89x0.txt13
-rw-r--r--dts/Bindings/net/cpsw.txt1
-rw-r--r--dts/Bindings/net/davinci-mdio.txt5
-rw-r--r--dts/Bindings/net/dsa/b53.txt97
-rw-r--r--dts/Bindings/net/dsa/dsa.txt280
-rw-r--r--dts/Bindings/net/fsl-fec.txt3
-rw-r--r--dts/Bindings/net/hisilicon-femac-mdio.txt22
-rw-r--r--dts/Bindings/net/hisilicon-femac.txt39
-rw-r--r--dts/Bindings/net/keystone-netcp.txt2
-rw-r--r--dts/Bindings/net/mdio-mux.txt3
-rw-r--r--dts/Bindings/net/micrel.txt10
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt3
-rw-r--r--dts/Bindings/net/socfpga-dwmac.txt19
-rw-r--r--dts/Bindings/net/stmmac.txt3
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore,spi.txt41
-rw-r--r--dts/Bindings/pci/aardvark-pci.txt56
-rw-r--r--dts/Bindings/pci/axis,artpec6-pcie.txt46
-rw-r--r--dts/Bindings/pci/layerscape-pci.txt4
-rw-r--r--dts/Bindings/phy/brcm,mdio-mux-bus-pci.txt27
-rw-r--r--dts/Bindings/phy/brcm-sata-phy.txt4
-rw-r--r--dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt2
-rw-r--r--dts/Bindings/phy/phy-da8xx-usb.txt40
-rw-r--r--dts/Bindings/phy/rockchip-emmc-phy.txt9
-rw-r--r--dts/Bindings/phy/rockchip-usb-phy.txt27
-rw-r--r--dts/Bindings/pinctrl/brcm,iproc-gpio.txt18
-rw-r--r--dts/Bindings/pinctrl/brcm,nsp-pinmux.txt79
-rw-r--r--dts/Bindings/pinctrl/meson,pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt60
-rw-r--r--dts/Bindings/pinctrl/oxnas,pinctrl.txt57
-rw-r--r--dts/Bindings/pinctrl/pinctrl-max77620.txt127
-rw-r--r--dts/Bindings/pinctrl/qcom,mdm9615-pinctrl.txt152
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt5
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-mpp.txt1
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.txt1
-rw-r--r--dts/Bindings/power/max8903-charger.txt25
-rw-r--r--dts/Bindings/power/renesas,apmu.txt31
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt1
-rw-r--r--dts/Bindings/power/reset/brcm,bcm21664-resetmgr.txt (renamed from dts/Bindings/reset/brcm,bcm21664-resetmgr.txt)0
-rw-r--r--dts/Bindings/power/reset/reboot-mode.txt25
-rw-r--r--dts/Bindings/power/reset/syscon-reboot-mode.txt35
-rw-r--r--dts/Bindings/power_supply/axp20x_usb_power.txt3
-rw-r--r--dts/Bindings/powerpc/fsl/cpm_qe/network.txt43
-rw-r--r--dts/Bindings/powerpc/fsl/fman.txt4
-rw-r--r--dts/Bindings/powerpc/opal/oppanel-opal.txt14
-rw-r--r--dts/Bindings/pwm/brcm,iproc-pwm.txt21
-rw-r--r--dts/Bindings/pwm/cirrus,clps711x-pwm.txt5
-rw-r--r--dts/Bindings/pwm/google,cros-ec-pwm.txt23
-rw-r--r--dts/Bindings/pwm/nvidia,tegra20-pwm.txt12
-rw-r--r--dts/Bindings/pwm/pwm-omap-dmtimer.txt4
-rw-r--r--dts/Bindings/pwm/pwm-tiecap.txt38
-rw-r--r--dts/Bindings/pwm/pwm-tiehrpwm.txt38
-rw-r--r--dts/Bindings/pwm/pwm-tipwmss.txt33
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt1
-rw-r--r--dts/Bindings/pwm/st,stmpe-pwm.txt18
-rw-r--r--dts/Bindings/regmap/regmap.txt2
-rw-r--r--dts/Bindings/regulator/da9210.txt12
-rw-r--r--dts/Bindings/regulator/da9211.txt47
-rw-r--r--dts/Bindings/regulator/mt6323-regulator.txt237
-rw-r--r--dts/Bindings/regulator/pwm-regulator.txt26
-rw-r--r--dts/Bindings/regulator/qcom,spmi-regulator.txt6
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt137
-rw-r--r--dts/Bindings/reserved-memory/ramoops.txt48
-rw-r--r--dts/Bindings/reset/amlogic,meson-reset.txt18
-rw-r--r--dts/Bindings/reset/hisilicon,hi6220-reset.txt4
-rw-r--r--dts/Bindings/reset/ti-syscon-reset.txt91
-rw-r--r--dts/Bindings/rng/amlogic,meson-rng.txt14
-rw-r--r--dts/Bindings/rng/brcm,bcm2835.txt8
-rw-r--r--dts/Bindings/rtc/rtc-opal.txt2
-rw-r--r--dts/Bindings/security/tpm/tpm_tis_spi.txt24
-rw-r--r--dts/Bindings/serial/8250.txt19
-rw-r--r--dts/Bindings/serial/cirrus,clps711x-uart.txt4
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/qcom,msm-uartdm.txt4
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt6
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/cpm.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/cpm.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/cpm/brg.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/cpm/i2c.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/cpm/pic.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/cpm/usb.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/gpio.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/gpio.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/network.txt124
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/qe.txt)52
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/firmware.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/qe/firmware.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/par_io.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/qe/par_io.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/pincfg.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/qe/ucc.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/qe/usb.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/serial.txt (renamed from dts/Bindings/powerpc/fsl/cpm_qe/serial.txt)0
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/uqe_serial.txt17
-rw-r--r--dts/Bindings/soc/qcom/qcom,smp2p.txt4
-rw-r--r--dts/Bindings/soc/qcom/qcom,smsm.txt4
-rw-r--r--dts/Bindings/soc/qcom/qcom,wcnss.txt116
-rw-r--r--dts/Bindings/sound/adi,adau17x1.txt8
-rw-r--r--dts/Bindings/sound/adi,adau7002.txt19
-rw-r--r--dts/Bindings/sound/brcm,cygnus-audio.txt67
-rw-r--r--dts/Bindings/sound/bt-sco.txt2
-rw-r--r--dts/Bindings/sound/cs35l33.txt126
-rw-r--r--dts/Bindings/sound/cs53l30.txt44
-rw-r--r--dts/Bindings/sound/designware-i2s.txt4
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt2
-rw-r--r--dts/Bindings/sound/max98504.txt44
-rw-r--r--dts/Bindings/sound/max9860.txt28
-rw-r--r--dts/Bindings/sound/mt2701-afe-pcm.txt150
-rw-r--r--dts/Bindings/sound/mt2701-cs42448.txt43
-rw-r--r--dts/Bindings/sound/mt8173-rt5650.txt10
-rw-r--r--dts/Bindings/sound/omap-mcpdm.txt10
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt2
-rw-r--r--dts/Bindings/sound/rockchip-i2s.txt5
-rw-r--r--dts/Bindings/sound/rt5514.txt5
-rw-r--r--dts/Bindings/sound/samsung,odroidx2-max98090.txt35
-rw-r--r--dts/Bindings/sound/sgtl5000.txt18
-rw-r--r--dts/Bindings/sound/simple-card.txt2
-rw-r--r--dts/Bindings/sound/st,sti-asoc-card.txt20
-rw-r--r--dts/Bindings/sound/sun4i-i2s.txt34
-rw-r--r--dts/Bindings/spi/fsl-imx-cspi.txt5
-rw-r--r--dts/Bindings/spi/spi-bus.txt35
-rw-r--r--dts/Bindings/spi/spi-clps711x.txt33
-rw-r--r--dts/Bindings/spi/spi-davinci.txt2
-rw-r--r--dts/Bindings/spi/spi-orion.txt49
-rw-r--r--dts/Bindings/spi/spi-rockchip.txt11
-rw-r--r--dts/Bindings/spi/spi-samsung.txt15
-rw-r--r--dts/Bindings/spi/ti_qspi.txt2
-rw-r--r--dts/Bindings/timer/allwinner,sun5i-a13-hstimer.txt2
-rw-r--r--dts/Bindings/timer/cirrus,clps711x-timer.txt6
-rw-r--r--dts/Bindings/timer/oxsemi,rps-timer.txt17
-rw-r--r--dts/Bindings/timer/rockchip,rk-timer.txt (renamed from dts/Bindings/timer/rockchip,rk3288-timer.txt)6
-rw-r--r--dts/Bindings/ufs/tc-dwc-g210-pltfrm.txt26
-rw-r--r--dts/Bindings/ufs/ufshcd-pltfrm.txt4
-rw-r--r--dts/Bindings/usb/atmel-usb.txt14
-rw-r--r--dts/Bindings/usb/ci-hdrc-usb2.txt2
-rw-r--r--dts/Bindings/usb/nvidia,tegra124-xusb.txt8
-rw-r--r--dts/Bindings/usb/usb-ohci.txt2
-rw-r--r--dts/Bindings/vendor-prefixes.txt5
-rw-r--r--dts/Bindings/watchdog/aspeed-wdt.txt16
-rw-r--r--dts/Bindings/watchdog/meson-gxbb-wdt.txt16
-rw-r--r--dts/Bindings/watchdog/qcom-wdt.txt4
-rw-r--r--dts/Bindings/watchdog/renesas-wdt.txt6
265 files changed, 6404 insertions, 601 deletions
diff --git a/dts/Bindings/arm/altera/socfpga-eccmgr.txt b/dts/Bindings/arm/altera/socfpga-eccmgr.txt
index 5a6b160..b545856 100644
--- a/dts/Bindings/arm/altera/socfpga-eccmgr.txt
+++ b/dts/Bindings/arm/altera/socfpga-eccmgr.txt
@@ -61,7 +61,9 @@ Required Properties:
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
- interrupt. Note the rising edge type.
+ interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
+- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses
Subcomponents:
@@ -70,11 +72,23 @@ L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg : Address and size for ECC block registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
+Ethernet FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-eth-mac-ecc"
+- reg : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent Ethernet node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
Example:
@@ -85,15 +99,37 @@ Example:
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
ranges;
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+ <32 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x90>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+ <33 IRQ_TYPE_LEVEL_HIGH> ;
+ };
+
+ emac0-rx-ecc@ff8c0800 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0800 0x400>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+ <36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-tx-ecc@ff8c0c00 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0c00 0x400>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+ <37 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/dts/Bindings/arm/arm,scpi.txt b/dts/Bindings/arm/arm,scpi.txt
index 313dabd..faa4b44 100644
--- a/dts/Bindings/arm/arm,scpi.txt
+++ b/dts/Bindings/arm/arm,scpi.txt
@@ -87,10 +87,33 @@ Required properties:
implementation for the IDs to use. For Juno
R0 and Juno R1 refer to [3].
+Power domain bindings for the power domains based on SCPI Message Protocol
+------------------------------------------------------------
+
+This binding uses the generic power domain binding[4].
+
+PM domain providers
+===================
+
+Required properties:
+ - #power-domain-cells : Should be 1. Contains the device or the power
+ domain ID value used by SCPI commands.
+ - num-domains: Total number of power domains provided by SCPI. This is
+ needed as the SCPI message protocol lacks a mechanism to
+ query this information at runtime.
+
+PM domain consumers
+===================
+
+Required properties:
+ - power-domains : A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle.
+
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/thermal/thermal.txt
[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
+[4] Documentation/devicetree/bindings/power/power_domain.txt
Example:
@@ -144,6 +167,12 @@ scpi_protocol: scpi@2e000000 {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
+
+ scpi_devpd: scpi-power-domains {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
};
cpu@0 {
@@ -156,6 +185,7 @@ hdlcd@7ff60000 {
...
reg = <0 0x7ff60000 0 0x1000>;
clocks = <&scpi_clk 4>;
+ power-domains = <&scpi_devpd 1>;
};
thermal-zones {
@@ -186,3 +216,7 @@ The thermal-sensors property in the soc_thermal node uses the
temperature sensor provided by SCP firmware to setup a thermal
zone. The ID "3" is the sensor identifier for the temperature sensor
as used by the firmware.
+
+The num-domains property in scpi-power-domains domain specifies that
+SCPI provides 2 power domains. The hdlcd node uses the power domain with
+domain ID 1.
diff --git a/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
index 8240c02..e3f9969 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
@@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
The enable method is specified by defining the following required
-properties in the "cpus" device tree node:
+properties in the "cpu" device tree node:
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <...>;
@@ -19,8 +19,6 @@ Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
cpu0: cpu@0 {
device_type = "cpu";
@@ -32,5 +30,7 @@ Example:
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "brcm,bcm11351-cpu-method";
+ secondary-boot-reg = <0x3500417c>;
};
};
diff --git a/dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
new file mode 100644
index 0000000..a3af54c
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Kona Family CPU Enable Method
+--------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+ BCM23550
+
+The enable method is specified by defining the following required
+properties in the "cpu" device tree node:
+ - enable-method = "brcm,bcm23550";
+ - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU. The value written to the register is
+formed by encoding the target CPU id into the low bits of the
+physical start address it should jump to.
+
+Example:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "brcm,bcm23550";
+ secondary-boot-reg = <0x3500417c>;
+ };
+ };
diff --git a/dts/Bindings/arm/bcm/brcm,bcm23550.txt b/dts/Bindings/arm/bcm/brcm,bcm23550.txt
new file mode 100644
index 0000000..080baad
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm23550.txt
@@ -0,0 +1,15 @@
+Broadcom BCM23550 device tree bindings
+--------------------------------------
+
+This document describes the device tree bindings for boards with the BCM23550
+SoC.
+
+Required root node property:
+ - compatible: brcm,bcm23550
+
+Example:
+ / {
+ model = "BCM23550 SoC";
+ compatible = "brcm,bcm23550";
+ [...]
+ }
diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
index 11d3056..6ffe087 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
Required root node properties:
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
+Raspberry Pi 3 Model B
+Required root node properties:
+compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
+
Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 93147c0..fcbae6a 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -12,14 +12,33 @@ its hardware characteristcs.
* compatible: These have to be supplemented with "arm,primecell" as
drivers are using the AMBA bus interface. Possible values include:
- - "arm,coresight-etb10", "arm,primecell";
- - "arm,coresight-tpiu", "arm,primecell";
- - "arm,coresight-tmc", "arm,primecell";
- - "arm,coresight-funnel", "arm,primecell";
- - "arm,coresight-etm3x", "arm,primecell";
- - "arm,coresight-etm4x", "arm,primecell";
- - "qcom,coresight-replicator1x", "arm,primecell";
- - "arm,coresight-stm", "arm,primecell"; [1]
+ - Embedded Trace Buffer (version 1.0):
+ "arm,coresight-etb10", "arm,primecell";
+
+ - Trace Port Interface Unit:
+ "arm,coresight-tpiu", "arm,primecell";
+
+ - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
+ Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
+ configuration. The configuration mode (ETB, ETF, ETR) is
+ discovered at boot time when the device is probed.
+ "arm,coresight-tmc", "arm,primecell";
+
+ - Trace Funnel:
+ "arm,coresight-funnel", "arm,primecell";
+
+ - Embedded Trace Macrocell (version 3.x) and
+ Program Flow Trace Macrocell:
+ "arm,coresight-etm3x", "arm,primecell";
+
+ - Embedded Trace Macrocell (version 4.x):
+ "arm,coresight-etm4x", "arm,primecell";
+
+ - Qualcomm Configurable Replicator (version 1.x):
+ "qcom,coresight-replicator1x", "arm,primecell";
+
+ - System Trace Macrocell:
+ "arm,coresight-stm", "arm,primecell"; [1]
* reg: physical base address and length of the register
set(s) of the component.
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 3f0cbbb..e6782d5 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -193,6 +193,8 @@ nodes to be present and contain the properties described below.
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,realview-smp"
+ "brcm,bcm11351-cpu-method"
+ "brcm,bcm23550"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
@@ -204,6 +206,7 @@ nodes to be present and contain the properties described below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+ "renesas,apmu"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
diff --git a/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt b/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt
new file mode 100644
index 0000000..115c5be
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Required properties:
+- compatible: "hisilicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller@12010000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12010000 0x1000>;
+};
diff --git a/dts/Bindings/arm/l2c2x0.txt b/dts/Bindings/arm/l2c2x0.txt
index c453ab5..917199f 100644
--- a/dts/Bindings/arm/l2c2x0.txt
+++ b/dts/Bindings/arm/l2c2x0.txt
@@ -86,10 +86,10 @@ Optional properties:
firmware)
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
disable), <1> (forcibly enable), property absent (OS specific behavior,
- preferrably retain firmware settings)
+ preferably retain firmware settings)
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
<1> (forcibly enable), property absent (OS specific behavior,
- preferrably retain firmware settings)
+ preferably retain firmware settings)
Example:
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index d9c2a37..c860b24 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -10,6 +10,7 @@ compatible: Must contain one of
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
+ "mediatek,mt6755"
"mediatek,mt6795"
"mediatek,mt7623"
"mediatek,mt8127"
@@ -31,6 +32,9 @@ Supported boards:
- Evaluation board for MT6592:
Required root node properties:
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
+- Evaluation phone for MT6755(Helio P10):
+ Required root node properties:
+ - compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
diff --git a/dts/Bindings/arm/olimex.txt b/dts/Bindings/arm/olimex.txt
index 007fb5c..d726aec 100644
--- a/dts/Bindings/arm/olimex.txt
+++ b/dts/Bindings/arm/olimex.txt
@@ -1,5 +1,9 @@
-Olimex i.MX Platforms Device Tree Bindings
-------------------------------------------
+Olimex Device Tree Bindings
+---------------------------
+
+SAM9-L9260 Board
+Required root node properties:
+ - compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
i.MX23 Olinuxino Low Cost Board
Required root node properties:
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
index 74d5417..61c8b46 100644
--- a/dts/Bindings/arm/pmu.txt
+++ b/dts/Bindings/arm/pmu.txt
@@ -39,7 +39,9 @@ Optional properties:
When using a PPI, specifies a list of phandles to CPU
nodes corresponding to the set of CPUs which have
a PMU of this type signalling the PPI listed in the
- interrupts property.
+ interrupts property, unless this is already specified
+ by the PPI interrupt specifier itself (in which case
+ the interrupt-affinity property shouldn't be present).
This property should be present when there is more than
a single SPI.
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 715d960..6668645 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -107,6 +107,9 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
+- Rockchip RK3229 Evaluation board:
+ - compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index f5deace..0ea7f14 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -47,6 +47,7 @@ Required root node properties:
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
+ - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
Odroid XU3 Lite board.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 9cf67e4..1df32d3 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -29,6 +29,8 @@ SoCs:
compatible = "renesas,r8a7794"
- R-Car H3 (R8A77950)
compatible = "renesas,r8a7795"
+ - R-Car M3-W (R8A77960)
+ compatible = "renesas,r8a7796"
Boards:
@@ -39,6 +41,8 @@ Boards:
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
+ - Blanche (RTP0RC7792SEB00010S)
+ compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
@@ -61,5 +65,7 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
+ - Salvator-X
+ compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/dts/Bindings/arm/tegra.txt b/dts/Bindings/arm/tegra.txt
index 73278c6..b5a4342 100644
--- a/dts/Bindings/arm/tegra.txt
+++ b/dts/Bindings/arm/tegra.txt
@@ -32,7 +32,11 @@ board-specific compatible values:
nvidia,whistler
toradex,apalis_t30
toradex,apalis_t30-eval
+ toradex,apalis-tk1
+ toradex,apalis-tk1-eval
toradex,colibri_t20-512
+ toradex,colibri_t30
+ toradex,colibri_t30-eval-v3
toradex,iris
Trusted Foundations
diff --git a/dts/Bindings/arm/xen.txt b/dts/Bindings/arm/xen.txt
index 0f7b9c2..c9b9321 100644
--- a/dts/Bindings/arm/xen.txt
+++ b/dts/Bindings/arm/xen.txt
@@ -11,10 +11,32 @@ the following properties:
memory where the grant table should be mapped to, using an
HYPERVISOR_memory_op hypercall. The memory region is large enough to map
the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
+ This property is unnecessary when booting Dom0 using ACPI.
- interrupts: the interrupt used by Xen to inject event notifications.
A GIC node is also required.
+ This property is unnecessary when booting Dom0 using ACPI.
+To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
+under /hypervisor with following parameters:
+
+________________________________________________________________________________
+Name | Size | Description
+================================================================================
+xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System
+ | | Table.
+--------------------------------------------------------------------------------
+xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory
+ | | map.
+--------------------------------------------------------------------------------
+xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map
+ | | pointed to in previous entry.
+--------------------------------------------------------------------------------
+xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI
+ | | memory map.
+--------------------------------------------------------------------------------
+xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format.
+--------------------------------------------------------------------------------
Example (assuming #address-cells = <2> and #size-cells = <2>):
@@ -22,4 +44,17 @@ hypervisor {
compatible = "xen,xen-4.3", "xen,xen";
reg = <0 0xb0000000 0 0x20000>;
interrupts = <1 15 0xf08>;
+ uefi {
+ xen,uefi-system-table = <0xXXXXXXXX>;
+ xen,uefi-mmap-start = <0xXXXXXXXX>;
+ xen,uefi-mmap-size = <0xXXXXXXXX>;
+ xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
+ xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
+ };
};
+
+The format and meaning of the "xen,uefi-*" parameters are similar to those in
+Documentation/arm/uefi.txt, which are provided by the regular UEFI stub. However
+they differ because they are provided by the Xen hypervisor, together with a set
+of UEFI runtime services implemented via hypercalls, see
+http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index 87adfb2..fedc213 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -10,6 +10,7 @@ PHYs.
Required properties:
- compatible : compatible string, one of:
- "allwinner,sun4i-a10-ahci"
+ - "brcm,iproc-ahci"
- "hisilicon,hisi-ahci"
- "cavium,octeon-7130-ahci"
- "ibm,476gtr-ahci"
diff --git a/dts/Bindings/ata/brcm,sata-brcmstb.txt b/dts/Bindings/ata/brcm,sata-brcm.txt
index 6087283..0a5b3b4 100644
--- a/dts/Bindings/ata/brcm,sata-brcmstb.txt
+++ b/dts/Bindings/ata/brcm,sata-brcm.txt
@@ -1,13 +1,14 @@
-* Broadcom SATA3 AHCI Controller for STB
+* Broadcom SATA3 AHCI Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : should be one or more of
- "brcm,bcm7425-ahci"
- "brcm,bcm7445-ahci"
- "brcm,sata3-ahci"
+ "brcm,bcm7425-ahci"
+ "brcm,bcm7445-ahci"
+ "brcm,bcm-nsp-ahci"
+ "brcm,sata3-ahci"
- reg : register mappings for AHCI and SATA_TOP_CTRL
- reg-names : "ahci" and "top-ctrl"
- interrupts : interrupt mapping for SATA IRQ
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
new file mode 100644
index 0000000..7ff13be
--- /dev/null
+++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
@@ -0,0 +1,45 @@
+NVIDIA Tegra ACONNECT Bus
+
+The Tegra ACONNECT bus is an AXI switch which is used to connnect various
+components inside the Audio Processing Engine (APE). All CPU accesses to
+the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
+
+Required properties:
+- compatible: Must be "nvidia,tegra210-aconnect".
+- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
+ and APE interface clock (TEGRA210_CLK_APB2APE).
+- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
+ 'clocks' entries.
+- power-domains: Must contain a phandle that points to the audio powergate
+ (namely 'aud') for Tegra210.
+- #address-cells: The number of cells used to represent physical base addresses
+ in the aconnect address space. Should be 1.
+- #size-cells: The number of cells used to represent the size of an address
+ range in the aconnect address space. Should be 1.
+- ranges: Mapping of the aconnect address space to the CPU address space.
+
+All devices accessed via the ACONNNECT are described by child-nodes.
+
+Example:
+
+ aconnect@702c0000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&tegra_car TEGRA210_CLK_APE>,
+ <&tegra_car TEGRA210_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&pd_audio>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
+
+ status = "disabled";
+
+ child1 {
+ ...
+ };
+
+ child2 {
+ ...
+ };
+ };
diff --git a/dts/Bindings/clock/amlogic,gxbb-clkc.txt b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
new file mode 100644
index 0000000..ce06435
--- /dev/null
+++ b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
@@ -0,0 +1,36 @@
+* Amlogic GXBB Clock and Reset Unit
+
+The Amlogic GXBB clock controller generates and supplies clock to various
+controllers within the SoC.
+
+Required Properties:
+
+- compatible: should be "amlogic,gxbb-clkc"
+- reg: physical base address of the clock controller and length of memory
+ mapped region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
+used in device tree sources.
+
+Example: Clock controller node:
+
+ clkc: clock-controller@c883c000 {
+ #clock-cells = <1>;
+ compatible = "amlogic,gxbb-clkc";
+ reg = <0x0 0xc883c000 0x0 0x3db>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart_AO: serial@c81004c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0xc81004c0 0x14>;
+ interrupts = <0 90 1>;
+ clocks = <&clkc CLKID_CLK81>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/clock/clps711x-clock.txt b/dts/Bindings/clock/clps711x-clock.txt
index ce5a747..f1bd53f 100644
--- a/dts/Bindings/clock/clps711x-clock.txt
+++ b/dts/Bindings/clock/clps711x-clock.txt
@@ -1,7 +1,7 @@
* Clock bindings for the Cirrus Logic CLPS711X CPUs
Required properties:
-- compatible : Shall contain "cirrus,clps711x-clk".
+- compatible : Shall contain "cirrus,ep7209-clk".
- reg : Address of the internal register set.
- startup-frequency: Factory set CPU startup frequency in HZ.
- #clock-cells : Should be <1>.
@@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs.
Example:
clks: clks@80000000 {
#clock-cells = <1>;
- compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
+ compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
reg = <0x80000000 0xc000>;
startup-frequency = <73728000>;
};
diff --git a/dts/Bindings/clock/fixed-factor-clock.txt b/dts/Bindings/clock/fixed-factor-clock.txt
index 1bae852..189467a 100644
--- a/dts/Bindings/clock/fixed-factor-clock.txt
+++ b/dts/Bindings/clock/fixed-factor-clock.txt
@@ -14,6 +14,10 @@ Required properties:
Optional properties:
- clock-output-names : From common clock binding.
+Some clocks that require special treatments are also handled by that
+driver, with the compatibles:
+ - allwinner,sun4i-a10-pll3-2x-clk
+
Example:
clock {
compatible = "fixed-factor-clock";
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index fefb802..394d725 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -13,7 +13,8 @@ They provide the following functionalities:
Required Properties:
- compatible: Must be one of:
- - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
+ - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
+ - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
@@ -21,8 +22,8 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7795)
- - "extalr" (r8a7795)
+ - "extal" (r8a7795, r8a7796)
+ - "extalr" (r8a7795, r8a7796)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt b/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt
index 16ed181..da578eb 100644
--- a/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -17,6 +17,7 @@ Required Properties:
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
+ - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
diff --git a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 2a9a8ed..f8c05bb 100644
--- a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -10,6 +10,7 @@ Required Properties:
- compatible: Must be one of
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
+ - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
and "renesas,rcar-gen2-cpg-clocks" as a fallback.
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
new file mode 100644
index 0000000..cb91507
--- /dev/null
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -0,0 +1,24 @@
+Allwinner Clock Control Unit Binding
+------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatible:
+ - "allwinner,sun8i-h3-ccu"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the oscillators feeding the CCU. Two are needed:
+ - "hosc": the high frequency oscillator (usually at 24MHz)
+ - "losc": the low frequency oscillator (usually at 32kHz)
+- clock-names: Must contain the clock names described just above
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+ccu: clock@01c20000 {
+ compatible = "allwinner,sun8i-h3-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
diff --git a/dts/Bindings/display/arm,malidp.txt b/dts/Bindings/display/arm,malidp.txt
new file mode 100644
index 0000000..2f78709
--- /dev/null
+++ b/dts/Bindings/display/arm,malidp.txt
@@ -0,0 +1,65 @@
+ARM Mali-DP
+
+The following bindings apply to a family of Display Processors sold as
+licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
+DP650 processors that offer multiple composition layers, support for
+rotation and scaling output.
+
+Required properties:
+ - compatible: should be one of
+ "arm,mali-dp500"
+ "arm,mali-dp550"
+ "arm,mali-dp650"
+ depending on the particular implementation present in the hardware
+ - reg: Physical base address and size of the block of registers used by
+ the processor.
+ - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
+ interrupt client nodes.
+ - interrupt-names: name of the engine inside the processor that will
+ use the corresponding interrupt. Should be one of "DE" or "SE".
+ - clocks: A list of phandle + clock-specifier pairs, one for each entry
+ in 'clock-names'
+ - clock-names: A list of clock names. It should contain:
+ - "pclk": for the APB interface clock
+ - "aclk": for the AXI interface clock
+ - "mclk": for the main processor clock
+ - "pxlclk": for the pixel clock feeding the output PLL of the processor.
+ - arm,malidp-output-port-lines: Array of u8 values describing the number
+ of output lines per channel (R, G and B).
+
+Required sub-nodes:
+ - port: The Mali DP connection to an encoder input port. The connection
+ is modelled using the OF graph bindings specified in
+ Documentation/devicetree/bindings/graph.txt
+
+Optional properties:
+ - memory-region: phandle to a node describing memory (see
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
+ to be used for the framebuffer; if not present, the framebuffer may
+ be located anywhere in memory.
+
+
+Example:
+
+/ {
+ ...
+
+ dp0: malidp@6f200000 {
+ compatible = "arm,mali-dp650";
+ reg = <0 0x6f200000 0 0x20000>;
+ memory-region = <&display_reserved>;
+ interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
+ <0 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "DE", "SE";
+ clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ port {
+ dp0_output: endpoint {
+ remote-endpoint = <&tda998x_2_input>;
+ };
+ };
+ };
+
+ ...
+};
diff --git a/dts/Bindings/display/bridge/adi,adv7511.txt b/dts/Bindings/display/bridge/adi,adv7511.txt
index 96c25ee..6532a59 100644
--- a/dts/Bindings/display/bridge/adi,adv7511.txt
+++ b/dts/Bindings/display/bridge/adi,adv7511.txt
@@ -1,13 +1,19 @@
-Analog Device ADV7511(W)/13 HDMI Encoders
+Analog Device ADV7511(W)/13/33 HDMI Encoders
-----------------------------------------
-The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters
+The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters
compatible with HDMI 1.4 and DVI 1.0. They support color space conversion,
-S/PDIF, CEC and HDCP.
+S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while
+the others support RGB interface.
Required properties:
-- compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513"
+- compatible: Should be one of:
+ "adi,adv7511"
+ "adi,adv7511w"
+ "adi,adv7513"
+ "adi,adv7533"
+
- reg: I2C slave address
The ADV7511 supports a large number of input data formats that differ by their
@@ -32,6 +38,11 @@ The following input format properties are required except in "rgb 1x" and
- adi,input-justification: The input bit justification ("left", "evenly",
"right").
+The following properties are required for ADV7533:
+
+- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
+ be one of 1, 2, 3 or 4.
+
Optional properties:
- interrupts: Specifier for the ADV7511 interrupt
@@ -42,13 +53,18 @@ Optional properties:
- adi,embedded-sync: The input uses synchronization signals embedded in the
data stream (similar to BT.656). Defaults to separate H/V synchronization
signals.
+- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
+ generator. The chip will rely on the sync signals in the DSI data lanes,
+ rather than generate its own timings for HDMI output.
Required nodes:
The ADV7511 has two video ports. Their connections are modelled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-- Video port 0 for the RGB or YUV input
+- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the
+ remote endpoint phandle should be a reference to a valid mipi_dsi_host device
+ node.
- Video port 1 for the HDMI output
diff --git a/dts/Bindings/display/bridge/analogix_dp.txt b/dts/Bindings/display/bridge/analogix_dp.txt
index 4f2ba8c..4a0f4f7 100644
--- a/dts/Bindings/display/bridge/analogix_dp.txt
+++ b/dts/Bindings/display/bridge/analogix_dp.txt
@@ -5,6 +5,7 @@ Required properties for dp-controller:
platform specific such as:
* "samsung,exynos5-dp"
* "rockchip,rk3288-dp"
+ * "rockchip,rk3399-edp"
-reg:
physical base address of the controller and length
of memory mapped region.
diff --git a/dts/Bindings/display/bridge/sii902x.txt b/dts/Bindings/display/bridge/sii902x.txt
new file mode 100644
index 0000000..56a3e68
--- /dev/null
+++ b/dts/Bindings/display/bridge/sii902x.txt
@@ -0,0 +1,35 @@
+sii902x HDMI bridge bindings
+
+Required properties:
+ - compatible: "sil,sii9022"
+ - reg: i2c address of the bridge
+
+Optional properties:
+ - interrupts-extended or interrupt-parent + interrupts: describe
+ the interrupt line used to inform the host about hotplug events.
+ - reset-gpios: OF device-tree gpio specification for RST_N pin.
+
+Optional subnodes:
+ - video input: this subnode can contain a video input port node
+ to connect the bridge to a display controller output (See this
+ documentation [1]).
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ hdmi-bridge@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ reset-gpios = <&pioA 1 0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dc_out>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/toshiba,tc358767.txt b/dts/Bindings/display/bridge/toshiba,tc358767.txt
new file mode 100644
index 0000000..e3f6aa6
--- /dev/null
+++ b/dts/Bindings/display/bridge/toshiba,tc358767.txt
@@ -0,0 +1,53 @@
+Toshiba TC358767 eDP bridge bindings
+
+Required properties:
+ - compatible: "toshiba,tc358767"
+ - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
+ - clock-names: should be "ref"
+ - clocks: OF device-tree clock specification for refclk input. The reference
+ clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
+
+Optional properties:
+ - shutdown-gpios: OF device-tree gpio specification for SD pin
+ (active high shutdown input)
+ - reset-gpios: OF device-tree gpio specification for RSTX pin
+ (active low system reset)
+ - ports: the ports node can contain video interface port nodes to connect
+ to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
+ - port@0: DSI input port
+ - port@1: DPI input port
+ - port@2: eDP/DP output port
+
+[1]: Documentation/devicetree/bindings/graph.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@68 {
+ compatible = "toshiba,tc358767";
+ reg = <0x68>;
+ shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ clock-names = "ref";
+ clocks = <&edp_refclk>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ bridge_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/cirrus,clps711x-fb.txt b/dts/Bindings/display/cirrus,clps711x-fb.txt
index d685be8..e9c6574 100644
--- a/dts/Bindings/display/cirrus,clps711x-fb.txt
+++ b/dts/Bindings/display/cirrus,clps711x-fb.txt
@@ -1,7 +1,7 @@
* Currus Logic CLPS711X Framebuffer
Required properties:
-- compatible: Shall contain "cirrus,clps711x-fb".
+- compatible: Shall contain "cirrus,ep7209-fb".
- reg : Physical base address and length of the controller's registers +
location and size of the framebuffer memory.
- clocks : phandle + clock specifier pair of the FB reference clock.
@@ -18,7 +18,7 @@ Optional properties:
Example:
fb: fb@800002c0 {
- compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb";
+ compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
clocks = <&clks 2>;
lcd-supply = <&reg5v0>;
diff --git a/dts/Bindings/display/connector/hdmi-connector.txt b/dts/Bindings/display/connector/hdmi-connector.txt
index acd5668..508aee4 100644
--- a/dts/Bindings/display/connector/hdmi-connector.txt
+++ b/dts/Bindings/display/connector/hdmi-connector.txt
@@ -8,6 +8,7 @@ Required properties:
Optional properties:
- label: a symbolic name for the connector
- hpd-gpios: HPD GPIO number
+- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
Required nodes:
- Video port for HDMI input
diff --git a/dts/Bindings/display/fsl,dcu.txt b/dts/Bindings/display/fsl,dcu.txt
index ae55cde..63ec2a6 100644
--- a/dts/Bindings/display/fsl,dcu.txt
+++ b/dts/Bindings/display/fsl,dcu.txt
@@ -12,7 +12,7 @@ Required properties:
- clock-names: Should be "dcu" and "pix"
See ../clocks/clock-bindings.txt for details.
- big-endian Boolean property, LS1021A DCU registers are big-endian.
-- fsl,panel: The phandle to panel node.
+- port Video port for the panel output
Optional properties:
- fsl,tcon: The phandle to the timing controller node.
@@ -24,6 +24,11 @@ dcu: dcu@2ce0000 {
clocks = <&platform_clk 0>, <&platform_clk 0>;
clock-names = "dcu", "pix";
big-endian;
- fsl,panel = <&panel>;
fsl,tcon = <&tcon>;
+
+ port {
+ dcu_out: endpoint {
+ remote-endpoint = <&panel_out>;
+ };
+ };
};
diff --git a/dts/Bindings/display/mediatek/mediatek,hdmi.txt b/dts/Bindings/display/mediatek/mediatek,hdmi.txt
new file mode 100644
index 0000000..7b12424
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,hdmi.txt
@@ -0,0 +1,148 @@
+Mediatek HDMI Encoder
+=====================
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,<chip>-hdmi".
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
+- phys: phandle link to the HDMI PHY node.
+ See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- mediatek,syscon-hdmi: phandle link and register offset to the system
+ configuration registers. For mt8173 this must be offset 0x900 into the
+ MMSYS_CONFIG region: <&mmsys 0x900>.
+- ports: A node containing input and output port nodes with endpoint
+ definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port@0: The input port in the ports node should be connected to a DPI output
+ port.
+- port@1: The output port in the ports node should be connected to the input
+ port of a connector node that contains a ddc-i2c-bus property, or to the
+ input port of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI CEC
+========
+
+The HDMI CEC controller handles hotplug detection and CEC communication.
+
+Required properties:
+- compatible: Should be "mediatek,<chip>-cec"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clock
+
+HDMI DDC
+========
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Should be "ddc-i2c".
+
+HDMI PHY
+========
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,<chip>-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- clocks: PLL reference clock
+- clock-names: must contain "pll_ref"
+- clock-output-names: must be "hdmitx_dig_cts" on mt8173
+- #phy-cells: must be <0>
+- #clock-cells: must be <0>
+
+Optional properties:
+- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+};
+
+hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0 0x11012000 0 0x1c>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+};
+
+hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
+ assigned-clock-parents = <&hdmi_phy>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+};
+
+connector {
+ compatible = "hdmi-connector";
+ type = "a";
+ ddc-i2c-bus = <&hdmiddc0>;
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+};
diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index f5948c4..6b1cab1 100644
--- a/dts/Bindings/display/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -11,8 +11,7 @@ Required properties:
be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clocks: Phandles to device clocks.
- clock-names: the following clocks are required:
* "mdp_core_clk"
* "iface_clk"
@@ -23,16 +22,21 @@ Required properties:
* "core_clk"
For DSIv2, we need an additional clock:
* "src_clk"
+- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
+- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
+ by a DSI PHY block. See [1] for details on clock bindings.
- vdd-supply: phandle to vdd regulator device node
- vddio-supply: phandle to vdd-io regulator device node
- vdda-supply: phandle to vdda regulator device node
-- qcom,dsi-phy: phandle to DSI PHY device node
+- phys: phandle to DSI PHY device node
+- phy-names: the name of the corresponding PHY device
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
+- ports: Contains 2 DSI controller ports as child nodes. Each port contains
+ an endpoint subnode as defined in [2] and [3].
Optional properties:
- panel@0: Node of panel connected to this DSI controller.
- See files in Documentation/devicetree/bindings/display/panel/ for each supported
- panel.
+ See files in [4] for each supported panel.
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
driving a panel which needs 2 DSI links.
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
@@ -44,34 +48,38 @@ Optional properties:
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
-- port: DSI controller output port, containing one endpoint subnode.
+- ports: contains DSI controller input and output ports as children, each
+ containing one endpoint subnode.
DSI Endpoint properties:
- - remote-endpoint: set to phandle of the connected panel's endpoint.
- See Documentation/devicetree/bindings/graph.txt for device graph info.
- - qcom,data-lane-map: this describes how the logical DSI lanes are mapped
- to the physical lanes on the given platform. The value contained in
- index n describes what logical data lane is mapped to the physical data
- lane n (DATAn, where n lies between 0 and 3).
+ - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
+ input endpoint. For port@1, set to the MDP interface output. See [2] for
+ device graph info.
+
+ - data-lanes: this describes how the physical DSI data lanes are mapped
+ to the logical lanes on the given platform. The value contained in
+ index n describes what physical lane is mapped to the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock lane position is fixed
+ and can't be changed. Hence, they aren't a part of the DT bindings. See
+ [3] for more info on the data-lanes property.
For example:
- qcom,data-lane-map = <3 0 1 2>;
+ data-lanes = <3 0 1 2>;
- The above mapping describes that the logical data lane DATA3 is mapped to
- the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
- to phys DATA2 and logic DATA2 to phys DATA3.
+ The above mapping describes that the logical data lane DATA0 is mapped to
+ the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
+ to phys DATA1 and logic DATA3 to phys DATA2.
There are only a limited number of physical to logical mappings possible:
-
- "0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
- "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
- "2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
- "1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
- "0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
- "1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
- "2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
- "3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
+ <0 1 2 3>
+ <1 2 3 0>
+ <2 3 0 1>
+ <3 0 1 2>
+ <0 3 2 1>
+ <1 0 3 2>
+ <2 1 0 3>
+ <3 2 1 0>
DSI PHY:
Required properties:
@@ -86,11 +94,12 @@ Required properties:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
+- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
+ 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
* "iface_clk"
- vddio-supply: phandle to vdd-io regulator device node
@@ -99,11 +108,16 @@ Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
regulator is wanted.
+[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
+[2] Documentation/devicetree/bindings/graph.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/display/panel/
+
Example:
- mdss_dsi0: qcom,mdss_dsi@fd922800 {
+ dsi0: dsi@fd922800 {
compatible = "qcom,mdss-dsi-ctrl";
qcom,dsi-host-index = <0>;
- interrupt-parent = <&mdss_mdp>;
+ interrupt-parent = <&mdp>;
interrupts = <4 0>;
reg-names = "dsi_ctrl";
reg = <0xfd922800 0x200>;
@@ -124,19 +138,48 @@ Example:
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_PCLK0_CLK>;
+
+ assigned-clocks =
+ <&mmcc BYTE0_CLK_SRC>,
+ <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents =
+ <&dsi_phy0 0>,
+ <&dsi_phy0 1>;
+
vdda-supply = <&pma8084_l2>;
vdd-supply = <&pma8084_l22>;
vddio-supply = <&pma8084_l12>;
- qcom,dsi-phy = <&mdss_dsi_phy0>;
+ phys = <&dsi_phy0>;
+ phy-names ="dsi-phy";
qcom,dual-dsi-mode;
qcom,master-dsi;
qcom,sync-dual-dsi;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&mdss_dsi_active>;
- pinctrl-1 = <&mdss_dsi_suspend>;
+ pinctrl-0 = <&dsi_active>;
+ pinctrl-1 = <&dsi_suspend>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
panel: panel@0 {
compatible = "sharp,lq101r1sx01";
@@ -152,16 +195,9 @@ Example:
};
};
};
-
- port {
- dsi0_out: endpoint {
- remote-endpoint = <&panel_in>;
- lanes = <0 1 2 3>;
- };
- };
};
- mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
+ dsi_phy0: dsi-phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
qcom,dsi-phy-index = <0>;
reg-names =
@@ -173,6 +209,7 @@ Example:
<0xfd922d80 0x7b>;
clock-names = "iface_clk";
clocks = <&mmcc MDSS_AHB_CLK>;
+ #clock-cells = <1>;
vddio-supply = <&pma8084_l12>;
qcom,dsi-phy-regulator-ldo-mode;
diff --git a/dts/Bindings/display/msm/mdp.txt b/dts/Bindings/display/msm/mdp.txt
deleted file mode 100644
index a214f6c..0000000
--- a/dts/Bindings/display/msm/mdp.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-Qualcomm adreno/snapdragon display controller
-
-Required properties:
-- compatible:
- * "qcom,mdp4" - mdp4
- * "qcom,mdp5" - mdp5
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The interrupt signal from the display controller.
-- connectors: array of phandles for output device(s)
-- clocks: device clocks
- See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required.
- For MDP4:
- * "core_clk"
- * "iface_clk"
- * "lut_clk"
- * "src_clk"
- * "hdmi_clk"
- * "mdp_clk"
- For MDP5:
- * "bus_clk"
- * "iface_clk"
- * "core_clk_src"
- * "core_clk"
- * "lut_clk" (some MDP5 versions may not need this)
- * "vsync_clk"
-
-Optional properties:
-- gpus: phandle for gpu device
-- clock-names: the following clocks are optional:
- * "lut_clk"
-
-Example:
-
-/ {
- ...
-
- mdp: qcom,mdp@5100000 {
- compatible = "qcom,mdp4";
- reg = <0x05100000 0xf0000>;
- interrupts = <GIC_SPI 75 0>;
- connectors = <&hdmi>;
- gpus = <&gpu>;
- clock-names =
- "core_clk",
- "iface_clk",
- "lut_clk",
- "src_clk",
- "hdmi_clk",
- "mdp_clk";
- clocks =
- <&mmcc MDP_SRC>,
- <&mmcc MDP_AHB_CLK>,
- <&mmcc MDP_LUT_CLK>,
- <&mmcc TV_SRC>,
- <&mmcc HDMI_TV_CLK>,
- <&mmcc MDP_TV_CLK>;
- };
-};
diff --git a/dts/Bindings/display/msm/mdp4.txt b/dts/Bindings/display/msm/mdp4.txt
new file mode 100644
index 0000000..3c341a1
--- /dev/null
+++ b/dts/Bindings/display/msm/mdp4.txt
@@ -0,0 +1,112 @@
+Qualcomm adreno/snapdragon MDP4 display controller
+
+Description:
+
+This is the bindings documentation for the MDP4 display controller found in
+SoCs like MSM8960, APQ8064 and MSM8660.
+
+Required properties:
+- compatible:
+ * "qcom,mdp4" - mdp4
+- reg: Physical base address and length of the controller's registers.
+- interrupts: The interrupt signal from the display controller.
+- clocks: device clocks
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required.
+ * "core_clk"
+ * "iface_clk"
+ * "bus_clk"
+ * "lut_clk"
+ * "hdmi_clk"
+ * "tv_clk"
+- ports: contains the list of output ports from MDP. These connect to interfaces
+ that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
+ special case since it is a part of the MDP block itself).
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ The output port mappings are:
+ Port 0 -> LCDC/LVDS
+ Port 1 -> DSI1 Cmd/Video
+ Port 2 -> DSI2 Cmd/Video
+ Port 3 -> DTV
+
+Optional properties:
+- clock-names: the following clocks are optional:
+ * "lut_clk"
+
+Example:
+
+/ {
+ ...
+
+ hdmi: hdmi@4a00000 {
+ ...
+ ports {
+ ...
+ port@0 {
+ reg = <0>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&mdp_dtv_out>;
+ };
+ };
+ ...
+ };
+ ...
+ };
+
+ ...
+
+ mdp: mdp@5100000 {
+ compatible = "qcom,mdp4";
+ reg = <0x05100000 0xf0000>;
+ interrupts = <GIC_SPI 75 0>;
+ clock-names =
+ "core_clk",
+ "iface_clk",
+ "lut_clk",
+ "hdmi_clk",
+ "tv_clk";
+ clocks =
+ <&mmcc MDP_CLK>,
+ <&mmcc MDP_AHB_CLK>,
+ <&mmcc MDP_AXI_CLK>,
+ <&mmcc MDP_LUT_CLK>,
+ <&mmcc HDMI_TV_CLK>,
+ <&mmcc MDP_TV_CLK>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp_lvds_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdp_dsi1_out: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ mdp_dsi2_out: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ mdp_dtv_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/display/msm/mdp5.txt b/dts/Bindings/display/msm/mdp5.txt
new file mode 100644
index 0000000..30c11ea
--- /dev/null
+++ b/dts/Bindings/display/msm/mdp5.txt
@@ -0,0 +1,160 @@
+Qualcomm adreno/snapdragon MDP5 display controller
+
+Description:
+
+This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
+encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
+controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
+
+MDSS:
+Required properties:
+- compatible:
+ * "qcom,mdss" - MDSS
+- reg: Physical base address and length of the controller's registers.
+- reg-names: The names of register regions. The following regions are required:
+ * "mdss_phys"
+ * "vbif_phys"
+- interrupts: The interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required.
+ * "iface_clk"
+ * "bus_clk"
+ * "vsync_clk"
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- clock-names: the following clocks are optional:
+ * "lut_clk"
+
+MDP5:
+Required properties:
+- compatible:
+ * "qcom,mdp5" - MDP5
+- reg: Physical base address and length of the controller's registers.
+- reg-names: The names of register regions. The following regions are required:
+ * "mdp_phys"
+- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
+- interrupt-parent: phandle to the MDSS block
+ through MDP block
+- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required.
+- * "bus_clk"
+- * "iface_clk"
+- * "core_clk"
+- * "vsync_clk"
+- ports: contains the list of output ports from MDP. These connect to interfaces
+ that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
+ special case since it is a part of the MDP block itself).
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ The availability of output ports can vary across SoC revisions:
+
+ For MSM8974 and APQ8084:
+ Port 0 -> MDP_INTF0 (eDP)
+ Port 1 -> MDP_INTF1 (DSI1)
+ Port 2 -> MDP_INTF2 (DSI2)
+ Port 3 -> MDP_INTF3 (HDMI)
+
+ For MSM8916:
+ Port 0 -> MDP_INTF1 (DSI1)
+
+ For MSM8994 and MSM8996:
+ Port 0 -> MDP_INTF1 (DSI1)
+ Port 1 -> MDP_INTF2 (DSI2)
+ Port 2 -> MDP_INTF3 (HDMI)
+
+Optional properties:
+- clock-names: the following clocks are optional:
+ * "lut_clk"
+
+Example:
+
+/ {
+ ...
+
+ mdss: mdss@1a00000 {
+ compatible = "qcom,mdss";
+ reg = <0x1a00000 0x1000>,
+ <0x1ac8000 0x3000>;
+ reg-names = "mdss_phys", "vbif_phys";
+
+ power-domains = <&gcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk",
+ "bus_clk",
+ "vsync_clk"
+
+ interrupts = <0 72 0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdp: mdp@1a01000 {
+ compatible = "qcom,mdp5";
+ reg = <0x1a01000 0x90000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk",
+ "bus_clk",
+ "core_clk",
+ "vsync_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@1a98000 {
+ ...
+ ports {
+ ...
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+ ...
+ };
+ ...
+ };
+
+ dsi_phy0: dsi-phy@1a98300 {
+ ...
+ };
+ };
+};
diff --git a/dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt b/dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt
new file mode 100644
index 0000000..b9877ac
--- /dev/null
+++ b/dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt
@@ -0,0 +1,7 @@
+LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "lg,lp079qx1-sp0v"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/lg,lp097qx1-spa1.txt b/dts/Bindings/display/panel/lg,lp097qx1-spa1.txt
new file mode 100644
index 0000000..4214151
--- /dev/null
+++ b/dts/Bindings/display/panel/lg,lp097qx1-spa1.txt
@@ -0,0 +1,7 @@
+LG 9.7" (2048x1536 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "lg,lp097qx1-spa1"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/panel-dpi.txt b/dts/Bindings/display/panel/panel-dpi.txt
index 216c894..b52ac52 100644
--- a/dts/Bindings/display/panel/panel-dpi.txt
+++ b/dts/Bindings/display/panel/panel-dpi.txt
@@ -7,6 +7,8 @@ Required properties:
Optional properties:
- label: a symbolic name for the panel
- enable-gpios: panel enable gpio
+- reset-gpios: GPIO to control the RESET pin
+- vcc-supply: phandle of regulator that will be used to enable power to the display
Required nodes:
- "panel-timing" containing video timings
diff --git a/dts/Bindings/display/panel/samsung,lsn122dl01-c01.txt b/dts/Bindings/display/panel/samsung,lsn122dl01-c01.txt
new file mode 100644
index 0000000..dba298b
--- /dev/null
+++ b/dts/Bindings/display/panel/samsung,lsn122dl01-c01.txt
@@ -0,0 +1,7 @@
+Samsung 12.2" (2560x1600 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "samsung,lsn122dl01-c01"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/sharp,lq101k1ly04.txt b/dts/Bindings/display/panel/sharp,lq101k1ly04.txt
new file mode 100644
index 0000000..4aff25b
--- /dev/null
+++ b/dts/Bindings/display/panel/sharp,lq101k1ly04.txt
@@ -0,0 +1,7 @@
+Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "sharp,lq101k1ly04"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/sharp,lq123p1jx31.txt b/dts/Bindings/display/panel/sharp,lq123p1jx31.txt
new file mode 100644
index 0000000..bcb0e8a
--- /dev/null
+++ b/dts/Bindings/display/panel/sharp,lq123p1jx31.txt
@@ -0,0 +1,7 @@
+Sharp 12.3" (2400x1600 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "sharp,lq123p1jx31"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/starry,kr122ea0sra.txt b/dts/Bindings/display/panel/starry,kr122ea0sra.txt
new file mode 100644
index 0000000..1e87fe6
--- /dev/null
+++ b/dts/Bindings/display/panel/starry,kr122ea0sra.txt
@@ -0,0 +1,7 @@
+Starry 12.2" (1920x1200 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "starry,kr122ea0sra"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
index e832ff9..01cced1 100644
--- a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
================================
Required properties:
-- compatible: "rockchip,rk3288-edp";
+- compatible: "rockchip,rk3288-dp",
+ "rockchip,rk3399-edp";
- reg: physical base address of the controller and length
@@ -27,6 +28,12 @@ Required properties:
Port 0: contained 2 endpoints, connecting to the output of vop.
Port 1: contained 1 endpoint, connecting to the input of panel.
+Optional property for different chips:
+- clocks: from common clock binding: handle to grf_vio clock.
+
+- clock-names: from common clock binding:
+ Required elements: "grf"
+
For the below properties, please refer to Analogix DP binding document:
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
- phys (required)
diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
index a3bd8c0..0fad7ed 100644
--- a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -208,6 +208,7 @@ of the following host1x client modules:
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- sor: clock input for the SOR hardware
+ - source: source clock for the SOR clock
- parent: input for the pixel clock
- dp: reference clock for the SOR clock
- safe: safe reference for the SOR clock during power up
@@ -226,9 +227,9 @@ of the following host1x client modules:
- nvidia,dpaux: phandle to a DispayPort AUX interface
- dpaux: DisplayPort AUX interface
- - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
- must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
- <chip> is tegra132.
+ - compatible : Should contain one of the following:
+ - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
+ - "nvidia,tegra210-dpaux": for Tegra210
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
@@ -241,6 +242,12 @@ of the following host1x client modules:
- reset-names: Must include the following entries:
- dpaux
- vdd-supply: phandle of a supply that powers the DisplayPort link
+ - i2c-bus: Subnode where I2C slave devices are listed. This subnode
+ must be always present. If there are no I2C slave devices, an empty
+ node should be added. See ../../i2c/i2c.txt for more information.
+
+ See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
+ regarding the DPAUX pad controller bindings.
Example:
diff --git a/dts/Bindings/dma/mv-xor-v2.txt b/dts/Bindings/dma/mv-xor-v2.txt
new file mode 100644
index 0000000..217a90e
--- /dev/null
+++ b/dts/Bindings/dma/mv-xor-v2.txt
@@ -0,0 +1,24 @@
+* Marvell XOR v2 engines
+
+Required properties:
+- compatible: one of the following values:
+ "marvell,armada-7k-xor"
+ "marvell,xor-v2"
+- reg: Should contain registers location and length (two sets)
+ the first set is the DMA registers
+ the second set is the global registers
+- msi-parent: Phandle to the MSI-capable interrupt controller used for
+ interrupts.
+
+Optional properties:
+- clocks: Optional reference to the clock used by the XOR engine.
+
+Example:
+
+ xor0@400000 {
+ compatible = "marvell,xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ dma-coherent;
+ };
diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt
index 079b42a..18090e7 100644
--- a/dts/Bindings/dma/ti-edma.txt
+++ b/dts/Bindings/dma/ti-edma.txt
@@ -15,7 +15,7 @@ Required properties:
- reg: Memory map of eDMA CC
- reg-names: "edma3_cc"
- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
-- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
+- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
<&tptc_phandle TC_priority_number>. The highest priority is 0.
@@ -48,7 +48,7 @@ edma: edma@49000000 {
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
- interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
+ interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
diff --git a/dts/Bindings/dma/xilinx/xilinx_dma.txt b/dts/Bindings/dma/xilinx/xilinx_dma.txt
index 3cf0072..a2b8bfa 100644
--- a/dts/Bindings/dma/xilinx/xilinx_dma.txt
+++ b/dts/Bindings/dma/xilinx/xilinx_dma.txt
@@ -1,46 +1,96 @@
+Xilinx AXI VDMA engine, it does transfers between memory and video devices.
+It can be configured to have one channel or two channels. If configured
+as two channels, one is to transmit to the video device and another is
+to receive from the video device.
+
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
target devices. It can be configured to have one channel or two channels.
If configured as two channels, one is to transmit to the device and another
is to receive from the device.
+Xilinx AXI CDMA engine, it does transfers between memory-mapped source
+address and a memory-mapped destination address.
+
Required properties:
-- compatible: Should be "xlnx,axi-dma-1.00.a"
+- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
+ "xlnx,axi-cdma-1.00.a""
- #dma-cells: Should be <1>, see "dmas" property below
-- reg: Should contain DMA registers location and length.
+- reg: Should contain VDMA registers location and length.
+- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
+- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
- dma-channel child node: Should have at least one channel and can have up to
two channels per device. This node specifies the properties of each
DMA channel (see child node properties below).
+- clocks: Input clock specifier. Refer to common clock bindings.
+- clock-names: List of input clocks
+ For VDMA:
+ Required elements: "s_axi_lite_aclk"
+ Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
+ "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
+ For CDMA:
+ Required elements: "s_axi_lite_aclk", "m_axi_aclk"
+ FOR AXIDMA:
+ Required elements: "s_axi_lite_aclk"
+ Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
+ "m_axi_sg_aclk"
+
+Required properties for VDMA:
+- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
Optional properties:
-- xlnx,include-sg: Tells whether configured for Scatter-mode in
+- xlnx,include-sg: Tells configured for Scatter-mode in
the hardware.
+Optional properties for AXI DMA:
+- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
+Optional properties for VDMA:
+- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
+ It takes following values:
+ {1}, flush both channels
+ {2}, flush mm2s channel
+ {3}, flush s2mm channel
Required child node properties:
-- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
+- compatible:
+ For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
+ "xlnx,axi-vdma-s2mm-channel".
+ For CDMA: It should be "xlnx,axi-cdma-channel".
+ For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or
"xlnx,axi-dma-s2mm-channel".
-- interrupts: Should contain per channel DMA interrupts.
+- interrupts: Should contain per channel VDMA interrupts.
- xlnx,datawidth: Should contain the stream data width, take values
{32,64...1024}.
-Option child node properties:
-- xlnx,include-dre: Tells whether hardware is configured for Data
+Optional child node properties:
+- xlnx,include-dre: Tells hardware is configured for Data
Realignment Engine.
+Optional child node properties for VDMA:
+- xlnx,genlock-mode: Tells Genlock synchronization is
+ enabled/disabled in hardware.
+Optional child node properties for AXI DMA:
+-dma-channels: Number of dma channels in child node.
Example:
++++++++
-axi_dma_0: axidma@40400000 {
- compatible = "xlnx,axi-dma-1.00.a";
+axi_vdma_0: axivdma@40030000 {
+ compatible = "xlnx,axi-vdma-1.00.a";
#dma_cells = <1>;
- reg = < 0x40400000 0x10000 >;
- dma-channel@40400000 {
- compatible = "xlnx,axi-dma-mm2s-channel";
- interrupts = < 0 59 4 >;
+ reg = < 0x40030000 0x10000 >;
+ dma-ranges = <0x00000000 0x00000000 0x40000000>;
+ xlnx,num-fstores = <0x8>;
+ xlnx,flush-fsync = <0x1>;
+ xlnx,addrwidth = <0x20>;
+ clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
+ clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
+ "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
+ dma-channel@40030000 {
+ compatible = "xlnx,axi-vdma-mm2s-channel";
+ interrupts = < 0 54 4 >;
xlnx,datawidth = <0x40>;
} ;
- dma-channel@40400030 {
- compatible = "xlnx,axi-dma-s2mm-channel";
- interrupts = < 0 58 4 >;
+ dma-channel@40030030 {
+ compatible = "xlnx,axi-vdma-s2mm-channel";
+ interrupts = < 0 53 4 >;
xlnx,datawidth = <0x40>;
} ;
} ;
@@ -49,7 +99,7 @@ axi_dma_0: axidma@40400000 {
* DMA client
Required properties:
-- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
+- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
where Channel ID is '0' for write/tx and '1' for read/rx
channel.
- dma-names: a list of DMA channel names, one per "dmas" entry
@@ -57,9 +107,9 @@ Required properties:
Example:
++++++++
-dmatest_0: dmatest@0 {
- compatible ="xlnx,axi-dma-test-1.00.a";
- dmas = <&axi_dma_0 0
- &axi_dma_0 1>;
- dma-names = "dma0", "dma1";
+vdmatest_0: vdmatest@0 {
+ compatible ="xlnx,axi-vdma-test-1.00.a";
+ dmas = <&axi_vdma_0 0
+ &axi_vdma_0 1>;
+ dma-names = "vdma0", "vdma1";
} ;
diff --git a/dts/Bindings/dma/xilinx/xilinx_vdma.txt b/dts/Bindings/dma/xilinx/xilinx_vdma.txt
deleted file mode 100644
index a1f2683..0000000
--- a/dts/Bindings/dma/xilinx/xilinx_vdma.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-Xilinx AXI VDMA engine, it does transfers between memory and video devices.
-It can be configured to have one channel or two channels. If configured
-as two channels, one is to transmit to the video device and another is
-to receive from the video device.
-
-Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
-target devices. It can be configured to have one channel or two channels.
-If configured as two channels, one is to transmit to the device and another
-is to receive from the device.
-
-Xilinx AXI CDMA engine, it does transfers between memory-mapped source
-address and a memory-mapped destination address.
-
-Required properties:
-- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
- "xlnx,axi-cdma-1.00.a""
-- #dma-cells: Should be <1>, see "dmas" property below
-- reg: Should contain VDMA registers location and length.
-- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
-- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
-- dma-channel child node: Should have at least one channel and can have up to
- two channels per device. This node specifies the properties of each
- DMA channel (see child node properties below).
-- clocks: Input clock specifier. Refer to common clock bindings.
-- clock-names: List of input clocks
- For VDMA:
- Required elements: "s_axi_lite_aclk"
- Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
- "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
- For CDMA:
- Required elements: "s_axi_lite_aclk", "m_axi_aclk"
- FOR AXIDMA:
- Required elements: "s_axi_lite_aclk"
- Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
- "m_axi_sg_aclk"
-
-Required properties for VDMA:
-- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
-
-Optional properties:
-- xlnx,include-sg: Tells configured for Scatter-mode in
- the hardware.
-Optional properties for VDMA:
-- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
- It takes following values:
- {1}, flush both channels
- {2}, flush mm2s channel
- {3}, flush s2mm channel
-
-Required child node properties:
-- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
- "xlnx,axi-vdma-s2mm-channel".
-- interrupts: Should contain per channel VDMA interrupts.
-- xlnx,datawidth: Should contain the stream data width, take values
- {32,64...1024}.
-
-Optional child node properties:
-- xlnx,include-dre: Tells hardware is configured for Data
- Realignment Engine.
-Optional child node properties for VDMA:
-- xlnx,genlock-mode: Tells Genlock synchronization is
- enabled/disabled in hardware.
-
-Example:
-++++++++
-
-axi_vdma_0: axivdma@40030000 {
- compatible = "xlnx,axi-vdma-1.00.a";
- #dma_cells = <1>;
- reg = < 0x40030000 0x10000 >;
- dma-ranges = <0x00000000 0x00000000 0x40000000>;
- xlnx,num-fstores = <0x8>;
- xlnx,flush-fsync = <0x1>;
- xlnx,addrwidth = <0x20>;
- clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
- clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
- "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
- dma-channel@40030000 {
- compatible = "xlnx,axi-vdma-mm2s-channel";
- interrupts = < 0 54 4 >;
- xlnx,datawidth = <0x40>;
- } ;
- dma-channel@40030030 {
- compatible = "xlnx,axi-vdma-s2mm-channel";
- interrupts = < 0 53 4 >;
- xlnx,datawidth = <0x40>;
- } ;
-} ;
-
-
-* DMA client
-
-Required properties:
-- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
- where Channel ID is '0' for write/tx and '1' for read/rx
- channel.
-- dma-names: a list of DMA channel names, one per "dmas" entry
-
-Example:
-++++++++
-
-vdmatest_0: vdmatest@0 {
- compatible ="xlnx,axi-vdma-test-1.00.a";
- dmas = <&axi_vdma_0 0
- &axi_vdma_0 1>;
- dma-names = "vdma0", "vdma1";
-} ;
diff --git a/dts/Bindings/dma/xilinx/zynqmp_dma.txt b/dts/Bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 0000000..a784cdd
--- /dev/null
+++ b/dts/Bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,27 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible : Should be "xlnx,zynqmp-dma-1.0"
+- reg : Memory map for gdma/adma module access.
+- interrupt-parent : Interrupt controller the interrupt is routed through
+- interrupts : Should contain DMA channel interrupt.
+- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
+- clock-names : List of input clocks "clk_main", "clk_apb"
+ (see clock bindings for details)
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent.
+
+Example:
+++++++++
+fpd_dma_chan1: dma@fd500000 {
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xFD500000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 117 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ dma-coherent;
+};
diff --git a/dts/Bindings/extcon/extcon-arizona.txt b/dts/Bindings/extcon/extcon-arizona.txt
index e27341f..7f3d94a 100644
--- a/dts/Bindings/extcon/extcon-arizona.txt
+++ b/dts/Bindings/extcon/extcon-arizona.txt
@@ -46,7 +46,8 @@ Optional properties:
The second cell represents the MICBIAS to be used.
The third cell represents the value of the micd-pol-gpio pin.
- - wlf,gpsw : Settings for the general purpose switch
+ - wlf,gpsw : Settings for the general purpose switch, set as one of the
+ ARIZONA_GPSW_XXX defines.
Example:
diff --git a/dts/Bindings/firmware/qcom,scm.txt b/dts/Bindings/firmware/qcom,scm.txt
new file mode 100644
index 0000000..3b4436e
--- /dev/null
+++ b/dts/Bindings/firmware/qcom,scm.txt
@@ -0,0 +1,28 @@
+QCOM Secure Channel Manager (SCM)
+
+Qualcomm processors include an interface to communicate to the secure firmware.
+This interface allows for clients to request different types of actions. These
+can include CPU power up/down, HDCP requests, loading of firmware, and other
+assorted actions.
+
+Required properties:
+- compatible: must contain one of the following:
+ * "qcom,scm-apq8064" for APQ8064 platforms
+ * "qcom,scm-msm8660" for MSM8660 platforms
+ * "qcom,scm-msm8690" for MSM8690 platforms
+ * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
+- clocks: One to three clocks may be required based on compatible.
+ * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
+ * Core, iface, and bus clocks required for "qcom,scm"
+- clock-names: Must contain "core" for the core clock, "iface" for the interface
+ clock and "bus" for the bus clock per the requirements of the compatible.
+
+Example for MSM8916:
+
+ firmware {
+ scm {
+ compatible = "qcom,scm";
+ clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
+ clock-names = "core", "bus", "iface";
+ };
+ };
diff --git a/dts/Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt b/dts/Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
index 94ae9f8..fd42e72 100644
--- a/dts/Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
+++ b/dts/Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
@@ -1,7 +1,7 @@
* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
Required properties:
-- compatible: Should contain "cirrus,clps711x-mctrl-gpio".
+- compatible: Should contain "cirrus,ep7209-mctrl-gpio".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
@@ -11,7 +11,7 @@ Required properties:
Example:
sysgpio: sysgpio {
compatible = "cirrus,ep7312-mctrl-gpio",
- "cirrus,clps711x-mctrl-gpio";
+ "cirrus,ep7209-mctrl-gpio";
gpio-controller;
#gpio-cells = <2>;
};
diff --git a/dts/Bindings/gpio/gpio-clps711x.txt b/dts/Bindings/gpio/gpio-clps711x.txt
index e0d0446..0a304ad 100644
--- a/dts/Bindings/gpio/gpio-clps711x.txt
+++ b/dts/Bindings/gpio/gpio-clps711x.txt
@@ -1,7 +1,7 @@
Cirrus Logic CLPS711X GPIO controller
Required properties:
-- compatible: Should be "cirrus,clps711x-gpio"
+- compatible: Should be "cirrus,ep7209-gpio"
- reg: Physical base GPIO controller registers location and length.
There should be two registers, first is DATA register, the second
is DIRECTION.
@@ -21,7 +21,7 @@ aliases {
};
porta: gpio@80000000 {
- compatible = "cirrus,clps711x-gpio";
+ compatible = "cirrus,ep7312-gpio","cirrus,ep7209-gpio";
reg = <0x80000000 0x1>, <0x80000040 0x1>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/dts/Bindings/gpio/gpio-max77620.txt b/dts/Bindings/gpio/gpio-max77620.txt
new file mode 100644
index 0000000..410e716
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-max77620.txt
@@ -0,0 +1,25 @@
+GPIO driver for MAX77620 Power management IC from Maxim Semiconductor.
+
+Device has 8 GPIO pins which can be configured as GPIO as well as the
+special IO functions.
+
+Required properties:
+-------------------
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+For more details, please refer generic GPIO DT binding document
+<devicetree/bindings/gpio/gpio.txt>.
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+};
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
index 6b4a98f..08dd15f 100644
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -21,6 +21,7 @@ Required properties:
maxim,max7313
maxim,max7315
ti,pca6107
+ ti,pca9536
ti,tca6408
ti,tca6416
ti,tca6424
diff --git a/dts/Bindings/gpio/gpio_oxnas.txt b/dts/Bindings/gpio/gpio_oxnas.txt
new file mode 100644
index 0000000..928ed4f
--- /dev/null
+++ b/dts/Bindings/gpio/gpio_oxnas.txt
@@ -0,0 +1,47 @@
+* Oxford Semiconductor OXNAS SoC GPIO Controller
+
+Please refer to gpio.txt for generic information regarding GPIO bindings.
+
+Required properties:
+ - compatible: "oxsemi,ox810se-gpio"
+ - reg: Base address and length for the device.
+ - interrupts: The port interrupt shared by all pins.
+ - gpio-controller: Marks the port as GPIO controller.
+ - #gpio-cells: Two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity as defined in
+ defined in <dt-bindings/gpio/gpio.h>:
+ 0 = GPIO_ACTIVE_HIGH
+ 1 = GPIO_ACTIVE_LOW
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells: Two. The first cell is the GPIO number and second cell
+ is used to specify the trigger type as defined in
+ <dt-bindings/interrupt-controller/irq.h>:
+ IRQ_TYPE_EDGE_RISING
+ IRQ_TYPE_EDGE_FALLING
+ IRQ_TYPE_EDGE_BOTH
+ - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
+ gpio base and count, should be in the format of numeric-gpio-range as
+ specified in the gpio.txt file.
+
+Example:
+
+gpio0: gpio@0 {
+ compatible = "oxsemi,ox810se-gpio";
+ reg = <0x000000 0x100000>;
+ interrupts = <21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+};
+
+keys {
+ ...
+
+ button-esc {
+ label = "ESC";
+ linux,code = <1>;
+ gpios = <&gpio0 12 0>;
+ };
+};
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index f60e2f4..8da26b3 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -7,6 +7,7 @@ Required Properties:
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
- "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
+ - "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller.
- "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller.
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
diff --git a/dts/Bindings/hwmon/apm-xgene-hwmon.txt b/dts/Bindings/hwmon/apm-xgene-hwmon.txt
new file mode 100644
index 0000000..59b3855
--- /dev/null
+++ b/dts/Bindings/hwmon/apm-xgene-hwmon.txt
@@ -0,0 +1,14 @@
+APM X-Gene hwmon driver
+
+APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox.
+
+Required properties :
+ - compatible : should be "apm,xgene-slimpro-hwmon"
+ - mboxes : use the label reference for the mailbox as the first parameter.
+ The second parameter is the channel number.
+
+Example :
+ hwmonslimpro {
+ compatible = "apm,xgene-slimpro-hwmon";
+ mboxes = <&mailbox 7>;
+ };
diff --git a/dts/Bindings/hwmon/jc42.txt b/dts/Bindings/hwmon/jc42.txt
new file mode 100644
index 0000000..07a2504
--- /dev/null
+++ b/dts/Bindings/hwmon/jc42.txt
@@ -0,0 +1,42 @@
+Properties for Jedec JC-42.4 compatible temperature sensors
+
+Required properties:
+- compatible: May include a device-specific string consisting of the
+ manufacturer and the name of the chip. A list of supported
+ chip names follows.
+ Must include "jedec,jc-42.4-temp" for any Jedec JC-42.4
+ compatible temperature sensor.
+
+ Supported chip names:
+ adi,adt7408
+ atmel,at30ts00
+ atmel,at30tse004
+ onnn,cat6095
+ onnn,cat34ts02
+ maxim,max6604
+ microchip,mcp9804
+ microchip,mcp9805
+ microchip,mcp9808
+ microchip,mcp98243
+ microchip,mcp98244
+ microchip,mcp9843
+ nxp,se97
+ nxp,se98
+ st,stts2002
+ st,stts2004
+ st,stts3000
+ st,stts424
+ st,stts424e
+ idt,tse2002
+ idt,tse2004
+ idt,ts3000
+ idt,ts3001
+
+- reg: I2C address
+
+Example:
+
+temp-sensor@1a {
+ compatible = "jedec,jc-42.4-temp";
+ reg = <0x1a>;
+};
diff --git a/dts/Bindings/i2c/i2c-rk3x.txt b/dts/Bindings/i2c/i2c-rk3x.txt
index 0b4a85f..bbc5a1e 100644
--- a/dts/Bindings/i2c/i2c-rk3x.txt
+++ b/dts/Bindings/i2c/i2c-rk3x.txt
@@ -6,10 +6,20 @@ RK3xxx SoCs.
Required properties :
- reg : Offset and length of the register set for the device
- - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
- "rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
+ - compatible: should be one of the following:
+ - "rockchip,rk3066-i2c": for rk3066
+ - "rockchip,rk3188-i2c": for rk3188
+ - "rockchip,rk3228-i2c": for rk3228
+ - "rockchip,rk3288-i2c": for rk3288
+ - "rockchip,rk3399-i2c": for rk3399
- interrupts : interrupt number
- - clocks : parent clock
+ - clocks: See ../clock/clock-bindings.txt
+ - For older hardware (rk3066, rk3188, rk3228, rk3288):
+ - There is one clock that's used both to derive the functional clock
+ for the device and as the bus clock.
+ - For newer hardware (rk3399): specified by name
+ - "i2c": This is used to derive the functional clock.
+ - "pclk": This is the bus clock.
Required on RK3066, RK3188 :
diff --git a/dts/Bindings/i2c/i2c.txt b/dts/Bindings/i2c/i2c.txt
index c8d977e..f31b2ad 100644
--- a/dts/Bindings/i2c/i2c.txt
+++ b/dts/Bindings/i2c/i2c.txt
@@ -62,6 +62,13 @@ wants to support one of the below features, it should adapt the bindings below.
- wakeup-source
device can be used as a wakeup source.
+- reg
+ I2C slave addresses
+
+- reg-names
+ Names of map programmable addresses.
+ It can contain any map needing another address than default one.
+
Binding may contain optional "interrupts" property, describing interrupts
used by the device. I2C core will assign "irq" interrupt (or the very first
interrupt if not using interrupt names) as primary interrupt for the slave.
diff --git a/dts/Bindings/i2c/trivial-devices.txt b/dts/Bindings/i2c/trivial-devices.txt
index 5398744..5c70ce9 100644
--- a/dts/Bindings/i2c/trivial-devices.txt
+++ b/dts/Bindings/i2c/trivial-devices.txt
@@ -56,12 +56,77 @@ maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
mc,rv3029c2 Real Time Clock Module with I2C-Bus
+microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
+microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
+microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
+microchip,mcp4531-104 Microchip 7-bit Single I2C Digital Potentiometer (100k)
+microchip,mcp4532-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
+microchip,mcp4532-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
+microchip,mcp4532-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
+microchip,mcp4532-104 Microchip 7-bit Single I2C Digital Potentiometer (100k)
+microchip,mcp4541-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4541-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4541-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4541-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4542-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4542-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4542-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4542-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4551-502 Microchip 8-bit Single I2C Digital Potentiometer (5k)
+microchip,mcp4551-103 Microchip 8-bit Single I2C Digital Potentiometer (10k)
+microchip,mcp4551-503 Microchip 8-bit Single I2C Digital Potentiometer (50k)
+microchip,mcp4551-104 Microchip 8-bit Single I2C Digital Potentiometer (100k)
+microchip,mcp4552-502 Microchip 8-bit Single I2C Digital Potentiometer (5k)
+microchip,mcp4552-103 Microchip 8-bit Single I2C Digital Potentiometer (10k)
+microchip,mcp4552-503 Microchip 8-bit Single I2C Digital Potentiometer (50k)
+microchip,mcp4552-104 Microchip 8-bit Single I2C Digital Potentiometer (100k)
+microchip,mcp4561-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4561-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4561-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4561-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4562-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4562-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4562-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4562-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4631-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k)
+microchip,mcp4631-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k)
+microchip,mcp4631-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k)
+microchip,mcp4631-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k)
+microchip,mcp4632-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k)
+microchip,mcp4632-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k)
+microchip,mcp4632-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k)
+microchip,mcp4632-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k)
+microchip,mcp4641-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4641-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4641-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4641-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4642-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4642-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4642-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4642-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4651-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k)
+microchip,mcp4651-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k)
+microchip,mcp4651-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k)
+microchip,mcp4651-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k)
+microchip,mcp4652-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k)
+microchip,mcp4652-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k)
+microchip,mcp4652-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k)
+microchip,mcp4652-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k)
+microchip,mcp4661-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4661-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4661-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4661-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
national,lm63 Temperature sensor with integrated fan control
national,lm75 I2C TEMP SENSOR
national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
national,lm85 Temperature sensor with integrated fan control
national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
nuvoton,npct501 i2c trusted platform module (TPM)
+nuvoton,npct601 i2c trusted platform module (TPM2)
nxp,pca9556 Octal SMBus and I2C registered interface
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
nxp,pcf8563 Real-time clock/calendar
@@ -81,10 +146,10 @@ samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
sgx,vz89x SGX Sensortech VZ89X Sensors
sii,s35390a 2-wire CMOS real-time clock
skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
-st-micro,24c256 i2c serial eeprom (24cxx)
-stm,m41t00 Serial Access TIMEKEEPER
-stm,m41t62 Serial real-time clock (RTC) with alarm
-stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
+st,24c256 i2c serial eeprom (24cxx)
+st,m41t00 Serial real-time clock (RTC)
+st,m41t62 Serial real-time clock (RTC) with alarm
+st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
ti,ads7828 8-Channels, 12-bit ADC
ti,ads7830 8-Channels, 8-bit ADC
diff --git a/dts/Bindings/iio/adc/at91_adc.txt b/dts/Bindings/iio/adc/at91_adc.txt
index 0f813de..f65b04f 100644
--- a/dts/Bindings/iio/adc/at91_adc.txt
+++ b/dts/Bindings/iio/adc/at91_adc.txt
@@ -59,28 +59,24 @@ adc0: adc@fffb0000 {
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "lowres";
- trigger@0 {
- reg = <0>;
+ trigger0 {
trigger-name = "external-rising";
trigger-value = <0x1>;
trigger-external;
};
- trigger@1 {
- reg = <1>;
+ trigger1 {
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
};
- trigger@2 {
- reg = <2>;
+ trigger2 {
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
};
- trigger@3 {
- reg = <3>;
+ trigger3 {
trigger-name = "continuous";
trigger-value = <0x6>;
};
diff --git a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
new file mode 100644
index 0000000..caaaed7
--- /dev/null
+++ b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
@@ -0,0 +1,41 @@
+* Broadcom's IPROC Static ADC controller
+
+Broadcom iProc ADC controller has 8 channels 10bit ADC.
+Allows user to convert analog input voltage values to digital.
+
+Required properties:
+
+- compatible: Must be "brcm,iproc-static-adc"
+
+- adc-syscon: Handler of syscon node defining physical base address of the
+ controller and length of memory mapped region.
+
+- #io-channel-cells = <1>; As ADC has multiple outputs
+ refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
+
+- io-channel-ranges:
+ refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
+
+- clocks: Clock used for this block.
+
+- clock-names: Clock name should be given as tsc_clk.
+
+- interrupts: interrupt line number.
+
+For example:
+
+ ts_adc_syscon: ts_adc_syscon@180a6000 {
+ compatible = "brcm,iproc-ts-adc-syscon","syscon";
+ reg = <0x180a6000 0xc30>;
+ };
+
+ adc: adc@180a6000 {
+ compatible = "brcm,iproc-static-adc";
+ adc-syscon = <&ts_adc_syscon>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+ clock-names = "tsc_clk";
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/iio/adc/max1363.txt b/dts/Bindings/iio/adc/max1363.txt
new file mode 100644
index 0000000..94a9011
--- /dev/null
+++ b/dts/Bindings/iio/adc/max1363.txt
@@ -0,0 +1,63 @@
+* Maxim 1x3x/136x/116xx Analog to Digital Converter (ADC)
+
+The node for this driver must be a child node of a I2C controller, hence
+all mandatory properties for your controller must be specified. See directory:
+
+ Documentation/devicetree/bindings/i2c
+
+for more details.
+
+Required properties:
+ - compatible: Should be one of
+ "maxim,max1361"
+ "maxim,max1362"
+ "maxim,max1363"
+ "maxim,max1364"
+ "maxim,max1036"
+ "maxim,max1037"
+ "maxim,max1038"
+ "maxim,max1039"
+ "maxim,max1136"
+ "maxim,max1137"
+ "maxim,max1138"
+ "maxim,max1139"
+ "maxim,max1236"
+ "maxim,max1237"
+ "maxim,max1238"
+ "maxim,max1239"
+ "maxim,max11600"
+ "maxim,max11601"
+ "maxim,max11602"
+ "maxim,max11603"
+ "maxim,max11604"
+ "maxim,max11605"
+ "maxim,max11606"
+ "maxim,max11607"
+ "maxim,max11608"
+ "maxim,max11609"
+ "maxim,max11610"
+ "maxim,max11611"
+ "maxim,max11612"
+ "maxim,max11613"
+ "maxim,max11614"
+ "maxim,max11615"
+ "maxim,max11616"
+ "maxim,max11617"
+ "maxim,max11644"
+ "maxim,max11645"
+ "maxim,max11646"
+ "maxim,max11647"
+ - reg: Should contain the ADC I2C address
+
+Optional properties:
+ - vcc-supply: phandle to the regulator that provides power to the ADC.
+ - vref-supply: phandle to the regulator for ADC reference voltage.
+ - interrupts: IRQ line for the ADC. If not used the driver will use
+ polling.
+
+Example:
+adc: max11644@36 {
+ compatible = "maxim,max11644";
+ reg = <0x36>;
+ vref-supply = <&adc_vref>;
+};
diff --git a/dts/Bindings/iio/chemical/atlas,ec-sm.txt b/dts/Bindings/iio/chemical/atlas,ec-sm.txt
new file mode 100644
index 0000000..2962bd9
--- /dev/null
+++ b/dts/Bindings/iio/chemical/atlas,ec-sm.txt
@@ -0,0 +1,22 @@
+* Atlas Scientific EC-SM OEM sensor
+
+http://www.atlas-scientific.com/_files/_datasheets/_oem/EC_oem_datasheet.pdf
+
+Required properties:
+
+ - compatible: must be "atlas,ec-sm"
+ - reg: the I2C address of the sensor
+ - interrupt-parent: should be the phandle for the interrupt controller
+ - interrupts: the sole interrupt generated by the device
+
+ Refer to interrupt-controller/interrupts.txt for generic interrupt client
+ node bindings.
+
+Example:
+
+atlas@64 {
+ compatible = "atlas,ec-sm";
+ reg = <0x64>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 2>;
+};
diff --git a/dts/Bindings/iio/dac/ad5755.txt b/dts/Bindings/iio/dac/ad5755.txt
new file mode 100644
index 0000000..f0bbd7e
--- /dev/null
+++ b/dts/Bindings/iio/dac/ad5755.txt
@@ -0,0 +1,124 @@
+* Analog Device AD5755 IIO Multi-Channel DAC Linux Driver
+
+Required properties:
+ - compatible: Has to contain one of the following:
+ adi,ad5755
+ adi,ad5755-1
+ adi,ad5757
+ adi,ad5735
+ adi,ad5737
+
+ - reg: spi chip select number for the device
+ - spi-cpha or spi-cpol: is the only modes that is supported
+
+Recommended properties:
+ - spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+See include/dt-bindings/iio/ad5755.h
+ - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
+ external resistor and thereby bypasses
+ the internal compensation resistor.
+ - adi,dc-dc-phase:
+ Valid values for DC DC Phase control is:
+ 0: All dc-to-dc converters clock on the same edge.
+ 1: Channel A and Channel B clock on the same edge,
+ Channel C and Channel D clock on opposite edges.
+ 2: Channel A and Channel C clock on the same edge,
+ Channel B and Channel D clock on opposite edges.
+ 3: Channel A, Channel B, Channel C, and Channel D
+ clock 90 degrees out of phase from each other.
+ - adi,dc-dc-freq-hz:
+ Valid values for DC DC frequency is [Hz]:
+ 250000
+ 410000
+ 650000
+ - adi,dc-dc-max-microvolt:
+ Valid values for the maximum allowed Vboost voltage supplied by
+ the dc-to-dc converter is:
+ 23000000
+ 24500000
+ 27000000
+ 29500000
+
+Optional for every channel:
+ - adi,mode:
+ Valid values for DAC modes is:
+ 0: 0 V to 5 V voltage range.
+ 1: 0 V to 10 V voltage range.
+ 2: Plus minus 5 V voltage range.
+ 3: Plus minus 10 V voltage range.
+ 4: 4 mA to 20 mA current range.
+ 5: 0 mA to 20 mA current range.
+ 6: 0 mA to 24 mA current range.
+ - adi,ext-current-sense-resistor: boolean set if the hardware a external
+ current sense resistor.
+ - adi,enable-voltage-overrange: boolean enable voltage overrange
+ - adi,slew: Array of slewrate settings should contain 3 fields:
+ 1: Should be either 0 or 1 in order to enable or disable slewrate.
+ 2: Slew rate settings:
+ Valid values for the slew rate update frequency:
+ 64000
+ 32000
+ 16000
+ 8000
+ 4000
+ 2000
+ 1000
+ 500
+ 250
+ 125
+ 64
+ 32
+ 16
+ 8
+ 4
+ 0
+ 3: Slew step size:
+ Valid values for the step size LSBs:
+ 1
+ 2
+ 4
+ 16
+ 32
+ 64
+ 128
+ 256
+
+Example:
+dac@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "adi,ad5755";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ adi,dc-dc-phase = <0>;
+ adi,dc-dc-freq-hz = <410000>;
+ adi,dc-dc-max-microvolt = <23000000>;
+ channel@0 {
+ reg = <0>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ channel@1 {
+ reg = <1>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ channel@2 {
+ reg = <2>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ channel@3 {
+ reg = <3>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+};
diff --git a/dts/Bindings/iio/pressure/bmp085.txt b/dts/Bindings/iio/pressure/bmp085.txt
index d7a6deb..c7198a0 100644
--- a/dts/Bindings/iio/pressure/bmp085.txt
+++ b/dts/Bindings/iio/pressure/bmp085.txt
@@ -1,7 +1,11 @@
-BMP085/BMP18x digital pressure sensors
+BMP085/BMP18x/BMP28x digital pressure sensors
Required properties:
-- compatible: bosch,bmp085
+- compatible: must be one of:
+ "bosch,bmp085"
+ "bosch,bmp180"
+ "bosch,bmp280"
+ "bosch,bme280"
Optional properties:
- chip-id: configurable chip id for non-default chip revisions
@@ -10,6 +14,10 @@ Optional properties:
value range is 0-3 with rising sensitivity.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ
+- reset-gpios: a GPIO line handling reset of the sensor: as the line is
+ active low, it should be marked GPIO_ACTIVE_LOW (see gpio/gpio.txt)
+- vddd-supply: digital voltage regulator (see regulator/regulator.txt)
+- vdda-supply: analog voltage regulator (see regulator/regulator.txt)
Example:
@@ -21,4 +29,7 @@ pressure@77 {
default-oversampling = <2>;
interrupt-parent = <&gpio0>;
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ vddd-supply = <&foo>;
+ vdda-supply = <&bar>;
};
diff --git a/dts/Bindings/iio/st-sensors.txt b/dts/Bindings/iio/st-sensors.txt
index 5844cf7..e41fe34 100644
--- a/dts/Bindings/iio/st-sensors.txt
+++ b/dts/Bindings/iio/st-sensors.txt
@@ -64,3 +64,4 @@ Pressure sensors:
- st,lps001wp-press
- st,lps25h-press
- st,lps331ap-press
+- st,lps22hb-press
diff --git a/dts/Bindings/input/atmel,captouch.txt b/dts/Bindings/input/atmel,captouch.txt
new file mode 100644
index 0000000..fe9ee5c
--- /dev/null
+++ b/dts/Bindings/input/atmel,captouch.txt
@@ -0,0 +1,36 @@
+Device tree bindings for Atmel capacitive touch device, typically
+an Atmel touch sensor connected to AtmegaXX MCU running firmware
+based on Qtouch library.
+
+The node for this device must be a child of a I2C controller node, as the
+device communicates via I2C.
+
+Required properties:
+
+ compatible: Must be "atmel,captouch".
+ reg: The I2C slave address of the device.
+ interrupts: Property describing the interrupt line the device
+ is connected to. The device only has one interrupt
+ source.
+ linux,keycodes: Specifies an array of numeric keycode values to
+ be used for reporting button presses. The array can
+ contain up to 8 entries.
+
+Optional properties:
+
+ autorepeat: Enables the Linux input system's autorepeat
+ feature on the input device.
+
+Example:
+
+ atmel-captouch@51 {
+ compatible = "atmel,captouch";
+ reg = <0x51>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
+ linux,keycodes = <BTN_0>, <BTN_1>,
+ <BTN_2>, <BTN_3>,
+ <BTN_4>, <BTN_5>,
+ <BTN_6>, <BTN_7>;
+ autorepeat;
+ };
diff --git a/dts/Bindings/input/clps711x-keypad.txt b/dts/Bindings/input/clps711x-keypad.txt
index e68d2bb..3eed881 100644
--- a/dts/Bindings/input/clps711x-keypad.txt
+++ b/dts/Bindings/input/clps711x-keypad.txt
@@ -1,7 +1,7 @@
* Cirrus Logic CLPS711X matrix keypad device tree bindings
Required Properties:
-- compatible: Shall contain "cirrus,clps711x-keypad".
+- compatible: Shall contain "cirrus,ep7209-keypad".
- row-gpios: List of GPIOs used as row lines.
- poll-interval: Poll interval time in milliseconds.
- linux,keymap: The definition can be found at
@@ -12,7 +12,7 @@ Optional Properties:
Example:
keypad {
- compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad";
+ compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad";
autorepeat;
poll-interval = <120>;
row-gpios = <&porta 0 0>,
diff --git a/dts/Bindings/input/raydium_i2c_ts.txt b/dts/Bindings/input/raydium_i2c_ts.txt
new file mode 100644
index 0000000..5b6232d
--- /dev/null
+++ b/dts/Bindings/input/raydium_i2c_ts.txt
@@ -0,0 +1,20 @@
+Raydium I2C touchscreen
+
+Required properties:
+- compatible: must be "raydium,rm32380"
+- reg: The I2C address of the device
+- interrupt-parent: the phandle for the interrupt controller
+- interrupts: interrupt to which the chip is connected
+ See ../interrupt-controller/interrupts.txt
+Optional properties:
+- avdd-supply: analog power supply needed to power device
+- vccio-supply: IO Power source
+- reset-gpios: reset gpio the chip is connected to.
+
+Example:
+ touchscreen@39 {
+ compatible = "raydium,rm32380";
+ reg = <0x39>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>;
+ };
diff --git a/dts/Bindings/input/rmi4/rmi_i2c.txt b/dts/Bindings/input/rmi4/rmi_i2c.txt
index 95fa715..ec908b9 100644
--- a/dts/Bindings/input/rmi4/rmi_i2c.txt
+++ b/dts/Bindings/input/rmi4/rmi_i2c.txt
@@ -22,6 +22,15 @@ See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- syna,reset-delay-ms: The number of milliseconds to wait after resetting the
device.
+- syna,startup-delay-ms: The number of milliseconds to wait after powering on
+ the device.
+
+- vdd-supply: VDD power supply.
+See ../regulator/regulator.txt
+
+- vio-supply: VIO power supply
+See ../regulator/regulator.txt
+
Function Parameters:
Parameters specific to RMI functions are contained in child nodes of the rmi device
node. Documentation for the parameters of each function can be found in:
diff --git a/dts/Bindings/input/rotary-encoder.txt b/dts/Bindings/input/rotary-encoder.txt
index 6c9f0c8..e85ce3d 100644
--- a/dts/Bindings/input/rotary-encoder.txt
+++ b/dts/Bindings/input/rotary-encoder.txt
@@ -20,6 +20,8 @@ Optional properties:
2: Half-period mode
4: Quarter-period mode
- wakeup-source: Boolean, rotary encoder can wake up the system.
+- rotary-encoder,encoding: String, the method used to encode steps.
+ Supported are "gray" (the default and more common) and "binary".
Deprecated properties:
- rotary-encoder,half-period: Makes the driver work on half-period mode.
@@ -34,6 +36,7 @@ Example:
compatible = "rotary-encoder";
gpios = <&gpio 19 1>, <&gpio 20 0>; /* GPIO19 is inverted */
linux,axis = <0>; /* REL_X */
+ rotary-encoder,encoding = "gray";
rotary-encoder,relative-axis;
};
@@ -42,5 +45,6 @@ Example:
gpios = <&gpio 21 0>, <&gpio 22 0>;
linux,axis = <1>; /* ABS_Y */
rotary-encoder,steps = <24>;
+ rotary-encoder,encoding = "binary";
rotary-encoder,rollover;
};
diff --git a/dts/Bindings/input/touchscreen/silead_gsl1680.txt b/dts/Bindings/input/touchscreen/silead_gsl1680.txt
new file mode 100644
index 0000000..1112e0d
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/silead_gsl1680.txt
@@ -0,0 +1,36 @@
+* GSL 1680 touchscreen controller
+
+Required properties:
+- compatible : "silead,gsl1680"
+- reg : I2C slave address of the chip (0x40)
+- interrupt-parent : a phandle pointing to the interrupt controller
+ serving the interrupt for this chip
+- interrupts : interrupt specification for the gsl1680 interrupt
+- power-gpios : Specification for the pin connected to the gsl1680's
+ shutdown input. This needs to be driven high to take the
+ gsl1680 out of its low power state
+- touchscreen-size-x : See touchscreen.txt
+- touchscreen-size-y : See touchscreen.txt
+
+Optional properties:
+- touchscreen-inverted-x : See touchscreen.txt
+- touchscreen-inverted-y : See touchscreen.txt
+- touchscreen-swapped-x-y : See touchscreen.txt
+- silead,max-fingers : maximum number of fingers the touchscreen can detect
+
+Example:
+
+i2c@00000000 {
+ gsl1680: touchscreen@40 {
+ compatible = "silead,gsl1680";
+ reg = <0x40>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>;
+ power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ silead,max-fingers = <5>;
+ };
+};
diff --git a/dts/Bindings/input/touchscreen/sis_i2c.txt b/dts/Bindings/input/touchscreen/sis_i2c.txt
new file mode 100644
index 0000000..d87ad14
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/sis_i2c.txt
@@ -0,0 +1,33 @@
+* SiS I2C Multiple Touch Controller
+
+Required properties:
+- compatible: must be "sis,9200-ts"
+- reg: i2c slave address
+- interrupt-parent: the phandle for the interrupt controller
+ (see interrupt binding [0])
+- interrupts: touch controller interrupt (see interrupt
+ binding [0])
+
+Optional properties:
+- pinctrl-names: should be "default" (see pinctrl binding [1]).
+- pinctrl-0: a phandle pointing to the pin settings for the
+ device (see pinctrl binding [1]).
+- attn-gpios: the gpio pin used as attention line
+- reset-gpios: the gpio pin used to reset the controller
+- wakeup-source: touchscreen can be used as a wakeup source
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+Example:
+
+ sis9255@5c {
+ compatible = "sis,9200-ts";
+ reg = <0x5c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sis>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+ irq-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/interrupt-controller/arm,gic.txt b/dts/Bindings/interrupt-controller/arm,gic.txt
index 793c20f..5393e2a 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.txt
+++ b/dts/Bindings/interrupt-controller/arm,gic.txt
@@ -21,6 +21,7 @@ Main node required properties:
"arm,pl390"
"arm,tc11mp-gic"
"brcm,brahma-b15-gic"
+ "nvidia,tegra210-agic"
"qcom,msm-8660-qgic"
"qcom,msm-qgic2"
- interrupt-controller : Identifies the node as an interrupt controller
@@ -68,7 +69,7 @@ Optional
"ic_clk" (for "arm,arm11mp-gic")
"PERIPHCLKEN" (for "arm,cortex-a15-gic")
"PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
- "clk" (for "arm,gic-400")
+ "clk" (for "arm,gic-400" and "nvidia,tegra210")
"gclk" (for "arm,pl390")
- power-domains : A phandle and PM domain specifier as defined by bindings of
diff --git a/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt b/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
new file mode 100644
index 0000000..6c6e853
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
@@ -0,0 +1,22 @@
+Aspeed Vectored Interrupt Controller
+
+These bindings are for the Aspeed AST2400 interrupt controller register layout.
+The SoC has an legacy register layout, but this driver does not support that
+mode of operation.
+
+Required properties:
+
+- compatible : should be "aspeed,ast2400-vic".
+
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+Example:
+
+ vic: interrupt-controller@1e6c0080 {
+ compatible = "aspeed,ast2400-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1e6c0080 0x80>;
+ };
diff --git a/dts/Bindings/interrupt-controller/cirrus,clps711x-intc.txt b/dts/Bindings/interrupt-controller/cirrus,clps711x-intc.txt
index 759339c..969b458 100644
--- a/dts/Bindings/interrupt-controller/cirrus,clps711x-intc.txt
+++ b/dts/Bindings/interrupt-controller/cirrus,clps711x-intc.txt
@@ -2,7 +2,7 @@ Cirrus Logic CLPS711X Interrupt Controller
Required properties:
-- compatible: Should be "cirrus,clps711x-intc".
+- compatible: Should be "cirrus,ep7209-intc".
- reg: Specifies base physical address of the registers set.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
@@ -34,7 +34,7 @@ ID Name Description
Example:
intc: interrupt-controller {
- compatible = "cirrus,clps711x-intc";
+ compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
reg = <0x80000000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index 8cf564d..9d1d72c 100644
--- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -9,6 +9,7 @@ Required properties:
"mediatek,mt8135-sysirq"
"mediatek,mt8127-sysirq"
"mediatek,mt6795-sysirq"
+ "mediatek,mt6755-sysirq"
"mediatek,mt6592-sysirq"
"mediatek,mt6589-sysirq"
"mediatek,mt6582-sysirq"
diff --git a/dts/Bindings/iommu/arm,smmu-v3.txt b/dts/Bindings/iommu/arm,smmu-v3.txt
index 947863a..7b94c88 100644
--- a/dts/Bindings/iommu/arm,smmu-v3.txt
+++ b/dts/Bindings/iommu/arm,smmu-v3.txt
@@ -1,6 +1,6 @@
* ARM SMMUv3 Architecture Implementation
-The SMMUv3 architecture is a significant deparature from previous
+The SMMUv3 architecture is a significant departure from previous
revisions, replacing the MMIO register interface with in-memory command
and event queues and adding support for the ATS and PRI components of
the PCIe specification.
diff --git a/dts/Bindings/iommu/mediatek,iommu.txt b/dts/Bindings/iommu/mediatek,iommu.txt
index cd1b1cd..53c20ca 100644
--- a/dts/Bindings/iommu/mediatek,iommu.txt
+++ b/dts/Bindings/iommu/mediatek,iommu.txt
@@ -1,7 +1,9 @@
* Mediatek IOMMU Architecture Implementation
- Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which
-uses the ARM Short-Descriptor translation table format for address translation.
+ Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
+this M4U have two generations of HW architecture. Generation one uses flat
+pagetable, and only supports 4K size page mapping. Generation two uses the
+ARM Short-Descriptor translation table format for address translation.
About the M4U Hardware Block Diagram, please check below:
@@ -36,7 +38,9 @@ in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
Required properties:
-- compatible : must be "mediatek,mt8173-m4u".
+- compatible : must be one of the following string:
+ "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
+ "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
@@ -46,7 +50,8 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
- dt-binding/memory/mt8173-larb-port.h.
+ dt-binding/memory/mt2701-larb-port.h for mt2701 and
+ dt-binding/memory/mt8173-larb-port.h for mt8173
Example:
iommu: iommu@10205000 {
diff --git a/dts/Bindings/iommu/msm,iommu-v0.txt b/dts/Bindings/iommu/msm,iommu-v0.txt
new file mode 100644
index 0000000..2023638
--- /dev/null
+++ b/dts/Bindings/iommu/msm,iommu-v0.txt
@@ -0,0 +1,64 @@
+* QCOM IOMMU
+
+The MSM IOMMU is an implementation compatible with the ARM VMSA short
+descriptor page tables. It provides address translation for bus masters outside
+of the CPU, each connected to the IOMMU through a port called micro-TLB.
+
+Required Properties:
+
+ - compatible: Must contain "qcom,apq8064-iommu".
+ - reg: Base address and size of the IOMMU registers.
+ - interrupts: Specifiers for the MMU fault interrupts. For instances that
+ support secure mode two interrupts must be specified, for non-secure and
+ secure mode, in that order. For instances that don't support secure mode a
+ single interrupt must be specified.
+ - #iommu-cells: The number of cells needed to specify the stream id. This
+ is always 1.
+ - qcom,ncb: The total number of context banks in the IOMMU.
+ - clocks : List of clocks to be used during SMMU register access. See
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ for information about the format. For each clock specified
+ here, there must be a corresponding entry in clock-names
+ (see below).
+
+ - clock-names : List of clock names corresponding to the clocks specified in
+ the "clocks" property (above).
+ Should be "smmu_pclk" for specifying the interface clock
+ required for iommu's register accesses.
+ Should be "smmu_clk" for specifying the functional clock
+ required by iommu for bus accesses.
+
+Each bus master connected to an IOMMU must reference the IOMMU in its device
+node with the following property:
+
+ - iommus: A reference to the IOMMU in multiple cells. The first cell is a
+ phandle to the IOMMU and the second cell is the stream id.
+ A single master device can be connected to more than one iommu
+ and multiple contexts in each of the iommu. So multiple entries
+ are required to list all the iommus and the stream ids that the
+ master is connected to.
+
+Example: mdp iommu and its bus master
+
+ mdp_port0: iommu@7500000 {
+ compatible = "qcom,apq8064-iommu";
+ #iommu-cells = <1>;
+ clock-names =
+ "smmu_pclk",
+ "smmu_clk";
+ clocks =
+ <&mmcc SMMU_AHB_CLK>,
+ <&mmcc MDP_AXI_CLK>;
+ reg = <0x07500000 0x100000>;
+ interrupts =
+ <GIC_SPI 63 0>,
+ <GIC_SPI 64 0>;
+ qcom,ncb = <2>;
+ };
+
+ mdp: qcom,mdp@5100000 {
+ compatible = "qcom,mdp";
+ ...
+ iommus = <&mdp_port0 0
+ &mdp_port0 2>;
+ };
diff --git a/dts/Bindings/leds/backlight/lp855x.txt b/dts/Bindings/leds/backlight/lp855x.txt
index 0a3ecbc..88f5664 100644
--- a/dts/Bindings/leds/backlight/lp855x.txt
+++ b/dts/Bindings/leds/backlight/lp855x.txt
@@ -13,6 +13,7 @@ Optional properties:
- rom-addr: Register address of ROM area to be updated (u8)
- rom-val: Register value to be updated (u8)
- power-supply: Regulator which controls the 3V rail
+ - enable-supply: Regulator which controls the EN/VDDIO input
Example:
@@ -57,6 +58,7 @@ Example:
backlight@2c {
compatible = "ti,lp8557";
reg = <0x2c>;
+ enable-supply = <&backlight_vddio>;
power-supply = <&backlight_vdd>;
dev-ctrl = /bits/ 8 <0x41>;
diff --git a/dts/Bindings/leds/common.txt b/dts/Bindings/leds/common.txt
index af10678..93ef6e6 100644
--- a/dts/Bindings/leds/common.txt
+++ b/dts/Bindings/leds/common.txt
@@ -26,7 +26,9 @@ Optional properties for child nodes:
"default-on" - LED will turn on (but for leds-gpio see "default-state"
property in Documentation/devicetree/bindings/gpio/led.txt)
"heartbeat" - LED "double" flashes at a load average based rate
- "ide-disk" - LED indicates disk activity
+ "disk-activity" - LED indicates disk activity
+ "ide-disk" - LED indicates IDE disk activity (deprecated),
+ in new implementations use "disk-activity"
"timer" - LED flashes at a fixed, configurable rate
- led-max-microamp : Maximum LED supply current in microamperes. This property
diff --git a/dts/Bindings/leds/leds-gpio.txt b/dts/Bindings/leds/leds-gpio.txt
index cbbeb18..5b1b43a 100644
--- a/dts/Bindings/leds/leds-gpio.txt
+++ b/dts/Bindings/leds/leds-gpio.txt
@@ -33,9 +33,9 @@ Examples:
leds {
compatible = "gpio-leds";
hdd {
- label = "IDE Activity";
+ label = "Disk Activity";
gpios = <&mcu_pio 0 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "ide-disk";
+ linux,default-trigger = "disk-activity";
};
fault {
diff --git a/dts/Bindings/leds/leds-pca9532.txt b/dts/Bindings/leds/leds-pca9532.txt
new file mode 100644
index 0000000..198f3ba
--- /dev/null
+++ b/dts/Bindings/leds/leds-pca9532.txt
@@ -0,0 +1,39 @@
+*NXP - pca9532 PWM LED Driver
+
+The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
+The PWM support 256 steps.
+
+Required properties:
+ - compatible:
+ "nxp,pca9530"
+ "nxp,pca9531"
+ "nxp,pca9532"
+ "nxp,pca9533"
+ - reg - I2C slave address
+
+Each led is represented as a sub-node of the nxp,pca9530.
+
+Optional sub-node properties:
+ - label: see Documentation/devicetree/bindings/leds/common.txt
+ - type: Output configuration, see dt-bindings/leds/leds-pca9532.h (default NONE)
+ - linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt
+
+Example:
+ #include <dt-bindings/leds/leds-pca9532.h>
+
+ leds: pca9530@60 {
+ compatible = "nxp,pca9530";
+ reg = <0x60>;
+
+ red-power {
+ label = "pca:red:power";
+ type = <PCA9532_TYPE_LED>;
+ };
+ green-power {
+ label = "pca:green:power";
+ type = <PCA9532_TYPE_LED>;
+ };
+ };
+
+For more product information please see the link below:
+http://nxp.com/documents/data_sheet/PCA9532.pdf
diff --git a/dts/Bindings/mailbox/brcm,iproc-pdc-mbox.txt b/dts/Bindings/mailbox/brcm,iproc-pdc-mbox.txt
new file mode 100644
index 0000000..411ccf4
--- /dev/null
+++ b/dts/Bindings/mailbox/brcm,iproc-pdc-mbox.txt
@@ -0,0 +1,23 @@
+The PDC driver manages data transfer to and from various offload engines
+on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is
+one device tree entry per block.
+
+Required properties:
+- compatible : Should be "brcm,iproc-pdc-mbox".
+- reg: Should contain PDC registers location and length.
+- interrupts: Should contain the IRQ line for the PDC.
+- #mbox-cells: 1
+- brcm,rx-status-len: Length of metadata preceding received frames, in bytes.
+
+Optional properties:
+- brcm,use-bcm-hdr: present if a BCM header precedes each frame.
+
+Example:
+ pdc0: iproc-pdc0@0x612c0000 {
+ compatible = "brcm,iproc-pdc-mbox";
+ reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>; /* one cell per mailbox channel */
+ brcm,rx-status-len = <32>;
+ brcm,use-bcm-hdr;
+ };
diff --git a/dts/Bindings/media/mediatek-vcodec.txt b/dts/Bindings/media/mediatek-vcodec.txt
new file mode 100644
index 0000000..59a47a5
--- /dev/null
+++ b/dts/Bindings/media/mediatek-vcodec.txt
@@ -0,0 +1,59 @@
+Mediatek Video Codec
+
+Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
+supports high resolution encoding functionalities.
+
+Required properties:
+- compatible : "mediatek,mt8173-vcodec-enc" for encoder
+- reg : Physical base address of the video codec registers and length of
+ memory mapped region.
+- interrupts : interrupt number to the cpu.
+- mediatek,larb : must contain the local arbiters in the current Socs.
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property.
+- clock-names: encoder must contain "venc_sel_src", "venc_sel",
+- "venc_lt_sel_src", "venc_lt_sel".
+- iommus : should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+- mediatek,vpu : the node of video processor unit
+
+Example:
+vcodec_enc: vcodec@0x18002000 {
+ compatible = "mediatek,mt8173-vcodec-enc";
+ reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
+ <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>,
+ <&larb5>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU>,
+ <&iommu M4U_PORT_VENC_REC>,
+ <&iommu M4U_PORT_VENC_BSDMA>,
+ <&iommu M4U_PORT_VENC_SV_COMV>,
+ <&iommu M4U_PORT_VENC_RD_COMV>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA>,
+ <&iommu M4U_PORT_VENC_REF_LUMA>,
+ <&iommu M4U_PORT_VENC_REF_CHROMA>,
+ <&iommu M4U_PORT_VENC_NBM_RDMA>,
+ <&iommu M4U_PORT_VENC_NBM_WDMA>,
+ <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL1_D2>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_sel_src",
+ "venc_sel",
+ "venc_lt_sel_src",
+ "venc_lt_sel";
+ };
diff --git a/dts/Bindings/media/mediatek-vpu.txt b/dts/Bindings/media/mediatek-vpu.txt
new file mode 100644
index 0000000..2a5bac3
--- /dev/null
+++ b/dts/Bindings/media/mediatek-vpu.txt
@@ -0,0 +1,31 @@
+* Mediatek Video Processor Unit
+
+Video Processor Unit is a HW video controller. It controls HW Codec including
+H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
+
+Required properties:
+ - compatible: "mediatek,mt8173-vpu"
+ - reg: Must contain an entry for each entry in reg-names.
+ - reg-names: Must include the following entries:
+ "tcm": tcm base
+ "cfg_reg": Main configuration registers base
+ - interrupts: interrupt number to the cpu.
+ - clocks : clock name from clock manager
+ - clock-names: must be main. It is the main clock of VPU
+
+Optional properties:
+ - memory-region: phandle to a node describing memory (see
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
+ to be used for VPU extended memory; if not present, VPU may be located
+ anywhere in the memory
+
+Example:
+ vpu: vpu@10020000 {
+ compatible = "mediatek,mt8173-vpu";
+ reg = <0 0x10020000 0 0x30000>,
+ <0 0x10050000 0 0x100>;
+ reg-names = "tcm", "cfg_reg";
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen TOP_SCP_SEL>;
+ clock-names = "main";
+ };
diff --git a/dts/Bindings/media/nokia,n900-ir b/dts/Bindings/media/nokia,n900-ir
new file mode 100644
index 0000000..13a18ce
--- /dev/null
+++ b/dts/Bindings/media/nokia,n900-ir
@@ -0,0 +1,20 @@
+Device-Tree bindings for LIRC TX driver for Nokia N900(RX51)
+
+Required properties:
+ - compatible: should be "nokia,n900-ir".
+ - pwms: specifies PWM used for IR signal transmission.
+
+Example node:
+
+ pwm9: dmtimer-pwm@9 {
+ compatible = "ti,omap-dmtimer-pwm";
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x00>; /* timer_sys_ck */
+ #pwm-cells = <3>;
+ };
+
+ ir: n900-ir {
+ compatible = "nokia,n900-ir";
+
+ pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
+ };
diff --git a/dts/Bindings/media/renesas,fcp.txt b/dts/Bindings/media/renesas,fcp.txt
new file mode 100644
index 0000000..6a12960
--- /dev/null
+++ b/dts/Bindings/media/renesas,fcp.txt
@@ -0,0 +1,32 @@
+Renesas R-Car Frame Compression Processor (FCP)
+-----------------------------------------------
+
+The FCP is a companion module of video processing modules in the Renesas R-Car
+Gen3 SoCs. It provides data compression and decompression, data caching, and
+conversion of AXI transactions in order to reduce the memory bandwidth.
+
+There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP
+for FDP (FCPF). Their configuration and behaviour depend on the module they
+are paired with. These DT bindings currently support the FCPV only.
+
+ - compatible: Must be one or more of the following
+
+ - "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'
+ - "renesas,fcpv" for generic compatible 'FCP for VSP'
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first, followed by the
+ family-specific and/or generic versions.
+
+ - reg: the register base and size for the device registers
+ - clocks: Reference to the functional clock
+
+
+Device node example
+-------------------
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ };
diff --git a/dts/Bindings/media/renesas,vsp1.txt b/dts/Bindings/media/renesas,vsp1.txt
index 627405a..9b695bc 100644
--- a/dts/Bindings/media/renesas,vsp1.txt
+++ b/dts/Bindings/media/renesas,vsp1.txt
@@ -14,6 +14,11 @@ Required properties:
- interrupts: VSP interrupt specifier.
- clocks: A phandle + clock-specifier pair for the VSP functional clock.
+Optional properties:
+
+ - renesas,fcp: A phandle referencing the FCP that handles memory accesses
+ for the VSP. Not needed on Gen2, mandatory on Gen3.
+
Example: R8A7790 (R-Car H2) VSP1-S node
diff --git a/dts/Bindings/media/s5p-cec.txt b/dts/Bindings/media/s5p-cec.txt
new file mode 100644
index 0000000..925ab4d
--- /dev/null
+++ b/dts/Bindings/media/s5p-cec.txt
@@ -0,0 +1,31 @@
+* Samsung HDMI CEC driver
+
+The HDMI CEC module is present is Samsung SoCs and its purpose is to
+handle communication between HDMI connected devices over the CEC bus.
+
+Required properties:
+ - compatible : value should be following
+ "samsung,s5p-cec"
+
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+ - interrupts : HDMI CEC interrupt number to the CPU.
+ - clocks : from common clock binding: handle to HDMI CEC clock.
+ - clock-names : from common clock binding: must contain "hdmicec",
+ corresponding to entry in the clocks property.
+ - samsung,syscon-phandle - phandle to the PMU system controller
+
+Example:
+
+hdmicec: cec@100B0000 {
+ compatible = "samsung,s5p-cec";
+ reg = <0x100B0000 0x200>;
+ interrupts = <0 114 0>;
+ clocks = <&clock CLK_HDMI_CEC>;
+ clock-names = "hdmicec";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
diff --git a/dts/Bindings/media/s5p-mfc.txt b/dts/Bindings/media/s5p-mfc.txt
index 2d5787e..92c94f5 100644
--- a/dts/Bindings/media/s5p-mfc.txt
+++ b/dts/Bindings/media/s5p-mfc.txt
@@ -21,15 +21,18 @@ Required properties:
- clock-names : from common clock binding: must contain "mfc",
corresponding to entry in the clocks property.
- - samsung,mfc-r : Base address of the first memory bank used by MFC
- for DMA contiguous memory allocation and its size.
-
- - samsung,mfc-l : Base address of the second memory bank used by MFC
- for DMA contiguous memory allocation and its size.
-
Optional properties:
- power-domains : power-domain property defined with a phandle
to respective power domain.
+ - memory-region : from reserved memory binding: phandles to two reserved
+ memory regions, first is for "left" mfc memory bus interfaces,
+ second if for the "right" mfc memory bus, used when no SYSMMU
+ support is available
+
+Obsolete properties:
+ - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
+ property instead
+
Example:
SoC specific DT entry:
@@ -43,9 +46,29 @@ mfc: codec@13400000 {
clock-names = "mfc";
};
+Reserved memory specific DT entry for given board (see reserved memory binding
+for more information):
+
+reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mfc_left: region@51000000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0x51000000 0x800000>;
+ };
+
+ mfc_right: region@43000000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0x43000000 0x800000>;
+ };
+};
+
Board specific DT entry:
codec@13400000 {
- samsung,mfc-r = <0x43000000 0x800000>;
- samsung,mfc-l = <0x51000000 0x800000>;
+ memory-region = <&mfc_left>, <&mfc_right>;
};
diff --git a/dts/Bindings/memory-controllers/atmel,ebi.txt b/dts/Bindings/memory-controllers/atmel,ebi.txt
new file mode 100644
index 0000000..9bb5f57
--- /dev/null
+++ b/dts/Bindings/memory-controllers/atmel,ebi.txt
@@ -0,0 +1,136 @@
+* Device tree bindings for Atmel EBI
+
+The External Bus Interface (EBI) controller is a bus where you can connect
+asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
+The EBI provides a glue-less interface to asynchronous memories through the SMC
+(Static Memory Controller).
+
+Required properties:
+
+- compatible: "atmel,at91sam9260-ebi"
+ "atmel,at91sam9261-ebi"
+ "atmel,at91sam9263-ebi0"
+ "atmel,at91sam9263-ebi1"
+ "atmel,at91sam9rl-ebi"
+ "atmel,at91sam9g45-ebi"
+ "atmel,at91sam9x5-ebi"
+ "atmel,sama5d3-ebi"
+
+- reg: Contains offset/length value for EBI memory mapping.
+ This property might contain several entries if the EBI
+ memory range is not contiguous
+
+- #address-cells: Must be 2.
+ The first cell encodes the CS.
+ The second cell encode the offset into the CS memory
+ range.
+
+- #size-cells: Must be set to 1.
+
+- ranges: Encodes CS to memory region association.
+
+- clocks: Clock feeding the EBI controller.
+ See clock-bindings.txt
+
+Children device nodes are representing device connected to the EBI bus.
+
+Required device node properties:
+
+- reg: Contains the chip-select id, the offset and the length
+ of the memory region requested by the device.
+
+EBI bus configuration will be defined directly in the device subnode.
+
+Optional EBI/SMC properties:
+
+- atmel,smc-bus-width: width of the asynchronous device's data bus
+ 8, 16 or 32.
+ Default to 8 when undefined.
+
+- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet).
+ Default to "select" when undefined.
+
+- atmel,smc-read-mode "nrd" or "ncs".
+ Default to "ncs" when undefined.
+
+- atmel,smc-write-mode "nwe" or "ncs".
+ Default to "ncs" when undefined.
+
+- atmel,smc-exnw-mode "disabled", "frozen" or "ready".
+ Default to "disabled" when undefined.
+
+- atmel,smc-page-mode enable page mode if present. The provided value
+ defines the page size (supported values: 4, 8,
+ 16 and 32).
+
+- atmel,smc-tdf-mode: "normal" or "optimized". When set to
+ "optimized" the data float time is optimized
+ depending on the next device being accessed
+ (next device setup time is subtracted to the
+ current device data float time).
+ Default to "normal" when undefined.
+
+If at least one atmel,smc- property is defined the following SMC timing
+properties become mandatory. In the other hand, if none of the atmel,smc-
+properties are specified, we assume that the EBI bus configuration will be
+handled by the sub-device driver, and none of those properties should be
+defined.
+
+All the timings are expressed in nanoseconds (see Atmel datasheet for a full
+description).
+
+- atmel,smc-ncs-rd-setup-ns
+- atmel,smc-nrd-setup-ns
+- atmel,smc-ncs-wr-setup-ns
+- atmel,smc-nwe-setup-ns
+- atmel,smc-ncs-rd-pulse-ns
+- atmel,smc-nrd-pulse-ns
+- atmel,smc-ncs-wr-pulse-ns
+- atmel,smc-nwe-pulse-ns
+- atmel,smc-nwe-cycle-ns
+- atmel,smc-nrd-cycle-ns
+- atmel,smc-tdf-ns
+
+Example:
+
+ ebi: ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&hsmc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x10000000
+ 0x40000000 0x30000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x40000000 0x10000000
+ 0x2 0x0 0x50000000 0x10000000
+ 0x3 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr>;
+
+ nor: flash@0,0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+
+ atmel,smc-read-mode = "nrd";
+ atmel,smc-write-mode = "nwe";
+ atmel,smc-bus-width = <16>;
+ atmel,smc-ncs-rd-setup-ns = <0>;
+ atmel,smc-ncs-wr-setup-ns = <0>;
+ atmel,smc-nwe-setup-ns = <8>;
+ atmel,smc-nrd-setup-ns = <16>;
+ atmel,smc-ncs-rd-pulse-ns = <84>;
+ atmel,smc-ncs-wr-pulse-ns = <84>;
+ atmel,smc-nrd-pulse-ns = <76>;
+ atmel,smc-nwe-pulse-ns = <76>;
+ atmel,smc-nrd-cycle-ns = <107>;
+ atmel,smc-nwe-cycle-ns = <84>;
+ atmel,smc-tdf-ns = <16>;
+ };
+ };
+
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-common.txt b/dts/Bindings/memory-controllers/mediatek,smi-common.txt
index 06a83ce..aa614b2 100644
--- a/dts/Bindings/memory-controllers/mediatek,smi-common.txt
+++ b/dts/Bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,16 +2,31 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
+Mediatek SMI have two generations of HW architecture, mt8173 uses the second
+generation of SMI HW while mt2701 uses the first generation HW of SMI.
+
+There's slight differences between the two SMI, for generation 2, the
+register which control the iommu port is at each larb's register base. But
+for generation 1, the register is at smi ao base(smi always on register
+base). Besides that, the smi async clock should be prepared and enabled for
+SMI generation 1 to transform the smi clock into emi clock domain, but that is
+not needed for SMI generation 2.
+
Required properties:
-- compatible : must be "mediatek,mt8173-smi-common"
+- compatible : must be one of :
+ "mediatek,mt2701-smi-common"
+ "mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : must contain 2 entries, as follows:
+- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
+ for generation 2 smi HW as follows:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
- They may be the same if both source clocks are the same.
+ They may be the same if both source clocks are the same.
+ - "async" : asynchronous clock, it help transform the smi clock into the emi
+ clock domain, this clock is only needed by generation 1 smi HW.
Example:
smi_common: smi@14022000 {
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
index 55ff3b7..21277a5 100644
--- a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
@@ -3,7 +3,9 @@ SMI (Smart Multimedia Interface) Local Arbiter
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Required properties:
-- compatible : must be "mediatek,mt8173-smi-larb"
+- compatible : must be one of :
+ "mediatek,mt8173-smi-larb"
+ "mediatek,mt2701-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
diff --git a/dts/Bindings/memory-controllers/omap-gpmc.txt b/dts/Bindings/memory-controllers/omap-gpmc.txt
index 21055e2..c1359f4 100644
--- a/dts/Bindings/memory-controllers/omap-gpmc.txt
+++ b/dts/Bindings/memory-controllers/omap-gpmc.txt
@@ -46,6 +46,10 @@ Required properties:
0 maps to GPMC_WAIT0 pin.
- gpio-cells: Must be set to 2
+Required properties when using NAND prefetch dma:
+ - dmas GPMC NAND prefetch dma channel
+ - dma-names Must be set to "rxtx"
+
Timing properties for child nodes. All are optional and default to 0.
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
@@ -137,7 +141,8 @@ Example for an AM33xx board:
ti,hwmods = "gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
-
+ dmas = <&edma 52 0>;
+ dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index d20b103..585a955 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -22,6 +22,11 @@ Optional properties:
AXP152/20X: range: 750-1875, Default: 1.5 MHz
AXP22X/80X: range: 1800-4050, Default: 3 MHz
+- x-powers,drive-vbus-en: axp221 / axp223 only boolean, set this when the
+ N_VBUSEN pin is used as an output pin to control an external
+ regulator to drive the OTG VBus, rather then as an input pin
+ which signals whether the board is driving OTG VBus or not.
+
- <input>-supply: a phandle to the regulator supply node. May be omitted if
inputs are unregulated, such as using the IPSOUT output
from the PMIC.
@@ -79,6 +84,7 @@ ELDO3 : LDO : eldoin-supply : shared supply
LDO_IO0 : LDO : ips-supply : GPIO 0
LDO_IO1 : LDO : ips-supply : GPIO 1
RTC_LDO : LDO : ips-supply : always on
+DRIVEVBUS : Enable output : drivevbus-supply : external regulator
AXP809 regulators, type, and corresponding input supply names:
diff --git a/dts/Bindings/mfd/da9052-i2c.txt b/dts/Bindings/mfd/da9052-i2c.txt
index 1857f4a..9554292 100644
--- a/dts/Bindings/mfd/da9052-i2c.txt
+++ b/dts/Bindings/mfd/da9052-i2c.txt
@@ -8,10 +8,13 @@ Sub-nodes:
- regulators : Contain the regulator nodes. The DA9052/53 regulators are
bound using their names as listed below:
- buck0 : regulator BUCK0
- buck1 : regulator BUCK1
- buck2 : regulator BUCK2
- buck3 : regulator BUCK3
+ buck1 : regulator BUCK CORE
+ buck2 : regulator BUCK PRO
+ buck3 : regulator BUCK MEM
+ buck4 : regulator BUCK PERI
+ ldo1 : regulator LDO1
+ ldo2 : regulator LDO2
+ ldo3 : regulator LDO3
ldo4 : regulator LDO4
ldo5 : regulator LDO5
ldo6 : regulator LDO6
@@ -19,9 +22,6 @@ Sub-nodes:
ldo8 : regulator LDO8
ldo9 : regulator LDO9
ldo10 : regulator LDO10
- ldo11 : regulator LDO11
- ldo12 : regulator LDO12
- ldo13 : regulator LDO13
The bindings details of individual regulator device can be found in:
Documentation/devicetree/bindings/regulator/regulator.txt
@@ -36,22 +36,22 @@ i2c@63fc8000 { /* I2C1 */
reg = <0x48>;
regulators {
- buck0 {
+ buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
};
- buck1 {
+ buck2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
};
- buck2 {
+ buck3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
};
- buck3 {
+ buck4 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
};
diff --git a/dts/Bindings/mfd/rn5t618.txt b/dts/Bindings/mfd/rn5t618.txt
index 937785a..9e6770b 100644
--- a/dts/Bindings/mfd/rn5t618.txt
+++ b/dts/Bindings/mfd/rn5t618.txt
@@ -1,18 +1,21 @@
-* Ricoh RN5T618 PMIC
+* Ricoh RN5T567/RN5T618 PMIC
-Ricoh RN5T618 is a power management IC which integrates 3 step-down
-DCDC converters, 7 low-dropout regulators, a Li-ion battery charger,
-fuel gauge, ADC, GPIOs and a watchdog timer. It can be controlled
-through a I2C interface.
+Ricoh RN5T567/RN5T618 is a power management IC family which integrates
+3 to 4 step-down DCDC converters, 7 low-dropout regulators, GPIOs and
+a watchdog timer. The RN5T618 provides additionally a Li-ion battery
+charger, fuel gauge and an ADC. It can be controlled through an I2C
+interface.
Required properties:
- - compatible: should be "ricoh,rn5t618"
+ - compatible: must be one of
+ "ricoh,rn5t567"
+ "ricoh,rn5t618"
- reg: the I2C slave address of the device
Sub-nodes:
- regulators: the node is required if the regulator functionality is
- needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, LDO1,
- LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2.
+ needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4
+ (RN5T567), LDO1, LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2.
The common bindings for each individual regulator can be found in:
Documentation/devicetree/bindings/regulator/regulator.txt
diff --git a/dts/Bindings/mfd/twl6040.txt b/dts/Bindings/mfd/twl6040.txt
index a41157b..e6afdfa 100644
--- a/dts/Bindings/mfd/twl6040.txt
+++ b/dts/Bindings/mfd/twl6040.txt
@@ -19,8 +19,8 @@ Required properties:
Optional properties, nodes:
- enable-active-high: To power on the twl6040 during boot.
-- clocks: phandle to the clk32k clock provider
-- clock-names: Must be "clk32k"
+- clocks: phandle to the clk32k and/or to mclk clock provider
+- clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK.
Vibra functionality
Required properties:
diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt
index 31b35c3..3404afa 100644
--- a/dts/Bindings/mmc/arasan,sdhci.txt
+++ b/dts/Bindings/mmc/arasan,sdhci.txt
@@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller
[4] Documentation/devicetree/bindings/phy/phy-bindings.txt
Required Properties:
- - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
- 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
+ - compatible: Compatibility string. One of:
+ - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
+ - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
+ - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
+ - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
+ For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
@@ -22,6 +26,17 @@ Required Properties for "arasan,sdhci-5.1":
- phys: From PHY bindings: Phandle for the Generic PHY for arasan.
- phy-names: MUST be "phy_arasan".
+Optional Properties:
+ - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
+ used to access core corecfg registers. Offsets of registers in this
+ syscon are determined based on the main compatible string for the device.
+ - clock-output-names: If specified, this will be the name of the card clock
+ which will be exposed by this device. Required if #clock-cells is
+ specified.
+ - #clock-cells: If specified this should be the value <0>. With this property
+ in place we will export a clock representing the Card Clock. This clock
+ is expected to be consumed by our PHY. You must also specify
+
Example:
sdhci@e0100000 {
compatible = "arasan,sdhci-8.9a";
@@ -42,3 +57,19 @@ Example:
phys = <&emmc_phy>;
phy-names = "phy_arasan";
} ;
+
+ sdhci: sdhci@fe330000 {
+ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+ reg = <0x0 0xfe330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+ clock-names = "clk_xin", "clk_ahb";
+ arasan,soc-ctl-syscon = <&grf>;
+ assigned-clocks = <&cru SCLK_EMMC>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ #clock-cells = <0>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/mmc/brcm,bcm2835-sdhci.txt b/dts/Bindings/mmc/brcm,bcm2835-sdhci.txt
deleted file mode 100644
index 59476fb..0000000
--- a/dts/Bindings/mmc/brcm,bcm2835-sdhci.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Broadcom BCM2835 SDHCI controller
-
-This file documents differences between the core properties described
-by mmc.txt and the properties that represent the BCM2835 controller.
-
-Required properties:
-- compatible : Should be "brcm,bcm2835-sdhci".
-- clocks : The clock feeding the SDHCI controller.
-
-Example:
-
-sdhci: sdhci {
- compatible = "brcm,bcm2835-sdhci";
- reg = <0x7e300000 0x100>;
- interrupts = <2 30>;
- clocks = <&clk_mmc>;
- bus-width = <4>;
-};
diff --git a/dts/Bindings/mmc/brcm,bcm7425-sdhci.txt b/dts/Bindings/mmc/brcm,bcm7425-sdhci.txt
new file mode 100644
index 0000000..8284717
--- /dev/null
+++ b/dts/Bindings/mmc/brcm,bcm7425-sdhci.txt
@@ -0,0 +1,36 @@
+* BROADCOM BRCMSTB/BMIPS SDHCI Controller
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-brcmstb driver.
+
+NOTE: The driver disables all UHS speed modes by default and depends
+on Device Tree properties to enable them for SoC/Board combinations
+that support them.
+
+Required properties:
+- compatible: "brcm,bcm7425-sdhci"
+
+Refer to clocks/clock-bindings.txt for generic clock consumer properties.
+
+Example:
+
+ sdhci@f03e0100 {
+ compatible = "brcm,bcm7425-sdhci";
+ reg = <0xf03e0000 0x100>;
+ interrupts = <0x0 0x26 0x0>;
+ sdhci,auto-cmd12;
+ clocks = <&sw_sdio>;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ };
+
+ sdhci@f03e0300 {
+ non-removable;
+ bus-width = <0x8>;
+ compatible = "brcm,bcm7425-sdhci";
+ reg = <0xf03e0200 0x100>;
+ interrupts = <0x0 0x27 0x0>;
+ sdhci,auto-cmd12;
+ clocks = <sw_sdio>;
+ mmc-hs200-1_8v;
+ };
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.txt b/dts/Bindings/mmc/fsl-imx-esdhc.txt
index dca56d6..3e29050 100644
--- a/dts/Bindings/mmc/fsl-imx-esdhc.txt
+++ b/dts/Bindings/mmc/fsl-imx-esdhc.txt
@@ -28,6 +28,8 @@ Optional properties:
transparent level shifters on the outputs of the controller. Two cells are
required, first cell specifies minimum slot voltage (mV), second cell
specifies maximum slot voltage (mV). Several ranges could be specified.
+- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
+ in tuning procedure.
- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
The uSDHC use one delay cell as default increasing step to do tuning process.
This property allows user to change the tuning step to more than one delay
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index ed23b9b..22d1e1f 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -46,8 +46,12 @@ Optional properties:
- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
+- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported
- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
programmed with. Valid range: [0 .. 0xffff].
+- no-sdio: controller is limited to send sdio cmd during initialization
+- no-sd: controller is limited to send sd cmd during initialization
+- no-mmc: controller is limited to send mmc cmd during initialization
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"
diff --git a/dts/Bindings/mtd/atmel-quadspi.txt b/dts/Bindings/mtd/atmel-quadspi.txt
new file mode 100644
index 0000000..4898070
--- /dev/null
+++ b/dts/Bindings/mtd/atmel-quadspi.txt
@@ -0,0 +1,32 @@
+* Atmel Quad Serial Peripheral Interface (QSPI)
+
+Required properties:
+- compatible: Should be "atmel,sama5d2-qspi".
+- reg: Should contain the locations and lengths of the base registers
+ and the mapped memory.
+- reg-names: Should contain the resource reg names:
+ - qspi_base: configuration register address space
+ - qspi_mmap: memory mapped address space
+- interrupts: Should contain the interrupt for the device.
+- clocks: The phandle of the clock needed by the QSPI controller.
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+
+Example:
+
+spi@f0020000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&spi0_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+ status = "okay";
+
+ m25p80@0 {
+ ...
+ };
+};
diff --git a/dts/Bindings/mtd/brcm,brcmnand.txt b/dts/Bindings/mtd/brcm,brcmnand.txt
index 7066597..b40f3a4 100644
--- a/dts/Bindings/mtd/brcm,brcmnand.txt
+++ b/dts/Bindings/mtd/brcm,brcmnand.txt
@@ -27,6 +27,7 @@ Required properties:
brcm,brcmnand-v6.2
brcm,brcmnand-v7.0
brcm,brcmnand-v7.1
+ brcm,brcmnand-v7.2
brcm,brcmnand
- reg : the register start and length for NAND register region.
(optional) Flash DMA register range (if present)
diff --git a/dts/Bindings/mtd/cadence-quadspi.txt b/dts/Bindings/mtd/cadence-quadspi.txt
new file mode 100644
index 0000000..f248056
--- /dev/null
+++ b/dts/Bindings/mtd/cadence-quadspi.txt
@@ -0,0 +1,56 @@
+* Cadence Quad SPI controller
+
+Required properties:
+- compatible : Should be "cdns,qspi-nor".
+- reg : Contains two entries, each of which is a tuple consisting of a
+ physical address and length. The first entry is the address and
+ length of the controller register set. The second entry is the
+ address and length of the QSPI Controller data area.
+- interrupts : Unit interrupt specifier for the controller interrupt.
+- clocks : phandle to the Quad SPI clock.
+- cdns,fifo-depth : Size of the data FIFO in words.
+- cdns,fifo-width : Bus width of the data FIFO in bytes.
+- cdns,trigger-address : 32-bit indirect AHB trigger address.
+
+Optional properties:
+- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+
+Optional subnodes:
+Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
+custom properties:
+- cdns,read-delay : Delay for read capture logic, in clock cycles
+- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
+ mode chip select outputs are de-asserted between
+ transactions.
+- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
+ de-activated and the activation of another.
+- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
+ transaction and deasserting the device chip select
+ (qspi_n_ss_out).
+- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
+ and first bit transfer.
+
+Example:
+
+ qspi: spi@ff705000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ cdns,is-decoded-cs;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+
+ flash0: n25q00@0 {
+ ...
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+ };
diff --git a/dts/Bindings/mtd/gpmc-nand.txt b/dts/Bindings/mtd/gpmc-nand.txt
index 3ee7e20..174f68c 100644
--- a/dts/Bindings/mtd/gpmc-nand.txt
+++ b/dts/Bindings/mtd/gpmc-nand.txt
@@ -39,7 +39,7 @@ Optional properties:
"prefetch-polled" Prefetch polled mode (default)
"polled" Polled mode, without prefetch
- "prefetch-dma" Prefetch enabled sDMA mode
+ "prefetch-dma" Prefetch enabled DMA mode
"prefetch-irq" Prefetch enabled irq mode
- elm_id: <deprecated> use "ti,elm-id" instead
diff --git a/dts/Bindings/mtd/hisilicon,fmc-spi-nor.txt b/dts/Bindings/mtd/hisilicon,fmc-spi-nor.txt
new file mode 100644
index 0000000..7498152
--- /dev/null
+++ b/dts/Bindings/mtd/hisilicon,fmc-spi-nor.txt
@@ -0,0 +1,24 @@
+HiSilicon SPI-NOR Flash Controller
+
+Required properties:
+- compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
+ "hisilicon,hi3519-spi-nor"
+- address-cells : Should be 1.
+- size-cells : Should be 0.
+- reg : Offset and length of the register set for the controller device.
+- reg-names : Must include the following two entries: "control", "memory".
+- clocks : handle to spi-nor flash controller clock.
+
+Example:
+spi-nor-controller@10000000 {
+ compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
+ reg-names = "control", "memory";
+ clocks = <&clock HI3519_FMC_CLK>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
diff --git a/dts/Bindings/mtd/mtk-nand.txt b/dts/Bindings/mtd/mtk-nand.txt
new file mode 100644
index 0000000..069c192
--- /dev/null
+++ b/dts/Bindings/mtd/mtk-nand.txt
@@ -0,0 +1,160 @@
+MTK SoCs NAND FLASH controller (NFC) DT binding
+
+This file documents the device tree bindings for MTK SoCs NAND controllers.
+The functional split of the controller requires two drivers to operate:
+the nand controller interface driver and the ECC engine driver.
+
+The hardware description for both devices must be captured as device
+tree nodes.
+
+1) NFC NAND Controller Interface (NFI):
+=======================================
+
+The first part of NFC is NAND Controller Interface (NFI) HW.
+Required NFI properties:
+- compatible: Should be "mediatek,mtxxxx-nfc".
+- reg: Base physical address and size of NFI.
+- interrupts: Interrupts of NFI.
+- clocks: NFI required clocks.
+- clock-names: NFI clocks internal name.
+- status: Disabled default. Then set "okay" by platform.
+- ecc-engine: Required ECC Engine node.
+- #address-cells: NAND chip index, should be 1.
+- #size-cells: Should be 0.
+
+Example:
+
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt2701-nfc";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI>,
+ <&pericfg CLK_PERI_NFI_PAD>;
+ clock-names = "nfi_clk", "pad_clk";
+ status = "disabled";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+Platform related properties, should be set in {platform_name}.dts:
+- children nodes: NAND chips.
+
+Children nodes properties:
+- reg: Chip Select Signal, default 0.
+ Set as reg = <0>, <1> when need 2 CS.
+Optional:
+- nand-on-flash-bbt: Store BBT on NAND Flash.
+- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
+- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
+ valid values: 512 and 1024.
+ 1024 is recommended for large page NANDs.
+- nand-ecc-strength: Number of bits to correct per ECC step.
+ The valid values that the controller supports are: 4, 6,
+ 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
+ 48, 52, 56, 60.
+ The strength should be calculated as follows:
+ E = (S - F) * 8 / 14
+ S = O / (P / Q)
+ E : nand-ecc-strength.
+ S : spare size per sector.
+ F : FDM size, should be in the range [1,8].
+ It is used to store free oob data.
+ O : oob size.
+ P : page size.
+ Q : nand-ecc-step-size.
+ If the result does not match any one of the listed
+ choices above, please select the smaller valid value from
+ the list.
+ (otherwise the driver will do the adjustment at runtime)
+- pinctrl-names: Default NAND pin GPIO setting name.
+- pinctrl-0: GPIO setting node.
+
+Example:
+ &pio {
+ nand_pins_default: nanddefault {
+ pins_dat {
+ pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
+ <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
+ <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
+ <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
+ <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
+ <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
+ <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
+ <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
+ <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up;
+ };
+
+ pins_we {
+ pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins_ale {
+ pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+ };
+
+ &nandc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_default>;
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+ };
+ };
+
+NAND chip optional subnodes:
+- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ preloader@0 {
+ label = "pl";
+ read-only;
+ reg = <0x00000000 0x00400000>;
+ };
+ android@0x00400000 {
+ label = "android";
+ reg = <0x00400000 0x12c00000>;
+ };
+ };
+ };
+
+2) ECC Engine:
+==============
+
+Required BCH properties:
+- compatible: Should be "mediatek,mtxxxx-ecc".
+- reg: Base physical address and size of ECC.
+- interrupts: Interrupts of ECC.
+- clocks: ECC required clocks.
+- clock-names: ECC clocks internal name.
+- status: Disabled default. Then set "okay" by platform.
+
+Example:
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt2701-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
diff --git a/dts/Bindings/mtd/sunxi-nand.txt b/dts/Bindings/mtd/sunxi-nand.txt
index 086d6f4..f322f56 100644
--- a/dts/Bindings/mtd/sunxi-nand.txt
+++ b/dts/Bindings/mtd/sunxi-nand.txt
@@ -11,10 +11,16 @@ Required properties:
* "ahb" : AHB gating clock
* "mod" : nand controller clock
+Optional properties:
+- dmas : shall reference DMA channel associated to the NAND controller.
+- dma-names : shall be "rxtx".
+
Optional children nodes:
Children nodes represent the available nand chips.
Optional properties:
+- reset : phandle + reset specifier pair
+- reset-names : must contain "ahb"
- allwinner,rb : shall contain the native Ready/Busy ids.
or
- rb-gpios : shall contain the gpios used as R/B pins.
diff --git a/dts/Bindings/net/apm-xgene-enet.txt b/dts/Bindings/net/apm-xgene-enet.txt
index 05f705e..e41b2d5 100644
--- a/dts/Bindings/net/apm-xgene-enet.txt
+++ b/dts/Bindings/net/apm-xgene-enet.txt
@@ -59,8 +59,8 @@ Example:
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
- <0x0 0X17030000 0x0 0X400>,
- <0x0 0X10000000 0x0 0X200>;
+ <0x0 0x17030000 0x0 0x400>,
+ <0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
port-id = <0>;
diff --git a/dts/Bindings/net/apm-xgene-mdio.txt b/dts/Bindings/net/apm-xgene-mdio.txt
new file mode 100644
index 0000000..78722d7
--- /dev/null
+++ b/dts/Bindings/net/apm-xgene-mdio.txt
@@ -0,0 +1,37 @@
+APM X-Gene SoC MDIO node
+
+MDIO node is defined to describe on-chip MDIO controller.
+
+Required properties:
+ - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+ - reg: Address and length of the register set
+ - clocks: Reference to the clock entry
+
+For the phys on the mdio bus, there must be a node with the following fields:
+ - compatible: PHY identifier. Please refer ./phy.txt for the format.
+ - reg: The ID number for the phy.
+
+Example:
+
+ mdio: mdio@17020000 {
+ compatible = "apm,xgene-mdio-rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x17020000 0x0 0xd100>;
+ clocks = <&menetclk 0>;
+ };
+
+ /* Board-specific peripheral configurations */
+ &mdio {
+ menetphy: phy@3 {
+ reg = <0x3>;
+ };
+ sgenet0phy: phy@4 {
+ reg = <0x4>;
+ };
+ sgenet1phy: phy@5 {
+ reg = <0x5>;
+ };
+ };
diff --git a/dts/Bindings/net/brcm,mdio-mux-iproc.txt b/dts/Bindings/net/brcm,mdio-mux-iproc.txt
new file mode 100644
index 0000000..dfe287a
--- /dev/null
+++ b/dts/Bindings/net/brcm,mdio-mux-iproc.txt
@@ -0,0 +1,59 @@
+Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
+
+This MDIO bus multiplexer defines buses that could be internal as well as
+external to SoCs and could accept MDIO transaction compatible to C-22 or
+C-45 Clause. When child bus is selected, one needs to select these two
+properties as well to generate desired MDIO transaction on appropriate bus.
+
+Required properties in addition to the generic multiplexer properties:
+
+MDIO multiplexer node:
+- compatible: brcm,mdio-mux-iproc.
+
+Every non-ethernet PHY requires a compatible so that it could be probed based
+on this compatible string.
+
+Additional information regarding generic multiplexer properties can be found
+at- Documentation/devicetree/bindings/net/mdio-mux.txt
+
+
+for example:
+ mdio_mux_iproc: mdio-mux@6602023c {
+ compatible = "brcm,mdio-mux-iproc";
+ reg = <0x6602023c 0x14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pci_phy0: pci-phy@0 {
+ compatible = "brcm,ns2-pcie-phy";
+ reg = <0x0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ mdio@7 {
+ reg = <0x7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pci_phy1: pci-phy@0 {
+ compatible = "brcm,ns2-pcie-phy";
+ reg = <0x0>;
+ #phy-cells = <0>;
+ };
+ };
+ mdio@10 {
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gphy0: eth-phy@10 {
+ reg = <0x10>;
+ };
+ };
+ };
diff --git a/dts/Bindings/net/can/rcar_canfd.txt b/dts/Bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..22a6f10
--- /dev/null
+++ b/dts/Bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,96 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+ - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+ - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first, followed by the
+ family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Optional property:
+The controller can operate in either CAN FD only mode (default) or
+Classical CAN only mode. The mode is global to both the channels. In order to
+enable the later, define the following optional property.
+ - renesas,no-can-fd: puts the controller in Classical CAN only mode.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a7795-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0 0xe66c0000 0 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+ };
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
+
+&canfd {
+ pinctrl-0 = <&canfd1_pins>;
+ pinctrl-names = "default";
+ renesas,no-can-fd;
+ status = "okay";
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+ pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+};
diff --git a/dts/Bindings/net/cavium-pip.txt b/dts/Bindings/net/cavium-pip.txt
index 7dbd158..e3b8fe7 100644
--- a/dts/Bindings/net/cavium-pip.txt
+++ b/dts/Bindings/net/cavium-pip.txt
@@ -37,6 +37,12 @@ Properties for PIP port which is a child the PIP interface:
- phy-handle: Optional, see ethernet.txt file in the same directory.
+- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
+ Value range is 1-31, and mapping to the actual delay varies depending on HW.
+
+- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
+ Value range is 1-31, and mapping to the actual delay varies depending on HW.
+
Example:
pip@11800a0000000 {
diff --git a/dts/Bindings/net/cirrus,cs89x0.txt b/dts/Bindings/net/cirrus,cs89x0.txt
new file mode 100644
index 0000000..c070076
--- /dev/null
+++ b/dts/Bindings/net/cirrus,cs89x0.txt
@@ -0,0 +1,13 @@
+* Cirrus Logic CS8900/CS8920 Network Controller
+
+Required properties:
+- compatible : Should be "cirrus,cs8900" or "cirrus,cs8920".
+- reg : Address and length of the IO space.
+- interrupts : Should contain the controller interrupt line.
+
+Examples:
+ eth0: eth@10000000 {
+ compatible = "cirrus,cs8900";
+ reg = <0x10000000 0x400>;
+ interrupts = <10>;
+ };
diff --git a/dts/Bindings/net/cpsw.txt b/dts/Bindings/net/cpsw.txt
index 0ae0649..5ad439f 100644
--- a/dts/Bindings/net/cpsw.txt
+++ b/dts/Bindings/net/cpsw.txt
@@ -15,7 +15,6 @@ Required properties:
- cpdma_channels : Specifies number of channels in CPDMA
- ale_entries : Specifies No of entries ALE can hold
- bd_ram_size : Specifies internal descriptor RAM size
-- rx_descs : Specifies number of Rx descriptors
- mac_control : Specifies Default MAC control register content
for the specific platform
- slaves : Specifies number for slaves
diff --git a/dts/Bindings/net/davinci-mdio.txt b/dts/Bindings/net/davinci-mdio.txt
index 0369e25..621156c 100644
--- a/dts/Bindings/net/davinci-mdio.txt
+++ b/dts/Bindings/net/davinci-mdio.txt
@@ -2,7 +2,10 @@ TI SoC Davinci/Keystone2 MDIO Controller Device Tree Bindings
---------------------------------------------------
Required properties:
-- compatible : Should be "ti,davinci_mdio" or "ti,keystone_mdio"
+- compatible : Should be "ti,davinci_mdio"
+ and "ti,keystone_mdio" for Keystone 2 SoCs
+ and "ti,cpsw-mdio" for am335x, am472x, am57xx/dra7, dm814x SoCs
+ and "ti,am4372-mdio" for am472x SoC
- reg : physical base address and size of the davinci mdio
registers map
- bus_freq : Mdio Bus frequency
diff --git a/dts/Bindings/net/dsa/b53.txt b/dts/Bindings/net/dsa/b53.txt
new file mode 100644
index 0000000..d6c6e41
--- /dev/null
+++ b/dts/Bindings/net/dsa/b53.txt
@@ -0,0 +1,97 @@
+Broadcom BCM53xx Ethernet switches
+==================================
+
+Required properties:
+
+- compatible: For external switch chips, compatible string must be exactly one
+ of: "brcm,bcm5325"
+ "brcm,bcm53115"
+ "brcm,bcm53125"
+ "brcm,bcm53128"
+ "brcm,bcm5365"
+ "brcm,bcm5395"
+ "brcm,bcm5397"
+ "brcm,bcm5398"
+
+ For the BCM5310x SoCs with an integrated switch, must be one of:
+ "brcm,bcm53010-srab"
+ "brcm,bcm53011-srab"
+ "brcm,bcm53012-srab"
+ "brcm,bcm53018-srab"
+ "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
+
+ For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of:
+ "brcm,bcm58522-srab"
+ "brcm,bcm58523-srab"
+ "brcm,bcm58525-srab"
+ "brcm,bcm58622-srab"
+ "brcm,bcm58623-srab"
+ "brcm,bcm58625-srab"
+ "brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string
+
+ For the BCM63xx/33xx SoCs with an integrated switch, must be one of:
+ "brcm,bcm3384-switch"
+ "brcm,bcm6328-switch"
+ "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
+
+See Documentation/devicetree/bindings/dsa/dsa.txt for a list of additional
+required and optional properties.
+
+Examples:
+
+Ethernet switch connected via MDIO to the host, CPU port wired to eth0:
+
+ eth0: ethernet@10001000 {
+ compatible = "brcm,unimac";
+ reg = <0x10001000 0x1000>;
+
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ };
+
+ mdio0: mdio@10000000 {
+ compatible = "brcm,unimac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0: ethernet-switch@30 {
+ compatible = "brcm,bcm53125";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ port0@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port1@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port5@5 {
+ reg = <5>;
+ label = "cable-modem";
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ phy-mode = "rgmii-txid";
+ };
+
+ port8@8 {
+ reg = <8>;
+ label = "cpu";
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ phy-mode = "rgmii-txid";
+ ethernet = <&eth0>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/net/dsa/dsa.txt b/dts/Bindings/net/dsa/dsa.txt
index 9f4807f..a4a570f 100644
--- a/dts/Bindings/net/dsa/dsa.txt
+++ b/dts/Bindings/net/dsa/dsa.txt
@@ -1,5 +1,279 @@
-Marvell Distributed Switch Architecture Device Tree Bindings
-------------------------------------------------------------
+Distributed Switch Architecture Device Tree Bindings
+----------------------------------------------------
+
+Two bindings exist, one of which has been deprecated due to
+limitations.
+
+Current Binding
+---------------
+
+Switches are true Linux devices and can be probes by any means. Once
+probed, they register to the DSA framework, passing a node
+pointer. This node is expected to fulfil the following binding, and
+may contain additional properties as required by the device it is
+embedded within.
+
+Required properties:
+
+- ports : A container for child nodes representing switch ports.
+
+Optional properties:
+
+- dsa,member : A two element list indicates which DSA cluster, and position
+ within the cluster a switch takes. <0 0> is cluster 0,
+ switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1,
+ switch 0. A switch not part of any cluster (single device
+ hanging off a CPU port) must not specify this property
+
+The ports container has the following properties
+
+Required properties:
+
+- #address-cells : Must be 1
+- #size-cells : Must be 0
+
+Each port children node must have the following mandatory properties:
+- reg : Describes the port address in the switch
+- label : Describes the label associated with this port, which
+ will become the netdev name. Special labels are
+ "cpu" to indicate a CPU port and "dsa" to
+ indicate an uplink/downlink port between switches in
+ the cluster.
+
+A port labelled "dsa" has the following mandatory property:
+
+- link : Should be a list of phandles to other switch's DSA
+ port. This port is used as the outgoing port
+ towards the phandle ports. The full routing
+ information must be given, not just the one hop
+ routes to neighbouring switches.
+
+A port labelled "cpu" has the following mandatory property:
+
+- ethernet : Should be a phandle to a valid Ethernet device node.
+ This host device is what the switch port is
+ connected to.
+
+Port child nodes may also contain the following optional standardised
+properties, described in binding documents:
+
+- phy-handle : Phandle to a PHY on an MDIO bus. See
+ Documentation/devicetree/bindings/net/ethernet.txt
+ for details.
+
+- phy-mode : See
+ Documentation/devicetree/bindings/net/ethernet.txt
+ for details.
+
+- fixed-link : Fixed-link subnode describing a link to a non-MDIO
+ managed entity. See
+ Documentation/devicetree/bindings/net/fixed-link.txt
+ for details.
+
+Example
+
+The following example shows three switches on three MDIO busses,
+linked into one DSA cluster.
+
+&mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0: switch0@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ switch0port5: port@5 {
+ reg = <5>;
+ label = "dsa";
+ phy-mode = "rgmii-txid";
+ link = <&switch1port6
+ &switch2port9>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&mdio2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch1: switch1@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsa,member = <0 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan3";
+ phy-handle = <&switch1phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ phy-handle = <&switch1phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan5";
+ phy-handle = <&switch1phy2>;
+ };
+
+ switch1port5: port@5 {
+ reg = <5>;
+ label = "dsa";
+ link = <&switch2port9>;
+ phy-mode = "rgmii-txid";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch1port6: port@6 {
+ reg = <6>;
+ label = "dsa";
+ phy-mode = "rgmii-txid";
+ link = <&switch0port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ switch1phy0: switch1phy0@0 {
+ reg = <0>;
+ };
+ switch1phy1: switch1phy0@1 {
+ reg = <1>;
+ };
+ switch1phy2: switch1phy0@2 {
+ reg = <2>;
+ };
+ };
+ };
+};
+
+&mdio4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch2: switch2@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsa,member = <0 2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan6";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan7";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan8";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "optical3";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ link-gpios = <&gpio6 2
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "optical4";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ link-gpios = <&gpio6 3
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ switch2port9: port@9 {
+ reg = <9>;
+ label = "dsa";
+ phy-mode = "rgmii-txid";
+ link = <&switch1port5
+ &switch0port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+Deprecated Binding
+------------------
+
+The deprecated binding makes use of a platform device to represent the
+switches. The switches themselves are not Linux devices, and make use
+of an MDIO bus for management.
Required properties:
- compatible : Should be "marvell,dsa"
@@ -43,7 +317,7 @@ Each port children node must have the following mandatory properties:
Note that a port labelled "dsa" will imply checking for the uplink phandle
described below.
-Optionnal property:
+Optional property:
- link : Should be a list of phandles to another switch's DSA port.
This property is only used when switches are being
chained/cascaded together. This port is used as outgoing port
diff --git a/dts/Bindings/net/fsl-fec.txt b/dts/Bindings/net/fsl-fec.txt
index b037a9d..a1e3693 100644
--- a/dts/Bindings/net/fsl-fec.txt
+++ b/dts/Bindings/net/fsl-fec.txt
@@ -27,6 +27,9 @@ Optional properties:
number to 1.
- fsl,magic-packet : If present, indicates that the hardware supports waking
up via magic packet.
+- fsl,err006687-workaround-present: If present indicates that the system has
+ the hardware workaround for ERR006687 applied and does not need a software
+ workaround.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
diff --git a/dts/Bindings/net/hisilicon-femac-mdio.txt b/dts/Bindings/net/hisilicon-femac-mdio.txt
new file mode 100644
index 0000000..23a39a3
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-femac-mdio.txt
@@ -0,0 +1,22 @@
+Hisilicon Fast Ethernet MDIO Controller interface
+
+Required properties:
+- compatible: should be "hisilicon,hisi-femac-mdio".
+- reg: address and length of the register set for the device.
+- clocks: A phandle to the reference clock for this device.
+
+- PHY subnode: inherits from phy binding [1]
+[1] Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+mdio: mdio@10091100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x10091100 0x10>;
+ clocks = <&crg HI3516CV300_MDIO_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: phy@1 {
+ reg = <1>;
+ };
+};
diff --git a/dts/Bindings/net/hisilicon-femac.txt b/dts/Bindings/net/hisilicon-femac.txt
new file mode 100644
index 0000000..d11af5e
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-femac.txt
@@ -0,0 +1,39 @@
+Hisilicon Fast Ethernet MAC controller
+
+Required properties:
+- compatible: should contain one of the following version strings:
+ * "hisilicon,hisi-femac-v1"
+ * "hisilicon,hisi-femac-v2"
+ and the soc string "hisilicon,hi3516cv300-femac".
+- reg: specifies base physical address(s) and size of the device registers.
+ The first region is the MAC core register base and size.
+ The second region is the global MAC control register.
+- interrupts: should contain the MAC interrupt.
+- clocks: A phandle to the MAC main clock.
+- resets: should contain the phandle to the MAC reset signal(required) and
+ the PHY reset signal(optional).
+- reset-names: should contain the reset signal name "mac"(required)
+ and "phy"(optional).
+- mac-address: see ethernet.txt [1].
+- phy-mode: see ethernet.txt [1].
+- phy-handle: see ethernet.txt [1].
+- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
+
+[1] Documentation/devicetree/bindings/net/ethernet.txt
+
+Example:
+ hisi_femac: ethernet@10090000 {
+ compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
+ reg = <0x10090000 0x1000>,<0x10091300 0x200>;
+ interrupts = <12>;
+ clocks = <&crg HI3518EV200_ETH_CLK>;
+ resets = <&crg 0xec 0>,<&crg 0xec 3>;
+ reset-names = "mac","phy";
+ mac-address = [00 00 00 00 00 00];
+ phy-mode = "mii";
+ phy-handle = <&phy0>;
+ hisilicon,phy-reset-delays-us = <10000 20000 20000>;
+ };
diff --git a/dts/Bindings/net/keystone-netcp.txt b/dts/Bindings/net/keystone-netcp.txt
index b30ab6b..04ba1dc 100644
--- a/dts/Bindings/net/keystone-netcp.txt
+++ b/dts/Bindings/net/keystone-netcp.txt
@@ -2,7 +2,7 @@ This document describes the device tree bindings associated with the
keystone network coprocessor(NetCP) driver support.
The network coprocessor (NetCP) is a hardware accelerator that processes
-Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsytem with a ethernet
+Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
switch sub-module to send and receive packets. NetCP also includes a packet
accelerator (PA) module to perform packet classification operations such as
header matching, and packet modification operations such as checksum
diff --git a/dts/Bindings/net/mdio-mux.txt b/dts/Bindings/net/mdio-mux.txt
index 491f5bd..f58571f 100644
--- a/dts/Bindings/net/mdio-mux.txt
+++ b/dts/Bindings/net/mdio-mux.txt
@@ -5,11 +5,12 @@ numbered uniquely in a device dependent manner. The nodes for an MDIO
bus multiplexer/switch will have one child node for each child bus.
Required properties:
-- mdio-parent-bus : phandle to the parent MDIO bus.
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties:
+- mdio-parent-bus : phandle to the parent MDIO bus.
+
- Other properties specific to the multiplexer/switch hardware.
Required properties for child nodes:
diff --git a/dts/Bindings/net/micrel.txt b/dts/Bindings/net/micrel.txt
index 87496a8..8d157f0 100644
--- a/dts/Bindings/net/micrel.txt
+++ b/dts/Bindings/net/micrel.txt
@@ -35,3 +35,13 @@ Optional properties:
supported clocks:
- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
input clock. Used to determine the XI input clock.
+
+ - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
+
+ Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
+ by the FXEN boot strapping pin. It can't be determined from the PHY
+ registers whether the PHY is in fiber mode, so this boolean device tree
+ property can be used to describe it.
+
+ In fiber mode, auto-negotiation is disabled and the PHY can only work in
+ 100base-fx (full and half duplex) modes.
diff --git a/dts/Bindings/net/rockchip-dwmac.txt b/dts/Bindings/net/rockchip-dwmac.txt
index 93eac7c..cccd945 100644
--- a/dts/Bindings/net/rockchip-dwmac.txt
+++ b/dts/Bindings/net/rockchip-dwmac.txt
@@ -3,7 +3,8 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
The device node has following properties.
Required properties:
- - compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac"
+ - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
+ "rockchip,rk3368-gmac"
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
diff --git a/dts/Bindings/net/socfpga-dwmac.txt b/dts/Bindings/net/socfpga-dwmac.txt
index 72d82d6..2e68a3c 100644
--- a/dts/Bindings/net/socfpga-dwmac.txt
+++ b/dts/Bindings/net/socfpga-dwmac.txt
@@ -17,9 +17,26 @@ Required properties:
Optional properties:
altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
DWMAC controller is connected emac splitter.
+phy-mode: The phy mode the ethernet operates in
+altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
+
+This device node has additional phandle dependency, the sgmii converter:
+
+Required properties:
+ - compatible : Should be altr,gmii-to-sgmii-2.0
+ - reg-names : Should be "eth_tse_control_port"
Example:
+gmii_to_sgmii_converter: phy@0x100000240 {
+ compatible = "altr,gmii-to-sgmii-2.0";
+ reg = <0x00000001 0x00000240 0x00000008>,
+ <0x00000001 0x00000200 0x00000040>;
+ reg-names = "eth_tse_control_port";
+ clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
+ clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+};
+
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@@ -30,4 +47,6 @@ gmac0: ethernet@ff700000 {
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac_0_clk>;
clock-names = "stmmaceth";
+ phy-mode = "sgmii";
+ altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
};
diff --git a/dts/Bindings/net/stmmac.txt b/dts/Bindings/net/stmmac.txt
index 95816c5..41b49e6 100644
--- a/dts/Bindings/net/stmmac.txt
+++ b/dts/Bindings/net/stmmac.txt
@@ -47,6 +47,9 @@ Optional properties:
supported by this device instance
- snps,perfect-filter-entries: Number of perfect filter entries supported
by this device instance
+- snps,ps-speed: port selection speed that can be passed to the core when
+ PCS is supported. For example, this is used in case of SGMII
+ and MAC2MAC connection.
- AXI BUS Mode parameters: below the list of all the parameters to program the
AXI register inside the DMA module:
- snps,lpi_en: enable Low Power Interface
diff --git a/dts/Bindings/net/wireless/ti,wlcore,spi.txt b/dts/Bindings/net/wireless/ti,wlcore,spi.txt
index 9180724..8f9ced0 100644
--- a/dts/Bindings/net/wireless/ti,wlcore,spi.txt
+++ b/dts/Bindings/net/wireless/ti,wlcore,spi.txt
@@ -1,19 +1,30 @@
-* Texas Instruments wl1271 wireless lan controller
+* Texas Instruments wl12xx/wl18xx wireless lan controller
-The wl1271 chip can be connected via SPI or via SDIO. This
+The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This
document describes the binding for the SPI connected chip.
Required properties:
-- compatible : Should be "ti,wl1271"
+- compatible : Should be one of the following:
+ * "ti,wl1271"
+ * "ti,wl1273"
+ * "ti,wl1281"
+ * "ti,wl1283"
+ * "ti,wl1801"
+ * "ti,wl1805"
+ * "ti,wl1807"
+ * "ti,wl1831"
+ * "ti,wl1835"
+ * "ti,wl1837"
- reg : Chip select address of device
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
-- ref-clock-frequency : Reference clock frequency
- interrupt-parent, interrupts :
Should contain parameters for 1 interrupt line.
Interrupt parameters: parent, line number, type.
-- vwlan-supply : Point the node of the regulator that powers/enable the wl1271 chip
+- vwlan-supply : Point the node of the regulator that powers/enable the
+ wl12xx/wl18xx chip
Optional properties:
+- ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
- clock-xtal : boolean, clock is generated from XTAL
- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -21,16 +32,28 @@ Optional properties:
Examples:
+For wl12xx family:
&spi1 {
- wl1271@1 {
+ wlcore: wlcore@1 {
compatible = "ti,wl1271";
-
reg = <1>;
spi-max-frequency = <48000000>;
- clock-xtal;
- ref-clock-frequency = <38400000>;
interrupt-parent = <&gpio3>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
vwlan-supply = <&vwlan_fixed>;
+ clock-xtal;
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+For wl18xx family:
+&spi0 {
+ wlcore: wlcore@0 {
+ compatible = "ti,wl1835";
+ reg = <0>;
+ spi-max-frequency = <48000000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <27 IRQ_TYPE_EDGE_RISING>;
+ vwlan-supply = <&vwlan_fixed>;
};
};
diff --git a/dts/Bindings/pci/aardvark-pci.txt b/dts/Bindings/pci/aardvark-pci.txt
new file mode 100644
index 0000000..bbcd9f4
--- /dev/null
+++ b/dts/Bindings/pci/aardvark-pci.txt
@@ -0,0 +1,56 @@
+Aardvark PCIe controller
+
+This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
+
+The Device Tree node describing an Aardvark PCIe controller must
+contain the following properties:
+
+ - compatible: Should be "marvell,armada-3700-pcie"
+ - reg: range of registers for the PCIe controller
+ - interrupts: the interrupt line of the PCIe controller
+ - #address-cells: set to <3>
+ - #size-cells: set to <2>
+ - device_type: set to "pci"
+ - ranges: ranges for the PCI memory and I/O regions
+ - #interrupt-cells: set to <1>
+ - msi-controller: indicates that the PCIe controller can itself
+ handle MSI interrupts
+ - msi-parent: pointer to the MSI controller to be used
+ - interrupt-map-mask and interrupt-map: standard PCI properties to
+ define the mapping of the PCIe interface to interrupt numbers.
+ - bus-range: PCI bus numbers covered
+
+In addition, the Device Tree describing an Aardvark PCIe controller
+must include a sub-node that describes the legacy interrupt controller
+built into the PCIe controller. This sub-node must have the following
+properties:
+
+ - interrupt-controller
+ - #interrupt-cells: set to <1>
+
+Example:
+
+ pcie0: pcie@d0070000 {
+ compatible = "marvell,armada-3700-pcie";
+ device_type = "pci";
+ status = "disabled";
+ reg = <0 0xd0070000 0 0x20000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ msi-controller;
+ msi-parent = <&pcie0>;
+ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
+ 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/pci/axis,artpec6-pcie.txt b/dts/Bindings/pci/axis,artpec6-pcie.txt
new file mode 100644
index 0000000..330a45b
--- /dev/null
+++ b/dts/Bindings/pci/axis,artpec6-pcie.txt
@@ -0,0 +1,46 @@
+* Axis ARTPEC-6 PCIe interface
+
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- reg: base addresses and lengths of the PCIe controller (DBI),
+ the phy controller, and configuration address space.
+- reg-names: Must include the following entries:
+ - "dbi"
+ - "phy"
+ - "config"
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+ - "msi": The interrupt that is asserted when an MSI is received
+- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
+ used to enable and control the Synopsys IP.
+
+Example:
+
+ pcie@f8050000 {
+ compatible = "axis,artpec6-pcie", "snps,dw-pcie";
+ reg = <0xf8050000 0x2000
+ 0xf8040000 0x1000
+ 0xc0000000 0x1000>;
+ reg-names = "dbi", "phy", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ /* downstream I/O */
+ ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>;
+ num-lanes = <2>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ axis,syscon-pcie = <&syscon>;
+ };
diff --git a/dts/Bindings/pci/layerscape-pci.txt b/dts/Bindings/pci/layerscape-pci.txt
index ef683b2..41e9f55 100644
--- a/dts/Bindings/pci/layerscape-pci.txt
+++ b/dts/Bindings/pci/layerscape-pci.txt
@@ -24,6 +24,9 @@ Required properties:
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
This is used to get SCFG PEXN registers
+- dma-coherent: Indicates that the hardware IP block can ensure the coherency
+ of the data transferred from/to the IP block. This can avoid the software
+ cache flush/invalid actions, and improve the performance significantly.
Example:
@@ -38,6 +41,7 @@ Example:
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
diff --git a/dts/Bindings/phy/brcm,mdio-mux-bus-pci.txt b/dts/Bindings/phy/brcm,mdio-mux-bus-pci.txt
new file mode 100644
index 0000000..5b51007
--- /dev/null
+++ b/dts/Bindings/phy/brcm,mdio-mux-bus-pci.txt
@@ -0,0 +1,27 @@
+* Broadcom NS2 PCIe PHY binding document
+
+Required bus properties:
+- reg: MDIO Bus number for the MDIO interface
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required PHY properties:
+- compatible: should be "brcm,ns2-pcie-phy"
+- reg: MDIO Phy ID for the MDIO interface
+- #phy-cells: must be 0
+
+This is a child bus node of "brcm,mdio-mux-iproc" node.
+
+Example:
+
+mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pci_phy0: pci-phy@0 {
+ compatible = "brcm,ns2-pcie-phy";
+ reg = <0x0>;
+ #phy-cells = <0>;
+ };
+};
diff --git a/dts/Bindings/phy/brcm-sata-phy.txt b/dts/Bindings/phy/brcm-sata-phy.txt
index d023120..6ccce09 100644
--- a/dts/Bindings/phy/brcm-sata-phy.txt
+++ b/dts/Bindings/phy/brcm-sata-phy.txt
@@ -5,6 +5,7 @@ Required properties:
"brcm,bcm7425-sata-phy"
"brcm,bcm7445-sata-phy"
"brcm,iproc-ns2-sata-phy"
+ "brcm,iproc-nsp-sata-phy"
"brcm,phy-sata3"
- address-cells: should be 1
- size-cells: should be 0
@@ -22,7 +23,8 @@ Sub-nodes required properties:
Sub-nodes optional properties:
- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
- This property is not applicable for "brcm,iproc-ns2-sata-phy".
+ This property is not applicable for "brcm,iproc-ns2-sata-phy" and
+ "brcm,iproc-nsp-sata-phy".
Example:
sata-phy@f0458100 {
diff --git a/dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt b/dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt
index 0bf1ae2..3742c15 100644
--- a/dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt
+++ b/dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt
@@ -124,7 +124,7 @@ For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
- functions: "usb3-ss", "sata"
For Tegra210, the list of valid PHY nodes is given below:
-- utmi: utmi-0, utmi-1, utmi-2, utmi-3
+- usb2: usb2-0, usb2-1, usb2-2, usb2-3
- functions: "snps", "xusb", "uart"
- hsic: hsic-0, hsic-1
- functions: "snps", "xusb"
diff --git a/dts/Bindings/phy/phy-da8xx-usb.txt b/dts/Bindings/phy/phy-da8xx-usb.txt
new file mode 100644
index 0000000..c26478b
--- /dev/null
+++ b/dts/Bindings/phy/phy-da8xx-usb.txt
@@ -0,0 +1,40 @@
+TI DA8xx/OMAP-L1xx/AM18xx USB PHY
+
+Required properties:
+ - compatible: must be "ti,da830-usb-phy".
+ - #phy-cells: must be 1.
+
+This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
+controllers on DA8xx SoCs. Consumers of this device should use index 0 for
+the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
+
+It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
+to access the CFGCHIP2 register.
+
+Example:
+
+ cfgchip: cfgchip@1417c {
+ compatible = "ti,da830-cfgchip", "syscon";
+ reg = <0x1417c 0x14>;
+ };
+
+ usb_phy: usb-phy {
+ compatible = "ti,da830-usb-phy";
+ #phy-cells = <1>;
+ };
+
+ usb20: usb@200000 {
+ compatible = "ti,da830-musb";
+ reg = <0x200000 0x1000>;
+ interrupts = <58>;
+ phys = <&usb_phy 0>;
+ phy-names = "usb-phy";
+ };
+
+ usb11: usb@225000 {
+ compatible = "ti,da830-ohci";
+ reg = <0x225000 0x1000>;
+ interrupts = <59>;
+ phys = <&usb_phy 1>;
+ phy-names = "usb-phy";
+ };
diff --git a/dts/Bindings/phy/rockchip-emmc-phy.txt b/dts/Bindings/phy/rockchip-emmc-phy.txt
index 555cb0f..e3ea557 100644
--- a/dts/Bindings/phy/rockchip-emmc-phy.txt
+++ b/dts/Bindings/phy/rockchip-emmc-phy.txt
@@ -7,6 +7,13 @@ Required properties:
- reg: PHY register address offset and length in "general
register files"
+Optional clocks using the clock bindings (see ../clock/clock-bindings.txt),
+specified by name:
+ - clock-names: Should contain "emmcclk". Although this is listed as optional
+ (because most boards can get basic functionality without having
+ access to it), it is strongly suggested.
+ - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
+
Example:
@@ -20,6 +27,8 @@ grf: syscon@ff770000 {
emmcphy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x20>;
+ clocks = <&sdhci>;
+ clock-names = "emmcclk";
#phy-cells = <0>;
};
};
diff --git a/dts/Bindings/phy/rockchip-usb-phy.txt b/dts/Bindings/phy/rockchip-usb-phy.txt
index 68498d5..cc6be96 100644
--- a/dts/Bindings/phy/rockchip-usb-phy.txt
+++ b/dts/Bindings/phy/rockchip-usb-phy.txt
@@ -5,11 +5,13 @@ Required properties:
"rockchip,rk3066a-usb-phy"
"rockchip,rk3188-usb-phy"
"rockchip,rk3288-usb-phy"
- - rockchip,grf : phandle to the syscon managing the "general
- register files"
- #address-cells: should be 1
- #size-cells: should be 0
+Deprecated properties:
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files" - phy should be a child of the GRF instead
+
Sub-nodes:
Each PHY should be represented as a sub-node.
@@ -28,14 +30,19 @@ Optional Properties:
Example:
-usbphy: phy {
- compatible = "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
+
+...
+
+ usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
- usbphy0: usb-phy0 {
- #phy-cells = <0>;
- reg = <0x320>;
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ reg = <0x320>;
+ };
};
};
diff --git a/dts/Bindings/pinctrl/brcm,iproc-gpio.txt b/dts/Bindings/pinctrl/brcm,iproc-gpio.txt
index e427792..a73cbeb 100644
--- a/dts/Bindings/pinctrl/brcm,iproc-gpio.txt
+++ b/dts/Bindings/pinctrl/brcm,iproc-gpio.txt
@@ -3,8 +3,22 @@ Broadcom iProc GPIO/PINCONF Controller
Required properties:
- compatible:
- Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio",
- "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
+ "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
+ supports full-featured pinctrl and GPIO functions used in various iProc
+ based SoCs
+
+ May contain an SoC-specific compatibility string to accommodate any
+ SoC-specific features
+
+ "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
+ "brcm,cygnus-crmu-gpio" for Cygnus SoCs
+
+ "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
+ disabled
+
+ "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
+ pinctrl support completely disabled in this IP block. In Stingray, a
+ different IP block is used to handle pinctrl related functions
- reg:
Define the base and range of the I/O address space that contains SoC
diff --git a/dts/Bindings/pinctrl/brcm,nsp-pinmux.txt b/dts/Bindings/pinctrl/brcm,nsp-pinmux.txt
new file mode 100644
index 0000000..603564e
--- /dev/null
+++ b/dts/Bindings/pinctrl/brcm,nsp-pinmux.txt
@@ -0,0 +1,79 @@
+Broadcom NSP (Northstar plus) IOMUX Controller
+
+The NSP IOMUX controller supports group based mux configuration. In
+addition, certain pins can be muxed to GPIO function individually.
+
+Required properties:
+- compatible:
+ Must be "brcm,nsp-pinmux"
+
+- reg:
+ Should contain the register physical address and length for each of
+ GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers
+
+Properties in subnodes:
+- function:
+ The mux function to select
+
+- groups:
+ The list of groups to select with a given function
+
+For more details, refer to
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+For example:
+
+ pinmux: pinmux@1803f1c0 {
+ compatible = "brcm,nsp-pinmux";
+ reg = <0x1803f1c0 0x04>,
+ <0x18030028 0x04>,
+ <0x1803f408 0x04>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm &gpio_b &nand_sel>;
+
+ pwm: pwm {
+ function = "pwm";
+ groups = "pwm0_grp", "pwm1_grp";
+ };
+
+ gpio_b: gpio_b {
+ function = "gpio_b";
+ groups = "gpio_b_0_grp", "gpio_b_1_grp";
+ };
+
+ nand_sel: nand_sel {
+ function = "nand";
+ groups = "nand_grp";
+ };
+ };
+
+List of supported functions and groups in Northstar Plus:
+
+"spi": "spi_grp"
+
+"i2c": "i2c_grp"
+
+"mdio": "mdio_grp"
+
+"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
+
+"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp"
+
+"uart1": "uart1_grp"
+
+"uart2": "uart2_grp"
+
+"synce": "synce_grp"
+
+"sata_led_grps": "sata0_led_grp", "sata1_led_grp"
+
+"xtal_out": "xtal_out_grp"
+
+"sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
+
+"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp"
+
+"nand": "nand_grp"
+
+"emmc": "emmc_grp"
diff --git a/dts/Bindings/pinctrl/meson,pinctrl.txt b/dts/Bindings/pinctrl/meson,pinctrl.txt
index 32f4a2d..fe7fe0b 100644
--- a/dts/Bindings/pinctrl/meson,pinctrl.txt
+++ b/dts/Bindings/pinctrl/meson,pinctrl.txt
@@ -5,6 +5,8 @@ Required properties for the root node:
"amlogic,meson8b-cbus-pinctrl"
"amlogic,meson8-aobus-pinctrl"
"amlogic,meson8b-aobus-pinctrl"
+ "amlogic,meson-gxbb-periphs-pinctrl"
+ "amlogic,meson-gxbb-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===
diff --git a/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
new file mode 100644
index 0000000..f2abdae
--- /dev/null
+++ b/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
@@ -0,0 +1,60 @@
+Device tree binding for NVIDIA Tegra DPAUX pad controller
+========================================================
+
+The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
+which can be assigned to either the DPAUX channel or to an I2C
+controller.
+
+This document defines the device-specific binding for the DPAUX pad
+controller. Refer to pinctrl-bindings.txt in this directory for generic
+information about pin controller device tree bindings. Please refer to
+the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
+details on the DPAUX binding.
+
+Pin muxing:
+-----------
+
+Child nodes contain the pinmux configurations following the conventions
+from the pinctrl-bindings.txt document.
+
+Since only three configurations are possible, only three child nodes are
+needed to describe the pin mux'ing options for the DPAUX pads.
+Furthermore, given that the pad functions are only applicable to a
+single set of pads, the child nodes only need to describe the pad group
+the functions are being applied to rather than the individual pads.
+
+Required properties:
+- groups: Must be "dpaux-io"
+- function: Must be either "aux", "i2c" or "off".
+
+Example:
+--------
+
+ dpaux@545c0000 {
+ ...
+
+ state_dpaux_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+ };
+
+ ...
+
+ i2c@7000d100 {
+ ...
+ pinctrl-0 = <&state_dpaux_i2c>;
+ pinctrl-1 = <&state_dpaux_off>;
+ pinctrl-names = "default", "idle";
+ status = "disabled";
+ };
diff --git a/dts/Bindings/pinctrl/oxnas,pinctrl.txt b/dts/Bindings/pinctrl/oxnas,pinctrl.txt
new file mode 100644
index 0000000..d607432
--- /dev/null
+++ b/dts/Bindings/pinctrl/oxnas,pinctrl.txt
@@ -0,0 +1,57 @@
+* Oxford Semiconductor OXNAS SoC Family Pin Controller
+
+Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
+../interrupt-controller/interrupts.txt for generic information regarding
+pin controller, GPIO, and interrupt bindings.
+
+OXNAS 'pin configuration node' is a node of a group of pins which can be
+used for a specific device or function. This node represents configurations of
+pins, optional function, and optional mux related configuration.
+
+Required properties for pin controller node:
+ - compatible: "oxsemi,ox810se-pinctrl"
+ - oxsemi,sys-ctrl: a phandle to the system controller syscon node
+
+Required properties for pin configuration sub-nodes:
+ - pins: List of pins to which the configuration applies.
+
+Optional properties for pin configuration sub-nodes:
+----------------------------------------------------
+ - function: Mux function for the specified pins.
+ - bias-pull-up: Enable weak pull-up.
+
+Example:
+
+pinctrl: pinctrl {
+ compatible = "oxsemi,ox810se-pinctrl";
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ pinctrl_uart2: pinctrl_uart2 {
+ uart2a {
+ pins = "gpio31";
+ function = "fct3";
+ };
+ uart2b {
+ pins = "gpio32";
+ function = "fct3";
+ };
+ };
+};
+
+uart2: serial@900000 {
+ compatible = "ns16550a";
+ reg = <0x900000 0x100000>;
+ clocks = <&sysclk>;
+ interrupts = <29>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ resets = <&reset 22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
diff --git a/dts/Bindings/pinctrl/pinctrl-max77620.txt b/dts/Bindings/pinctrl/pinctrl-max77620.txt
new file mode 100644
index 0000000..ad4fce3
--- /dev/null
+++ b/dts/Bindings/pinctrl/pinctrl-max77620.txt
@@ -0,0 +1,127 @@
+Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
+
+Device has 8 GPIO pins which can be configured as GPIO as well as the
+special IO functions.
+
+Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
+for details of the common pinctrl bindings used by client devices,
+including the meaning of the phrase "pin configuration node".
+
+Optional Pinmux properties:
+--------------------------
+Following properties are required if default setting of pins are required
+at boot.
+- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
+ <pinctrl-binding.txt>.
+
+The pin configurations are defined as child of the pinctrl states node. Each
+sub-node have following properties:
+
+Required properties:
+------------------
+- pins: List of pins. Valid values of pins properties are:
+ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.
+
+Optional properties:
+-------------------
+Following are optional properties defined as pinmux DT binding document
+<pinctrl-bindings.txt>. Absence of properties will leave the configuration
+on default.
+ function,
+ drive-push-pull,
+ drive-open-drain,
+ bias-pull-up,
+ bias-pull-down.
+
+Valid values for function properties are:
+ gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
+ reference-out
+
+Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These
+customised properties are required to configure FPS configuration parameters
+of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
+detail of Flexible Power Sequence (FPS).
+
+- maxim,active-fps-source: FPS source for the GPIOs to get
+ enabled/disabled when system is in
+ active state. Valid values are:
+ - MAX77620_FPS_SRC_0,
+ FPS source is FPS0.
+ - MAX77620_FPS_SRC_1,
+ FPS source is FPS1
+ - MAX77620_FPS_SRC_2 and
+ FPS source is FPS2
+ - MAX77620_FPS_SRC_NONE.
+ GPIO is not controlled
+ by FPS events and it gets
+ enabled/disabled by register
+ access.
+ Absence of this property will leave
+ the FPS configuration register for that
+ GPIO to default configuration.
+
+- maxim,active-fps-power-up-slot: Sequencing event slot number on which
+ the GPIO get enabled when
+ master FPS input event set to HIGH.
+ Valid values are 0 to 7.
+ This is applicable if FPS source is
+ selected as FPS0, FPS1 or FPS2.
+
+- maxim,active-fps-power-down-slot: Sequencing event slot number on which
+ the GPIO get disabled when master
+ FPS input event set to LOW.
+ Valid values are 0 to 7.
+ This is applicable if FPS source is
+ selected as FPS0, FPS1 or FPS2.
+
+- maxim,suspend-fps-source: This is same as property
+ "maxim,active-fps-source" but value
+ get configured when system enters in
+ to suspend state.
+
+- maxim,suspend-fps-power-up-slot: This is same as property
+ "maxim,active-fps-power-up-slot" but
+ this value get configured into FPS
+ configuration register when system
+ enters into suspend.
+ This is applicable if suspend state
+ FPS source is selected as FPS0, FPS1 or
+
+- maxim,suspend-fps-power-down-slot: This is same as property
+ "maxim,active-fps-power-down-slot" but
+ this value get configured into FPS
+ configuration register when system
+ enters into suspend.
+ This is applicable if suspend state
+ FPS source is selected as FPS0, FPS1 or
+ FPS2.
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spmic_default>;
+
+ spmic_default: pinmux@0 {
+ pin_gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ pin_gpio1 {
+ pins = "gpio1";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+ };
+
+ pin_gpio2 {
+ pins = "gpio2";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+ };
+ };
+};
diff --git a/dts/Bindings/pinctrl/qcom,mdm9615-pinctrl.txt b/dts/Bindings/pinctrl/qcom,mdm9615-pinctrl.txt
new file mode 100644
index 0000000..1b52f01
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,mdm9615-pinctrl.txt
@@ -0,0 +1,152 @@
+Qualcomm MDM9615 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+MDM9615 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,mdm9615-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode. Valid pins are:
+ gpio0-gpio87
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins.
+ Valid values are:
+ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
+ sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio,
+ cdc_mclk
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ msmgpio: pinctrl@800000 {
+ compatible = "qcom,mdm9615-pinctrl";
+ reg = <0x800000 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 16 0x4>;
+
+ gsbi8_uart: gsbi8-uart {
+ mux {
+ pins = "gpio34", "gpio35";
+ function = "gsbi8";
+ };
+
+ tx {
+ pins = "gpio34";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio35";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
diff --git a/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt b/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt
index 77aa117..df9a838 100644
--- a/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt
@@ -52,7 +52,7 @@ Valid values for function are:
gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
- usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm,
+ usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs
Example:
diff --git a/dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt b/dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt
index e4d6a9d..453bd7c 100644
--- a/dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt
@@ -49,6 +49,9 @@ Valid values for pins are:
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
Supports bias and drive-strength
+ hsic_data, hsic_strobe
+ Supports only mux
+
Valid values for function are:
cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
@@ -70,7 +73,7 @@ Valid values for function are:
cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
- ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio
+ ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio
(Note that this is not yet the complete list of functions)
diff --git a/dts/Bindings/pinctrl/qcom,pmic-mpp.txt b/dts/Bindings/pinctrl/qcom,pmic-mpp.txt
index d74e631..b484ba1 100644
--- a/dts/Bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/dts/Bindings/pinctrl/qcom,pmic-mpp.txt
@@ -9,6 +9,7 @@ of PMIC's from Qualcomm.
Definition: Should contain one of:
"qcom,pm8018-mpp",
"qcom,pm8038-mpp",
+ "qcom,pm8058-mpp",
"qcom,pm8821-mpp",
"qcom,pm8841-mpp",
"qcom,pm8916-mpp",
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 74e6ec0..e4cf022 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -72,7 +72,7 @@ Pin Configuration Node Properties:
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
-bias-disable, bias-pull-up, bias-pull-down, drive strength and power-source. For
+bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
pins that have a configurable I/O voltage, the power-source value should be the
nominal I/O voltage in millivolts.
diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
index 7b4800c..587bffb 100644
--- a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
@@ -9,6 +9,7 @@ Pin controller node:
Required properies:
- compatible: value should be one of the following:
(a) "st,stm32f429-pinctrl"
+ (b) "st,stm32f746-pinctrl"
- #address-cells: The value of this property must be 1
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
diff --git a/dts/Bindings/power/max8903-charger.txt b/dts/Bindings/power/max8903-charger.txt
new file mode 100644
index 0000000..f0f4e12
--- /dev/null
+++ b/dts/Bindings/power/max8903-charger.txt
@@ -0,0 +1,25 @@
+Maxim Semiconductor MAX8903 Battery Charger bindings
+
+Required properties:
+- compatible: "maxim,max8903" for MAX8903 Battery Charger
+- dok-gpios: Valid DC power has been detected (active low, input), optional if uok-gpios is provided
+- uok-gpios: Valid USB power has been detected (active low, input), optional if dok-gpios is provided
+
+Optional properties:
+- cen-gpios: Charge enable pin (active low, output)
+- chg-gpios: Charger status pin (active low, input)
+- flt-gpios: Fault pin (active low, output)
+- dcm-gpios: Current limit mode setting (DC=1 or USB=0, output)
+- usus-gpios: USB suspend pin (active high, output)
+
+
+Example:
+
+ max8903-charger {
+ compatible = "maxim,max8903";
+ dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ flt-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ chg-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ cen-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
diff --git a/dts/Bindings/power/renesas,apmu.txt b/dts/Bindings/power/renesas,apmu.txt
new file mode 100644
index 0000000..84404c9
--- /dev/null
+++ b/dts/Bindings/power/renesas,apmu.txt
@@ -0,0 +1,31 @@
+DT bindings for the Renesas Advanced Power Management Unit
+
+Renesas R-Car line of SoCs utilize one or more APMU hardware units
+for CPU core power domain control including SMP boot and CPU Hotplug.
+
+Required properties:
+
+- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
+ Examples with soctypes are:
+ - "renesas,r8a7790-apmu" (R-Car H2)
+ - "renesas,r8a7791-apmu" (R-Car M2-W)
+ - "renesas,r8a7792-apmu" (R-Car V2H)
+ - "renesas,r8a7793-apmu" (R-Car M2-N)
+ - "renesas,r8a7794-apmu" (R-Car E2)
+
+- reg: Base address and length of the I/O registers used by the APMU.
+
+- cpus: This node contains a list of CPU cores, which should match the order
+ of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
+ Management Unit section of the device's datasheet.
+
+
+Example:
+
+This shows the r8a7791 APMU that can control CPU0 and CPU1.
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
diff --git a/dts/Bindings/power/renesas,rcar-sysc.txt b/dts/Bindings/power/renesas,rcar-sysc.txt
index b74e4d4..0725fb3 100644
--- a/dts/Bindings/power/renesas,rcar-sysc.txt
+++ b/dts/Bindings/power/renesas,rcar-sysc.txt
@@ -14,6 +14,7 @@ Required properties:
- "renesas,r8a7793-sysc" (R-Car M2-N)
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
+ - "renesas,r8a7796-sysc" (R-Car M3-W)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/dts/Bindings/reset/brcm,bcm21664-resetmgr.txt b/dts/Bindings/power/reset/brcm,bcm21664-resetmgr.txt
index 93f31ca..93f31ca 100644
--- a/dts/Bindings/reset/brcm,bcm21664-resetmgr.txt
+++ b/dts/Bindings/power/reset/brcm,bcm21664-resetmgr.txt
diff --git a/dts/Bindings/power/reset/reboot-mode.txt b/dts/Bindings/power/reset/reboot-mode.txt
new file mode 100644
index 0000000..de34f27
--- /dev/null
+++ b/dts/Bindings/power/reset/reboot-mode.txt
@@ -0,0 +1,25 @@
+Generic reboot mode core map driver
+
+This driver get reboot mode arguments and call the write
+interface to store the magic value in special register
+or ram. Then the bootloader can read it and take different
+action according to the argument stored.
+
+All mode properties are vendor specific, it is a indication to tell
+the bootloader what to do when the system reboots, and should be named
+as mode-xxx = <magic> (xxx is mode name, magic should be a none-zero value).
+
+For example modes common on Android platform:
+- mode-normal: Normal reboot mode, system reboot with command "reboot".
+- mode-recovery: Android Recovery mode, it is a mode to format the device or update a new image.
+- mode-bootloader: Android fastboot mode, it's a mode to re-flash partitions on the Android based device.
+- mode-loader: A bootloader mode, it's a mode used to download image on Rockchip platform,
+ usually used in development.
+
+Example:
+ reboot-mode {
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ }
diff --git a/dts/Bindings/power/reset/syscon-reboot-mode.txt b/dts/Bindings/power/reset/syscon-reboot-mode.txt
new file mode 100644
index 0000000..f7ce1d8
--- /dev/null
+++ b/dts/Bindings/power/reset/syscon-reboot-mode.txt
@@ -0,0 +1,35 @@
+SYSCON reboot mode driver
+
+This driver gets reboot mode magic value form reboot-mode driver
+and stores it in a SYSCON mapped register. Then the bootloader
+can read it and take different action according to the magic
+value stored.
+
+This DT node should be represented as a sub-node of a "syscon", "simple-mfd"
+node.
+
+Required properties:
+- compatible: should be "syscon-reboot-mode"
+- offset: offset in the register map for the storage register (in bytes)
+
+Optional property:
+- mask: bits mask of the bits in the register to store the reboot mode magic value,
+ default set to 0xffffffff if missing.
+
+The rest of the properties should follow the generic reboot-mode description
+found in reboot-mode.txt
+
+Example:
+ pmu: pmu@20004000 {
+ compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
+ reg = <0x20004000 0x100>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x40>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
+ };
diff --git a/dts/Bindings/power_supply/axp20x_usb_power.txt b/dts/Bindings/power_supply/axp20x_usb_power.txt
index 862f4a4..f1d7bee 100644
--- a/dts/Bindings/power_supply/axp20x_usb_power.txt
+++ b/dts/Bindings/power_supply/axp20x_usb_power.txt
@@ -1,7 +1,8 @@
AXP20x USB power supply
Required Properties:
--compatible: "x-powers,axp202-usb-power-supply"
+-compatible: One of: "x-powers,axp202-usb-power-supply"
+ "x-powers,axp221-usb-power-supply"
This node is a subnode of the axp20x PMIC.
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/network.txt b/dts/Bindings/powerpc/fsl/cpm_qe/network.txt
deleted file mode 100644
index 29b28b8..0000000
--- a/dts/Bindings/powerpc/fsl/cpm_qe/network.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-* Network
-
-Currently defined compatibles:
-- fsl,cpm1-scc-enet
-- fsl,cpm2-scc-enet
-- fsl,cpm1-fec-enet
-- fsl,cpm2-fcc-enet (third resource is GFEMR)
-- fsl,qe-enet
-
-Example:
-
- ethernet@11300 {
- compatible = "fsl,mpc8272-fcc-enet",
- "fsl,cpm2-fcc-enet";
- reg = <11300 20 8400 100 11390 1>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <20 8>;
- interrupt-parent = <&PIC>;
- phy-handle = <&PHY0>;
- fsl,cpm-command = <12000300>;
- };
-
-* MDIO
-
-Currently defined compatibles:
-fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
-fsl,cpm2-mdio-bitbang (reg is port C registers)
-
-Properties for fsl,cpm2-mdio-bitbang:
-fsl,mdio-pin : pin of port C controlling mdio data
-fsl,mdc-pin : pin of port C controlling mdio clock
-
-Example:
- mdio@10d40 {
- compatible = "fsl,mpc8272ads-mdio-bitbang",
- "fsl,mpc8272-mdio-bitbang",
- "fsl,cpm2-mdio-bitbang";
- reg = <10d40 14>;
- #address-cells = <1>;
- #size-cells = <0>;
- fsl,mdio-pin = <12>;
- fsl,mdc-pin = <13>;
- };
diff --git a/dts/Bindings/powerpc/fsl/fman.txt b/dts/Bindings/powerpc/fsl/fman.txt
index 55c2c03..df873d1 100644
--- a/dts/Bindings/powerpc/fsl/fman.txt
+++ b/dts/Bindings/powerpc/fsl/fman.txt
@@ -35,7 +35,7 @@ PROPERTIES
Definition: Specifies the index of the FMan unit.
The cell-index value may be used by the SoC, to identify the
- FMan unit in the SoC memory map. In the table bellow,
+ FMan unit in the SoC memory map. In the table below,
there's a description of the cell-index use in each SoC:
- P1023:
@@ -247,7 +247,7 @@ PROPERTIES
The cell-index value may be used by the FMan or the SoC, to
identify the MAC unit in the FMan (or SoC) memory map.
- In the tables bellow there's a description of the cell-index
+ In the tables below there's a description of the cell-index
use, there are two tables, one describes the use of cell-index
by the FMan, the second describes the use by the SoC:
diff --git a/dts/Bindings/powerpc/opal/oppanel-opal.txt b/dts/Bindings/powerpc/opal/oppanel-opal.txt
new file mode 100644
index 0000000..dffb791
--- /dev/null
+++ b/dts/Bindings/powerpc/opal/oppanel-opal.txt
@@ -0,0 +1,14 @@
+IBM OPAL Operator Panel Binding
+-------------------------------
+
+Required properties:
+- compatible : Should be "ibm,opal-oppanel".
+- #lines : Number of lines on the operator panel e.g. <0x2>.
+- #length : Number of characters per line of the operator panel e.g. <0x10>.
+
+Example:
+ oppanel {
+ compatible = "ibm,opal-oppanel";
+ #lines = <0x2>;
+ #length = <0x10>;
+ };
diff --git a/dts/Bindings/pwm/brcm,iproc-pwm.txt b/dts/Bindings/pwm/brcm,iproc-pwm.txt
new file mode 100644
index 0000000..21f75bb
--- /dev/null
+++ b/dts/Bindings/pwm/brcm,iproc-pwm.txt
@@ -0,0 +1,21 @@
+Broadcom iProc PWM controller device tree bindings
+
+This controller has 4 channels.
+
+Required Properties :
+- compatible: must be "brcm,iproc-pwm"
+- reg: physical base address and length of the controller's registers
+- clocks: phandle + clock specifier pair for the external clock
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a
+ description of the cells format.
+
+Refer to clocks/clock-bindings.txt for generic clock consumer properties.
+
+Example:
+
+pwm: pwm@18031000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x18031000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+};
diff --git a/dts/Bindings/pwm/cirrus,clps711x-pwm.txt b/dts/Bindings/pwm/cirrus,clps711x-pwm.txt
index a183db4..c0b2028 100644
--- a/dts/Bindings/pwm/cirrus,clps711x-pwm.txt
+++ b/dts/Bindings/pwm/cirrus,clps711x-pwm.txt
@@ -1,15 +1,14 @@
* Cirris Logic CLPS711X PWM controller
Required properties:
-- compatible: Shall contain "cirrus,clps711x-pwm".
+- compatible: Shall contain "cirrus,ep7209-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks: phandle + clock specifier pair of the PWM reference clock.
- #pwm-cells: Should be 1. The cell specifies the index of the channel.
Example:
pwm: pwm@80000400 {
- compatible = "cirrus,ep7312-pwm",
- "cirrus,clps711x-pwm";
+ compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
reg = <0x80000400 0x4>;
clocks = <&clks 8>;
#pwm-cells = <1>;
diff --git a/dts/Bindings/pwm/google,cros-ec-pwm.txt b/dts/Bindings/pwm/google,cros-ec-pwm.txt
new file mode 100644
index 0000000..472bd46
--- /dev/null
+++ b/dts/Bindings/pwm/google,cros-ec-pwm.txt
@@ -0,0 +1,23 @@
+* PWM controlled by ChromeOS EC
+
+Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller
+(EC) and controlled via a host-command interface.
+
+An EC PWM node should be only found as a sub-node of the EC node (see
+Documentation/devicetree/bindings/mfd/cros-ec.txt).
+
+Required properties:
+- compatible: Must contain "google,cros-ec-pwm"
+- #pwm-cells: Should be 1. The cell specifies the PWM index.
+
+Example:
+ cros-ec@0 {
+ compatible = "google,cros-ec-spi";
+
+ ...
+
+ cros_ec_pwm: ec-pwm {
+ compatible = "google,cros-ec-pwm";
+ #pwm-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/pwm/nvidia,tegra20-pwm.txt b/dts/Bindings/pwm/nvidia,tegra20-pwm.txt
index c52f03b..b4e7377 100644
--- a/dts/Bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/dts/Bindings/pwm/nvidia,tegra20-pwm.txt
@@ -1,10 +1,14 @@
Tegra SoC PWFM controller
Required properties:
-- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30,
- must contain "nvidia,tegra30-pwm". Otherwise, must contain
- "nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
- tegra124, tegra132, or tegra210.
+- compatible: Must be:
+ - "nvidia,tegra20-pwm": for Tegra20
+ - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
+ - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
+ - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
+ - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
+ - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
+ - "nvidia,tegra186-pwm": for Tegra186
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
the cells format.
diff --git a/dts/Bindings/pwm/pwm-omap-dmtimer.txt b/dts/Bindings/pwm/pwm-omap-dmtimer.txt
index 5befb53..2e53324 100644
--- a/dts/Bindings/pwm/pwm-omap-dmtimer.txt
+++ b/dts/Bindings/pwm/pwm-omap-dmtimer.txt
@@ -9,6 +9,10 @@ Required properties:
Optional properties:
- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
+- ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
+ - 0x00 - high-frequency system clock (timer_sys_ck)
+ - 0x01 - 32-kHz always-on clock (timer_32k_ck)
+ - 0x02 - external clock (timer_ext_ck, OMAP2 only)
Example:
pwm9: dmtimer-pwm@9 {
diff --git a/dts/Bindings/pwm/pwm-tiecap.txt b/dts/Bindings/pwm/pwm-tiecap.txt
index fb81179..8007e83 100644
--- a/dts/Bindings/pwm/pwm-tiecap.txt
+++ b/dts/Bindings/pwm/pwm-tiecap.txt
@@ -2,28 +2,48 @@ TI SOC ECAP based APWM controller
Required properties:
- compatible: Must be "ti,<soc>-ecap".
- for am33xx - compatible = "ti,am33xx-ecap";
- for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap";
+ for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
+ for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
+ for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
+ for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The PWM channel index ranges from 0 to 4. The only third
cell flag supported by this binding is PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.
Optional properties:
-- ti,hwmods: Name of the hwmod associated to the ECAP:
- "ecap<x>", <x> being the 0-based instance number from the HW spec
+- clocks: Handle to the ECAP's functional clock.
+- clock-names: Must be set to "fck".
Example:
-ecap0: ecap@0 { /* ECAP on am33xx */
- compatible = "ti,am33xx-ecap";
+ecap0: ecap@48300100 { /* ECAP on am33xx */
+ compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48300100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+};
+
+ecap0: ecap@48300100 { /* ECAP on am4372 */
+ compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
ti,hwmods = "ecap0";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+};
+
+ecap0: ecap@1f06000 { /* ECAP on da850 */
+ compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x1f06000 0x80>;
};
-ecap0: ecap@0 { /* ECAP on da850 */
- compatible = "ti,da850-ecap", "ti,am33xx-ecap";
+ecap0: ecap@4843e100 {
+ compatible = "ti,dra746-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
- reg = <0x306000 0x80>;
+ reg = <0x4843e100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
};
diff --git a/dts/Bindings/pwm/pwm-tiehrpwm.txt b/dts/Bindings/pwm/pwm-tiehrpwm.txt
index 9c100b2..944fe35 100644
--- a/dts/Bindings/pwm/pwm-tiehrpwm.txt
+++ b/dts/Bindings/pwm/pwm-tiehrpwm.txt
@@ -2,28 +2,48 @@ TI SOC EHRPWM based PWM controller
Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
- for am33xx - compatible = "ti,am33xx-ehrpwm";
- for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
+ for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
+ for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
+ for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.
Optional properties:
-- ti,hwmods: Name of the hwmod associated to the EHRPWM:
- "ehrpwm<x>", <x> being the 0-based instance number from the HW spec
+- clocks: Handle to the PWM's time-base and functional clock.
+- clock-names: Must be set to "tbclk" and "fck".
Example:
-ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */
- compatible = "ti,am33xx-ehrpwm";
+ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
+ compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x100>;
+ clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+};
+
+ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
+ compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48300200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
ti,hwmods = "ehrpwm0";
};
-ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */
- compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
+ compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x1f00000 0x2000>;
+};
+
+ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
+ compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
- reg = <0x300000 0x2000>;
+ reg = <0x4843e200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
};
diff --git a/dts/Bindings/pwm/pwm-tipwmss.txt b/dts/Bindings/pwm/pwm-tipwmss.txt
index f7eae77..1a5d7b7 100644
--- a/dts/Bindings/pwm/pwm-tipwmss.txt
+++ b/dts/Bindings/pwm/pwm-tipwmss.txt
@@ -1,7 +1,11 @@
TI SOC based PWM Subsystem
Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
+- compatible: Must be "ti,<soc>-pwmss".
+ for am33xx - compatible = "ti,am33xx-pwmss";
+ for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
+
- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
Should set to 1.
@@ -16,7 +20,7 @@ Required properties:
Also child nodes should also populated under PWMSS DT node.
Example:
-pwmss0: pwmss@48300000 {
+epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
@@ -29,3 +33,28 @@ pwmss0: pwmss@48300000 {
/* child nodes go here */
};
+
+epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"
+ reg = <0x48300000 0x10>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48300100 0x48300100 0x80 /* ECAP */
+ 0x48300180 0x48300180 0x80 /* EQEP */
+ 0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+ /* child nodes go here */
+};
+
+epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* child nodes go here */
+};
diff --git a/dts/Bindings/pwm/renesas,pwm-rcar.txt b/dts/Bindings/pwm/renesas,pwm-rcar.txt
index 0822a08..d6de643 100644
--- a/dts/Bindings/pwm/renesas,pwm-rcar.txt
+++ b/dts/Bindings/pwm/renesas,pwm-rcar.txt
@@ -7,6 +7,7 @@ Required Properties:
- "renesas,pwm-r8a7790": for R-Car H2
- "renesas,pwm-r8a7791": for R-Car M2-W
- "renesas,pwm-r8a7794": for R-Car E2
+ - "renesas,pwm-r8a7795": for R-Car H3
- reg: base address and length of the registers block for the PWM.
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
the cells format.
diff --git a/dts/Bindings/pwm/st,stmpe-pwm.txt b/dts/Bindings/pwm/st,stmpe-pwm.txt
new file mode 100644
index 0000000..cb20964
--- /dev/null
+++ b/dts/Bindings/pwm/st,stmpe-pwm.txt
@@ -0,0 +1,18 @@
+== ST STMPE PWM controller ==
+
+This is a PWM block embedded in the ST Microelectronics STMPE
+(ST Multi-Purpose Expander) chips. The PWM is registered as a
+subdevices of the STMPE MFD device.
+
+Required properties:
+- compatible: should be:
+ - "st,stmpe-pwm"
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+ the cells format.
+
+Example:
+
+pwm0: pwm {
+ compatible = "st,stmpe-pwm";
+ #pwm-cells = <2>;
+};
diff --git a/dts/Bindings/regmap/regmap.txt b/dts/Bindings/regmap/regmap.txt
index 0127be3..873096b 100644
--- a/dts/Bindings/regmap/regmap.txt
+++ b/dts/Bindings/regmap/regmap.txt
@@ -14,7 +14,7 @@ architectures that typically run big-endian operating systems
be marked that way in the devicetree.
On SoCs that can be operated in both big-endian and little-endian
-modes, with a single hardware switch controlling both the endianess
+modes, with a single hardware switch controlling both the endianness
of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
chips), "native-endian" is used to allow using the same device tree
blob in both cases.
diff --git a/dts/Bindings/regulator/da9210.txt b/dts/Bindings/regulator/da9210.txt
index 7aa9b1f..58065ca 100644
--- a/dts/Bindings/regulator/da9210.txt
+++ b/dts/Bindings/regulator/da9210.txt
@@ -1,4 +1,4 @@
-* Dialog Semiconductor DA9210 Voltage Regulator
+* Dialog Semiconductor DA9210 Multi-phase 12A DCDC BUCK Converter
Required properties:
@@ -18,8 +18,12 @@ Example:
compatible = "dlg,da9210";
reg = <0x68>;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1000000>;
+ interrupt-parent = <...>;
+ interrupts = <...>;
+
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <1600000>;
+ regulator-max-microamp = <4600000>;
regulator-boot-on;
- regulator-always-on;
};
diff --git a/dts/Bindings/regulator/da9211.txt b/dts/Bindings/regulator/da9211.txt
index c620493..0f2a6f8 100644
--- a/dts/Bindings/regulator/da9211.txt
+++ b/dts/Bindings/regulator/da9211.txt
@@ -1,7 +1,8 @@
-* Dialog Semiconductor DA9211/DA9213/DA9215 Voltage Regulator
+* Dialog Semiconductor DA9211/DA9212/DA9213/DA9214/DA9215 Voltage Regulator
Required properties:
-- compatible: "dlg,da9211" or "dlg,da9213" or "dlg,da9215"
+- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213"
+ or "dlg,da9214" or "dlg,da9215"
- reg: I2C slave address, usually 0x68.
- interrupts: the interrupt outputs of the controller
- regulators: A node that houses a sub-node for each regulator within the
@@ -30,6 +31,25 @@ Example 1) DA9211
regulator-max-microamp = <5000000>;
enable-gpios = <&gpio 27 0>;
};
+ };
+ };
+
+Example 2) DA9212
+
+ pmic: da9212@68 {
+ compatible = "dlg,da9212";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <5000000>;
+ enable-gpios = <&gpio 27 0>;
+ };
BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 300000>;
@@ -41,7 +61,7 @@ Example 1) DA9211
};
};
-Example 2) DA9213
+Example 3) DA9213
pmic: da9213@68 {
compatible = "dlg,da9213";
reg = <0x68>;
@@ -56,6 +76,24 @@ Example 2) DA9213
regulator-max-microamp = <6000000>;
enable-gpios = <&gpio 27 0>;
};
+ };
+ };
+
+Example 4) DA9214
+ pmic: da9214@68 {
+ compatible = "dlg,da9214";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <6000000>;
+ enable-gpios = <&gpio 27 0>;
+ };
BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 300000>;
@@ -67,8 +105,7 @@ Example 2) DA9213
};
};
-
-Example 3) DA9215
+Example 5) DA9215
pmic: da9215@68 {
compatible = "dlg,da9215";
reg = <0x68>;
diff --git a/dts/Bindings/regulator/mt6323-regulator.txt b/dts/Bindings/regulator/mt6323-regulator.txt
new file mode 100644
index 0000000..c35d878
--- /dev/null
+++ b/dts/Bindings/regulator/mt6323-regulator.txt
@@ -0,0 +1,237 @@
+Mediatek MT6323 Regulator Driver
+
+All voltage regulators are defined as subnodes of the regulators node. A list
+of regulators provided by this controller are defined as subnodes of the
+PMIC's node. Each regulator is named according to its regulator type,
+buck_<name> and ldo_<name>. The definition for each of these nodes is defined
+using the standard binding for regulators at
+Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+ buck_vproc, buck_vsys, buck_vpa
+LDO:
+ ldo_vtcxo, ldo_vcn28, ldo_vcn33_bt, ldo_vcn33_wifi, ldo_va, ldo_vcama,
+ ldo_vio28, ldo_vusb, ldo_vmc, ldo_vmch, ldo_vemc3v3, ldo_vgp1, ldo_vgp2,
+ ldo_vgp3, ldo_vcn18, ldo_vsim1, ldo_vsim2, ldo_vrtc, ldo_vcamaf, ldo_vibr,
+ ldo_vrf18, ldo_vm, ldo_vio18, ldo_vcamd, ldo_vcamio
+
+Example:
+
+ pmic: mt6323 {
+ mt6323regulator: regulators {
+ mt6323_vproc_reg: buck_vproc{
+ regulator-name = "vproc";
+ regulator-min-microvolt = < 700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vsys_reg: buck_vsys{
+ regulator-name = "vsys";
+ regulator-min-microvolt = <1400000>;
+ regulator-max-microvolt = <2987500>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vpa_reg: buck_vpa{
+ regulator-name = "vpa";
+ regulator-min-microvolt = < 500000>;
+ regulator-max-microvolt = <3650000>;
+ };
+
+ mt6323_vtcxo_reg: ldo_vtcxo{
+ regulator-name = "vtcxo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <90>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcn28_reg: ldo_vcn28{
+ regulator-name = "vcn28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <185>;
+ };
+
+ mt6323_vcn33_bt_reg: ldo_vcn33_bt{
+ regulator-name = "vcn33_bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-enable-ramp-delay = <185>;
+ };
+
+ mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
+ regulator-name = "vcn33_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-enable-ramp-delay = <185>;
+ };
+
+ mt6323_va_reg: ldo_va{
+ regulator-name = "va";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcama_reg: ldo_vcama{
+ regulator-name = "vcama";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vio28_reg: ldo_vio28{
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vusb_reg: ldo_vusb{
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-boot-on;
+ };
+
+ mt6323_vmc_reg: ldo_vmc{
+ regulator-name = "vmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ regulator-boot-on;
+ };
+
+ mt6323_vmch_reg: ldo_vmch{
+ regulator-name = "vmch";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ regulator-boot-on;
+ };
+
+ mt6323_vemc3v3_reg: ldo_vemc3v3{
+ regulator-name = "vemc3v3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ regulator-boot-on;
+ };
+
+ mt6323_vgp1_reg: ldo_vgp1{
+ regulator-name = "vgp1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vgp2_reg: ldo_vgp2{
+ regulator-name = "vgp2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vgp3_reg: ldo_vgp3{
+ regulator-name = "vgp3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vcn18_reg: ldo_vcn18{
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vsim1_reg: ldo_vsim1{
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vsim2_reg: ldo_vsim2{
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vrtc_reg: ldo_vrtc{
+ regulator-name = "vrtc";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcamaf_reg: ldo_vcamaf{
+ regulator-name = "vcamaf";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vibr_reg: ldo_vibr{
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ };
+
+ mt6323_vrf18_reg: ldo_vrf18{
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1825000>;
+ regulator-max-microvolt = <1825000>;
+ regulator-enable-ramp-delay = <187>;
+ };
+
+ mt6323_vm_reg: ldo_vm{
+ regulator-name = "vm";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vio18_reg: ldo_vio18{
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcamd_reg: ldo_vcamd{
+ regulator-name = "vcamd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vcamio_reg: ldo_vcamio{
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+ };
+ };
diff --git a/dts/Bindings/regulator/pwm-regulator.txt b/dts/Bindings/regulator/pwm-regulator.txt
index ed936f0..3aeba9f 100644
--- a/dts/Bindings/regulator/pwm-regulator.txt
+++ b/dts/Bindings/regulator/pwm-regulator.txt
@@ -34,20 +34,44 @@ Only required for Voltage Table Mode:
First cell is voltage in microvolts (uV)
Second cell is duty-cycle in percent (%)
+Optional properties for Continuous mode:
+- pwm-dutycycle-unit: Integer value encoding the duty cycle unit. If not
+ defined, <100> is assumed, meaning that
+ pwm-dutycycle-range contains values expressed in
+ percent.
+
+- pwm-dutycycle-range: Should contain 2 entries. The first entry is encoding
+ the dutycycle for regulator-min-microvolt and the
+ second one the dutycycle for regulator-max-microvolt.
+ Duty cycle values are expressed in pwm-dutycycle-unit.
+ If not defined, <0 100> is assumed.
+
NB: To be clear, if voltage-table is provided, then the device will be used
in Voltage Table Mode. If no voltage-table is provided, then the device will
be used in Continuous Voltage Mode.
+Optional properties:
+--------------------
+- enable-gpios: GPIO to use to enable/disable the regulator
+
Any property defined as part of the core regulator binding can also be used.
(See: ../regulator/regulator.txt)
-Continuous Voltage Example:
+Continuous Voltage With Enable GPIO Example:
pwm_regulator {
compatible = "pwm-regulator;
pwms = <&pwm1 0 8448 0>;
+ enable-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <1016000>;
regulator-max-microvolt = <1114000>;
regulator-name = "vdd_logic";
+ /* unit == per-mille */
+ pwm-dutycycle-unit = <1000>;
+ /*
+ * Inverted PWM logic, and the duty cycle range is limited
+ * to 30%-70%.
+ */
+ pwm-dutycycle-range <700 300>; /* */
};
Voltage Table Example:
diff --git a/dts/Bindings/regulator/qcom,spmi-regulator.txt b/dts/Bindings/regulator/qcom,spmi-regulator.txt
index 46c6f3e..0fa3b0f 100644
--- a/dts/Bindings/regulator/qcom,spmi-regulator.txt
+++ b/dts/Bindings/regulator/qcom,spmi-regulator.txt
@@ -113,9 +113,9 @@ pm8916:
l14, l15, l16, l17, l18
pm8941:
- s1, s2, s3, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14,
- l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3,
- mvs1, mvs2
+ s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
+ l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3,
+ 5vs1, 5vs2
pm8994:
s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
diff --git a/dts/Bindings/remoteproc/qcom,q6v5.txt b/dts/Bindings/remoteproc/qcom,q6v5.txt
new file mode 100644
index 0000000..57cb49e
--- /dev/null
+++ b/dts/Bindings/remoteproc/qcom,q6v5.txt
@@ -0,0 +1,137 @@
+Qualcomm Hexagon Peripheral Image Loader
+
+This document defines the binding for a component that loads and boots firmware
+on the Qualcomm Hexagon core.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,q6v5-pil"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the qdsp6 and
+ rmb register blocks
+
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "q6dsp" and "rmb"
+
+- interrupts-extended:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must list the watchdog, fatal IRQs ready, handover and
+ stop-ack IRQs
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
+
+- clocks:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the iface, bus and mem clocks to be held on
+ behalf of the booting of the Hexagon core
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "iface", "bus", "mem"
+
+- resets:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the reset-controller for the modem sub-system
+
+- reset-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "mss_restart"
+
+- cx-supply:
+- mss-supply:
+- mx-supply:
+- pll-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the regulators to be held on behalf of the
+ booting of the Hexagon core
+
+- qcom,smem-states:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the smem state for requesting the Hexagon to
+ shut down
+
+- qcom,smem-state-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "stop"
+
+- qcom,halt-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: a phandle reference to a syscon representing TCSR followed
+ by the three offsets within syscon for q6, modem and nc
+ halt registers.
+
+= SUBNODES:
+The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
+the memory regions used by the Hexagon firmware. Each sub-node must contain:
+
+- memory-region:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the reserved-memory for the region
+
+= EXAMPLE
+The following example describes the resources needed to boot control the
+Hexagon, as it is found on MSM8974 boards.
+
+ modem-rproc@fc880000 {
+ compatible = "qcom,q6v5-pil";
+ reg = <0xfc880000 0x100>,
+ <0xfc820000 0x020>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc 0 24 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 3 0>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>;
+ clock-names = "iface", "bus", "mem";
+
+ qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ mba {
+ memory-region = <&mba_region>;
+ };
+
+ mpss {
+ memory-region = <&mpss_region>;
+ };
+ };
diff --git a/dts/Bindings/reserved-memory/ramoops.txt b/dts/Bindings/reserved-memory/ramoops.txt
new file mode 100644
index 0000000..e81f821
--- /dev/null
+++ b/dts/Bindings/reserved-memory/ramoops.txt
@@ -0,0 +1,48 @@
+Ramoops oops/panic logger
+=========================
+
+ramoops provides persistent RAM storage for oops and panics, so they can be
+recovered after a reboot. This is a child-node of "/reserved-memory", and
+is named "ramoops" after the backend, rather than "pstore" which is the
+subsystem.
+
+Parts of this storage may be set aside for other persistent log buffers, such
+as kernel log messages, or for optional ECC error-correction data. The total
+size of these optional buffers must fit in the reserved region.
+
+Any remaining space will be used for a circular buffer of oops and panic
+records. These records have a configurable size, with a size of 0 indicating
+that they should be disabled.
+
+At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size"
+must be set non-zero, but are otherwise optional as listed below.
+
+
+Required properties:
+
+- compatible: must be "ramoops"
+
+- reg: region of memory that is preserved between reboots
+
+
+Optional properties:
+
+- ecc-size: enables ECC support and specifies ECC buffer size in bytes
+ (defaults to 0: no ECC)
+
+- record-size: maximum size in bytes of each dump done on oops/panic
+ (defaults to 0: disabled)
+
+- console-size: size in bytes of log buffer reserved for kernel messages
+ (defaults to 0: disabled)
+
+- ftrace-size: size in bytes of log buffer reserved for function tracing and
+ profiling (defaults to 0: disabled)
+
+- pmsg-size: size in bytes of log buffer reserved for userspace messages
+ (defaults to 0: disabled)
+
+- unbuffered: if present, use unbuffered mappings to map the reserved region
+ (defaults to buffered mappings)
+
+- no-dump-oops: if present, only dump panics (defaults to panics and oops)
diff --git a/dts/Bindings/reset/amlogic,meson-reset.txt b/dts/Bindings/reset/amlogic,meson-reset.txt
new file mode 100644
index 0000000..e746b63
--- /dev/null
+++ b/dts/Bindings/reset/amlogic,meson-reset.txt
@@ -0,0 +1,18 @@
+Amlogic Meson SoC Reset Controller
+=======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset"
+- reg: should contain the register address base
+- #reset-cells: 1, see below
+
+example:
+
+reset: reset-controller {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x04404 0x0 0x20>;
+ #reset-cells = <1>;
+};
diff --git a/dts/Bindings/reset/hisilicon,hi6220-reset.txt b/dts/Bindings/reset/hisilicon,hi6220-reset.txt
index e0b185a..c25da39 100644
--- a/dts/Bindings/reset/hisilicon,hi6220-reset.txt
+++ b/dts/Bindings/reset/hisilicon,hi6220-reset.txt
@@ -8,7 +8,9 @@ The reset controller registers are part of the system-ctl block on
hi6220 SoC.
Required properties:
-- compatible: may be "hisilicon,hi6220-sysctrl"
+- compatible: should be one of the following:
+ - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
+ - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
diff --git a/dts/Bindings/reset/ti-syscon-reset.txt b/dts/Bindings/reset/ti-syscon-reset.txt
new file mode 100644
index 0000000..164c7f3
--- /dev/null
+++ b/dts/Bindings/reset/ti-syscon-reset.txt
@@ -0,0 +1,91 @@
+TI SysCon Reset Controller
+=======================
+
+Almost all SoCs have hardware modules that require reset control in addition
+to clock and power control for their functionality. The reset control is
+typically provided by means of memory-mapped I/O registers. These registers are
+sometimes a part of a larger register space region implementing various
+functionalities. This register range is best represented as a syscon node to
+allow multiple entities to access their relevant registers in the common
+register space.
+
+A SysCon Reset Controller node defines a device that uses a syscon node
+and provides reset management functionality for various hardware modules
+present on the SoC.
+
+SysCon Reset Controller Node
+============================
+Each of the reset provider/controller nodes should be a child of a syscon
+node and have the following properties.
+
+Required properties:
+--------------------
+ - compatible : Should be,
+ "ti,k2e-pscrst"
+ "ti,k2l-pscrst"
+ "ti,k2hk-pscrst"
+ "ti,syscon-reset"
+ - #reset-cells : Should be 1. Please see the reset consumer node below
+ for usage details
+ - ti,reset-bits : Contains the reset control register information
+ Should contain 7 cells for each reset exposed to
+ consumers, defined as:
+ Cell #1 : offset of the reset assert control
+ register from the syscon register base
+ Cell #2 : bit position of the reset in the reset
+ assert control register
+ Cell #3 : offset of the reset deassert control
+ register from the syscon register base
+ Cell #4 : bit position of the reset in the reset
+ deassert control register
+ Cell #5 : offset of the reset status register
+ from the syscon register base
+ Cell #6 : bit position of the reset in the
+ reset status register
+ Cell #7 : Flags used to control reset behavior,
+ availible flags defined in the DT include
+ file <dt-bindings/reset/ti-syscon.h>
+
+SysCon Reset Consumer Nodes
+===========================
+Each of the reset consumer nodes should have the following properties,
+in addition to their own properties.
+
+Required properties:
+--------------------
+ - resets : A phandle to the reset controller node and an index number
+ to a reset specifier as defined above.
+
+Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
+common reset controller usage by consumers.
+
+Example:
+--------
+The following example demonstrates a syscon node, the reset controller node
+using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
+Edison SoC.
+
+/ {
+ soc {
+ psc: power-sleep-controller@02350000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x02350000 0x1000>;
+
+ pscrst: psc-reset {
+ compatible = "ti,k2e-pscrst", "ti,syscon-reset";
+ #reset-cells = <1>;
+
+ ti,reset-bits = <
+ 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */
+ 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */
+ >;
+ };
+ };
+
+ dsp0: dsp0 {
+ ...
+ resets = <&pscrst 0>;
+ ...
+ };
+ };
+};
diff --git a/dts/Bindings/rng/amlogic,meson-rng.txt b/dts/Bindings/rng/amlogic,meson-rng.txt
new file mode 100644
index 0000000..202f2d0
--- /dev/null
+++ b/dts/Bindings/rng/amlogic,meson-rng.txt
@@ -0,0 +1,14 @@
+Amlogic Meson Random number generator
+=====================================
+
+Required properties:
+
+- compatible : should be "amlogic,meson-rng"
+- reg : Specifies base physical address and size of the registers.
+
+Example:
+
+rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0xc8834000 0x0 0x4>;
+};
diff --git a/dts/Bindings/rng/brcm,bcm2835.txt b/dts/Bindings/rng/brcm,bcm2835.txt
index 07ccdaa..2654269 100644
--- a/dts/Bindings/rng/brcm,bcm2835.txt
+++ b/dts/Bindings/rng/brcm,bcm2835.txt
@@ -2,7 +2,8 @@ BCM2835 Random number generator
Required properties:
-- compatible : should be "brcm,bcm2835-rng"
+- compatible : should be "brcm,bcm2835-rng" or "brcm,bcm-nsp-rng" or
+ "brcm,bcm5301x-rng"
- reg : Specifies base physical address and size of the registers.
Example:
@@ -11,3 +12,8 @@ rng {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
};
+
+rng@18033000 {
+ compatible = "brcm,bcm-nsp-rng";
+ reg = <0x18033000 0x14>;
+};
diff --git a/dts/Bindings/rtc/rtc-opal.txt b/dts/Bindings/rtc/rtc-opal.txt
index a1734e5..2340938 100644
--- a/dts/Bindings/rtc/rtc-opal.txt
+++ b/dts/Bindings/rtc/rtc-opal.txt
@@ -2,7 +2,7 @@ IBM OPAL real-time clock
------------------------
Required properties:
-- comapatible: Should be "ibm,opal-rtc"
+- compatible: Should be "ibm,opal-rtc"
Optional properties:
- wakeup-source: Decides if the wakeup is supported or not
diff --git a/dts/Bindings/security/tpm/tpm_tis_spi.txt b/dts/Bindings/security/tpm/tpm_tis_spi.txt
new file mode 100644
index 0000000..85741cd
--- /dev/null
+++ b/dts/Bindings/security/tpm/tpm_tis_spi.txt
@@ -0,0 +1,24 @@
+Required properties:
+- compatible: should be one of the following
+ "st,st33htpm-spi"
+ "infineon,slb9670"
+ "tcg,tpm_tis-spi"
+- spi-max-frequency: Maximum SPI frequency (depends on TPMs).
+
+Optional SoC Specific Properties:
+- pinctrl-names: Contains only one value - "default".
+- pintctrl-0: Specifies the pin control groups used for this controller.
+
+Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
+
+&mcspi4 {
+
+ status = "okay";
+
+ tpm_tis@0 {
+
+ compatible = "tcg,tpm_tis-spi";
+
+ spi-max-frequency = <10000000>;
+ };
+};
diff --git a/dts/Bindings/serial/8250.txt b/dts/Bindings/serial/8250.txt
index 936ab5b..f5561ac 100644
--- a/dts/Bindings/serial/8250.txt
+++ b/dts/Bindings/serial/8250.txt
@@ -42,6 +42,9 @@ Optional properties:
- auto-flow-control: one way to enable automatic flow control support. The
driver is allowed to detect support for the capability even without this
property.
+- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
+ line respectively. It will use specified GPIO instead of the peripheral
+ function pin for the UART feature. If unsure, don't specify this property.
Note:
* fsl,ns16550:
@@ -63,3 +66,19 @@ Example:
interrupts = <10>;
reg-shift = <2>;
};
+
+Example for OMAP UART using GPIO-based modem control signals:
+
+ uart4: serial@49042000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49042000 0x400>;
+ interrupts = <80>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/serial/cirrus,clps711x-uart.txt b/dts/Bindings/serial/cirrus,clps711x-uart.txt
index caaeb25..07013fa 100644
--- a/dts/Bindings/serial/cirrus,clps711x-uart.txt
+++ b/dts/Bindings/serial/cirrus,clps711x-uart.txt
@@ -1,7 +1,7 @@
* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
Required properties:
-- compatible: Should be "cirrus,clps711x-uart".
+- compatible: Should be "cirrus,ep7209-uart".
- reg: Address and length of the register set for the device.
- interrupts: Should contain UART TX and RX interrupt.
- clocks: Should contain UART core clock number.
@@ -20,7 +20,7 @@ Example:
};
uart1: uart@80000480 {
- compatible = "cirrus,clps711x-uart";
+ compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
reg = <0x80000480 0x80>;
interrupts = <12 13>;
clocks = <&clks 11>;
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index e99e10a..0015c72 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -6,6 +6,7 @@ Required properties:
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
+ * "mediatek,mt6755-uart" for MT6755 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
diff --git a/dts/Bindings/serial/qcom,msm-uartdm.txt b/dts/Bindings/serial/qcom,msm-uartdm.txt
index 182777f..d5f73b8 100644
--- a/dts/Bindings/serial/qcom,msm-uartdm.txt
+++ b/dts/Bindings/serial/qcom,msm-uartdm.txt
@@ -28,10 +28,10 @@ Optional properties:
- dma-names: Should contain "tx" for transmit and "rx" for receive channels
- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
used with TX DMA channel. Required when using DMA for transmission
- with UARTDM v1.3 and bellow.
+ with UARTDM v1.3 and below.
- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
used with RX DMA channel. Required when using DMA for reception
- with UARTDM v1.3 and bellow.
+ with UARTDM v1.3 and below.
Note: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index 528c3b9..1e4000d 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -31,6 +31,8 @@ Required properties:
- "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
- "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.
- "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
+ - "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
+ - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
- "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART,
@@ -76,6 +78,10 @@ Optional properties:
- dmas: Must contain a list of two references to DMA specifiers, one for
transmission, and one for reception.
- dma-names: Must contain a list of two DMA names, "tx" and "rx".
+ - {cts,dsr,dcd,rng,rts,dtr}-gpios: Specify GPIOs for modem lines, cfr. the
+ generic serial DT bindings in serial.txt.
+ - uart-has-rtscts: Indicates dedicated lines for RTS/CTS hardware flow
+ control, cfr. the generic serial DT bindings in serial.txt.
Example:
aliases {
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/cpm.txt b/dts/Bindings/soc/fsl/cpm_qe/cpm.txt
index 160c752..160c752 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/cpm.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/cpm.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt b/dts/Bindings/soc/fsl/cpm_qe/cpm/brg.txt
index 4c7d45e..4c7d45e 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/cpm/brg.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt b/dts/Bindings/soc/fsl/cpm_qe/cpm/i2c.txt
index 87bc604..87bc604 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/cpm/i2c.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt b/dts/Bindings/soc/fsl/cpm_qe/cpm/pic.txt
index 8e3ee16..8e3ee16 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/cpm/pic.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt b/dts/Bindings/soc/fsl/cpm_qe/cpm/usb.txt
index 74bfda4..74bfda4 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/cpm/usb.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/gpio.txt b/dts/Bindings/soc/fsl/cpm_qe/gpio.txt
index 349f79f..349f79f 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/gpio.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/gpio.txt
diff --git a/dts/Bindings/soc/fsl/cpm_qe/network.txt b/dts/Bindings/soc/fsl/cpm_qe/network.txt
new file mode 100644
index 0000000..03c7416
--- /dev/null
+++ b/dts/Bindings/soc/fsl/cpm_qe/network.txt
@@ -0,0 +1,124 @@
+* Network
+
+Currently defined compatibles:
+- fsl,cpm1-scc-enet
+- fsl,cpm2-scc-enet
+- fsl,cpm1-fec-enet
+- fsl,cpm2-fcc-enet (third resource is GFEMR)
+- fsl,qe-enet
+
+Example:
+
+ ethernet@11300 {
+ compatible = "fsl,mpc8272-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <11300 20 8400 100 11390 1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY0>;
+ fsl,cpm-command = <12000300>;
+ };
+
+* MDIO
+
+Currently defined compatibles:
+fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
+fsl,cpm2-mdio-bitbang (reg is port C registers)
+
+Properties for fsl,cpm2-mdio-bitbang:
+fsl,mdio-pin : pin of port C controlling mdio data
+fsl,mdc-pin : pin of port C controlling mdio clock
+
+Example:
+ mdio@10d40 {
+ compatible = "fsl,mpc8272ads-mdio-bitbang",
+ "fsl,mpc8272-mdio-bitbang",
+ "fsl,cpm2-mdio-bitbang";
+ reg = <10d40 14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,mdio-pin = <12>;
+ fsl,mdc-pin = <13>;
+ };
+
+* HDLC
+
+Currently defined compatibles:
+- fsl,ucc-hdlc
+
+Properties for fsl,ucc-hdlc:
+- rx-clock-name
+- tx-clock-name
+ Usage: required
+ Value type: <string>
+ Definition : Must be "brg1"-"brg16" for internal clock source,
+ Must be "clk1"-"clk24" for external clock source.
+
+- fsl,tdm-interface
+ Usage: optional
+ Value type: <empty>
+ Definition : Specify that hdlc is based on tdm-interface
+
+The property below is dependent on fsl,tdm-interface:
+- fsl,rx-sync-clock
+ Usage: required
+ Value type: <string>
+ Definition : Must be "none", "rsync_pin", "brg9-11" and "brg13-15".
+
+- fsl,tx-sync-clock
+ Usage: required
+ Value type: <string>
+ Definition : Must be "none", "tsync_pin", "brg9-11" and "brg13-15".
+
+- fsl,tdm-framer-type
+ Usage: required for tdm interface
+ Value type: <string>
+ Definition : "e1" or "t1".Now e1 and t1 are used, other framer types
+ are not supported.
+
+- fsl,tdm-id
+ Usage: required for tdm interface
+ Value type: <u32>
+ Definition : number of TDM ID
+
+- fsl,tx-timeslot-mask
+- fsl,rx-timeslot-mask
+ Usage: required for tdm interface
+ Value type: <u32>
+ Definition : time slot mask for TDM operation. Indicates which time
+ slots used for transmitting and receiving.
+
+- fsl,siram-entry-id
+ Usage: required for tdm interface
+ Value type: <u32>
+ Definition : Must be 0,2,4...64. the number of TDM entry.
+
+- fsl,tdm-internal-loopback
+ usage: optional for tdm interface
+ value type: <empty>
+ Definition : Internal loopback connecting on TDM layer.
+
+Example for tdm interface:
+
+ ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffffffe>;
+ fsl,rx-timeslot-mask = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+
+Example for hdlc without tdm interface:
+
+ ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "brg1";
+ tx-clock-name = "brg1";
+ };
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/qe.txt b/dts/Bindings/soc/fsl/cpm_qe/qe.txt
index 4f89302..d7afaff 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/qe.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/qe.txt
@@ -69,6 +69,58 @@ Example:
};
};
+* Interrupt Controller (IC)
+
+Required properties:
+- compatible : should be "fsl,qe-ic".
+- reg : Address range of IC register set.
+- interrupts : interrupts generated by the device.
+- interrupt-controller : this device is a interrupt controller.
+
+Example:
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <95 2 0 0 94 2 0 0>;
+ };
+
+* Serial Interface Block (SI)
+
+The SI manages the routing of eight TDM lines to the QE block serial drivers
+, the MCC and the UCCs, for receive and transmit.
+
+Required properties:
+- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain
+ "fsl,t1040-qe-si".
+- reg : Address range of SI register set.
+
+Example:
+
+ si1: si@700 {
+ compatible = "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+* Serial Interface Block RAM(SIRAM)
+
+store the routing entries of SI
+
+Required properties:
+- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain
+ "fsl,t1040-qe-siram".
+- reg : Address range of SI RAM.
+
+Example:
+
+ siram1: siram@1000 {
+ compatible = "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
* QE Firmware Node
This node defines a firmware binary that is embedded in the device tree, for
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/qe/firmware.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/firmware.txt
index 249db3a..249db3a 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/qe/firmware.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/qe/firmware.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/qe/par_io.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/par_io.txt
index 6098426..6098426 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/qe/par_io.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/qe/par_io.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/pincfg.txt
index ec6ee2e..ec6ee2e 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/qe/pincfg.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/qe/ucc.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt
index e47734b..e47734b 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/qe/ucc.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/qe/usb.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt
index 9ccd5f3..9ccd5f3 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/qe/usb.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt
diff --git a/dts/Bindings/powerpc/fsl/cpm_qe/serial.txt b/dts/Bindings/soc/fsl/cpm_qe/serial.txt
index 2ea76d9..2ea76d9 100644
--- a/dts/Bindings/powerpc/fsl/cpm_qe/serial.txt
+++ b/dts/Bindings/soc/fsl/cpm_qe/serial.txt
diff --git a/dts/Bindings/soc/fsl/cpm_qe/uqe_serial.txt b/dts/Bindings/soc/fsl/cpm_qe/uqe_serial.txt
new file mode 100644
index 0000000..8823c86
--- /dev/null
+++ b/dts/Bindings/soc/fsl/cpm_qe/uqe_serial.txt
@@ -0,0 +1,17 @@
+* Serial
+
+Required Properties:
+compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
+"fsl,t1040-ucc-uart".
+port-number : port number of UCC-UART
+tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
+ should be "clk1"-"clk28" for external clock source.
+
+Example:
+
+ ucc_serial: ucc@2200 {
+ compatible = "fsl,t1040-ucc-uart";
+ port-number = <0>;
+ rx-clock-name = "brg2";
+ tx-clock-name = "brg2";
+ };
diff --git a/dts/Bindings/soc/qcom/qcom,smp2p.txt b/dts/Bindings/soc/qcom/qcom,smp2p.txt
index 5cc82b8..af9ca37 100644
--- a/dts/Bindings/soc/qcom/qcom,smp2p.txt
+++ b/dts/Bindings/soc/qcom/qcom,smp2p.txt
@@ -68,7 +68,7 @@ important.
Value type: <u32>
Definition: must be 2 - denoting the bit in the entry and IRQ flags
-- #qcom,state-cells:
+- #qcom,smem-state-cells:
Usage: required for outgoing entries
Value type: <u32>
Definition: must be 1 - denoting the bit in the entry
@@ -92,7 +92,7 @@ wcnss-smp2p {
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
- #qcom,state-cells = <1>;
+ #qcom,smem-state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
diff --git a/dts/Bindings/soc/qcom/qcom,smsm.txt b/dts/Bindings/soc/qcom/qcom,smsm.txt
index a6634c7..2993b5a 100644
--- a/dts/Bindings/soc/qcom/qcom,smsm.txt
+++ b/dts/Bindings/soc/qcom/qcom,smsm.txt
@@ -51,7 +51,7 @@ important.
Definition: specifies the offset, in words, of the first bit for this
entry
-- #qcom,state-cells:
+- #qcom,smem-state-cells:
Usage: required for local entry
Value type: <u32>
Definition: must be 1 - denotes bit number
@@ -91,7 +91,7 @@ smsm {
apps_smsm: apps@0 {
reg = <0>;
- #qcom,state-cells = <1>;
+ #qcom,smem-state-cells = <1>;
};
wcnss_smsm: wcnss@7 {
diff --git a/dts/Bindings/soc/qcom/qcom,wcnss.txt b/dts/Bindings/soc/qcom/qcom,wcnss.txt
new file mode 100644
index 0000000..4ea39e9
--- /dev/null
+++ b/dts/Bindings/soc/qcom/qcom,wcnss.txt
@@ -0,0 +1,116 @@
+Qualcomm WCNSS Binding
+
+This binding describes the Qualcomm WCNSS hardware. It consists of control
+block and a BT, WiFi and FM radio block, all using SMD as command channels.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be: "qcom,wcnss",
+
+- qcom,smd-channel:
+ Usage: required
+ Value type: <string>
+ Definition: standard SMD property specifying the SMD channel used for
+ communication with the WiFi firmware.
+ Should be "WCNSS_CTRL".
+
+- qcom,mmio:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to a node specifying the wcnss "ccu" and "dxe"
+ register blocks. The node must be compatible with one of
+ the following:
+ "qcom,riva",
+ "qcom,pronto"
+
+= SUBNODES
+The subnodes of the wcnss node are optional and describe the individual blocks in
+the WCNSS.
+
+== Bluetooth
+The following properties are defined to the bluetooth node:
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,wcnss-bt"
+
+== WiFi
+The following properties are defined to the WiFi node:
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,wcnss-wlan",
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the "rx" and "tx" interrupts
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must contain "rx" and "tx"
+
+- qcom,smem-state:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should reference the tx-enable and tx-rings-empty SMEM states
+
+- qcom,smem-state-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must contain "tx-enable" and "tx-rings-empty"
+
+= EXAMPLE
+The following example represents a SMD node, with one edge representing the
+"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks
+described; as found on the 8974 platform.
+
+smd {
+ compatible = "qcom,smd";
+
+ pronto-edge {
+ interrupts = <0 142 1>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,mmio = <&pronto>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wlan {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <0 145 0>, <0 146 0>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+};
+
+soc {
+ pronto: pronto {
+ compatible = "qcom,pronto";
+
+ reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+ };
+};
diff --git a/dts/Bindings/sound/adi,adau17x1.txt b/dts/Bindings/sound/adi,adau17x1.txt
index 8dbce0e..1447dec 100644
--- a/dts/Bindings/sound/adi,adau17x1.txt
+++ b/dts/Bindings/sound/adi,adau17x1.txt
@@ -13,6 +13,11 @@ Required properties:
- reg: The i2c address. Value depends on the state of ADDR0
and ADDR1, as wired in hardware.
+Optional properties:
+ - clock-names: If provided must be "mclk".
+ - clocks: phandle + clock-specifiers for the clock that provides
+ the audio master clock for the device.
+
Examples:
#include <dt-bindings/sound/adau17x1.h>
@@ -20,5 +25,8 @@ Examples:
adau1361@38 {
compatible = "adi,adau1761";
reg = <0x38>;
+
+ clock-names = "mclk";
+ clocks = <&audio_clock>;
};
};
diff --git a/dts/Bindings/sound/adi,adau7002.txt b/dts/Bindings/sound/adi,adau7002.txt
new file mode 100644
index 0000000..f144ee1
--- /dev/null
+++ b/dts/Bindings/sound/adi,adau7002.txt
@@ -0,0 +1,19 @@
+Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter
+
+Required properties:
+
+ - compatible: Must be "adi,adau7002"
+
+Optional properties:
+
+ - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD
+ supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt
+
+ If this property is not present it is assumed that the supply pin is
+ hardwired to always on.
+
+Example:
+ adau7002: pdm-to-i2s {
+ compatible = "adi,adau7002";
+ IOVDD-supply = <&supply>;
+ };
diff --git a/dts/Bindings/sound/brcm,cygnus-audio.txt b/dts/Bindings/sound/brcm,cygnus-audio.txt
new file mode 100644
index 0000000..b139e66
--- /dev/null
+++ b/dts/Bindings/sound/brcm,cygnus-audio.txt
@@ -0,0 +1,67 @@
+BROADCOM Cygnus Audio I2S/TDM/SPDIF controller
+
+Required properties:
+ - compatible : "brcm,cygnus-audio"
+ - #address-cells: 32bit valued, 1 cell.
+ - #size-cells: 32bit valued, 0 cell.
+ - reg : Should contain audio registers location and length
+ - reg-names: names of the registers listed in "reg" property
+ Valid names are "aud" and "i2s_in". "aud" contains a
+ set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains
+ a set of I2S_IN registers.
+ - clocks: PLL and leaf clocks used by audio ports
+ - assigned-clocks: PLL and leaf clocks
+ - assigned-clock-parents: parent clocks of the assigned clocks
+ (usually the PLL)
+ - assigned-clock-rates: List of clock frequencies of the
+ assigned clocks
+ - clock-names: names of 3 leaf clocks used by audio ports
+ Valid names are "ch0_audio", "ch1_audio", "ch2_audio"
+ - interrupts: audio DMA interrupt number
+
+SSP Subnode properties:
+- reg: The index of ssp port interface to use
+ Valid value are 0, 1, 2, or 3 (for spdif)
+
+Example:
+ cygnus_audio: audio@180ae000 {
+ compatible = "brcm,cygnus-audio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;
+ reg-names = "aud", "i2s_in";
+ clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
+ <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
+ <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
+ assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
+ <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
+ <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
+ <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
+ assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
+ assigned-clock-rates = <1769470191>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "ch0_audio", "ch1_audio", "ch2_audio";
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+
+ ssp0: ssp_port@0 {
+ reg = <0>;
+ status = "okay";
+ };
+
+ ssp1: ssp_port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ ssp2: ssp_port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ spdif: spdif_port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+ };
diff --git a/dts/Bindings/sound/bt-sco.txt b/dts/Bindings/sound/bt-sco.txt
index 29b8e5d..641edf7 100644
--- a/dts/Bindings/sound/bt-sco.txt
+++ b/dts/Bindings/sound/bt-sco.txt
@@ -4,7 +4,7 @@ This device support generic Bluetooth SCO link.
Required properties:
- - compatible : "delta,dfbmcs320"
+ - compatible : "delta,dfbmcs320" or "linux,bt-sco"
Example:
diff --git a/dts/Bindings/sound/cs35l33.txt b/dts/Bindings/sound/cs35l33.txt
new file mode 100644
index 0000000..acfb475
--- /dev/null
+++ b/dts/Bindings/sound/cs35l33.txt
@@ -0,0 +1,126 @@
+CS35L33 Speaker Amplifier
+
+Required properties:
+
+ - compatible : "cirrus,cs35l33"
+
+ - reg : the I2C address of the device for I2C
+
+ - VA-supply, VP-supply : power supplies for the device,
+ as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+Optional properties:
+
+ - reset-gpios : gpio used to reset the amplifier
+
+ - interrupt-parent : Specifies the phandle of the interrupt controller to
+ which the IRQs from CS35L33 are delivered to.
+ - interrupts : IRQ line info CS35L33.
+ (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+ for further information relating to interrupt properties)
+
+ - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
+ 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
+ a value of 1 and will increase at a step size of 100mV until a maximum of
+ 8000mV.
+
+ - cirrus,ramp-rate : On power up, it affects the time from when the power
+ up sequence begins to the time the audio reaches a full-scale output.
+ On power down, it affects the time from when the power-down sequence
+ begins to when the amplifier disables the PWM outputs. If this property
+ is not set then soft ramping will be disabled and ramp time would be
+ 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
+ 60ms,100ms,175ms respectively for 48KHz sample rate.
+
+ - cirrus,boost-ipk : The maximum current allowed for the boost converter.
+ The range starts at 1850000uA and goes to a maximum of 3600000uA
+ with a step size of 15625uA. The default is 2500000uA.
+
+ - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON
+ ADC data word. This property can be set as a value of 0 for bits 15 down
+ to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
+
+
+Optional H/G Algorithm sub-node:
+
+The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
+the internal H/G Algorithm.
+
+ - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that
+ controls the amplifier supplies.
+
+Optional properties for the "cirrus,hg-algo" sub-node:
+
+ - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in
+ LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
+ depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
+
+ cirrus,release-rate : The number of consecutive LRCLK periods before
+ allowing release condition tracking updates. The number of LRCLK periods
+ start at 3 to a maximum of 255.
+
+ - cirrus,ldo-thld : Configures the signal threshold at which the PWM output
+ stage enters LDO operation. Starts as a default value of 50mV for a value
+ of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
+ 0xF).
+
+ - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G
+ algorithm uses the max detection path. If not present, the LDO
+ detection path is used.
+
+ - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G
+ algorithm switches to the LDO voltage. This property can be set to values
+ from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
+ The default is 100ms.
+
+ - cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg
+ automatic updating is enabled.
+
+ - cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's
+ reference to the VP voltage for when to start generating a boosted VBST.
+ The reference voltage starts at 3000mV with a value of 0x3 and is increased
+ by 100mV per step to a maximum of 5500mV.
+
+ - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
+ allowed to increase to a higher voltage when using VPhg automatic
+ tracking. This property can be set to values from 0 to 3 with rates of 128
+ periods, 2048 periods, 32768 periods, and 524288 periods.
+ The default is 32768 periods.
+
+ - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking
+ using VPMON. This property can be set to values from 0 to 6 starting at
+ 1800mV with a step size of 50mV up to a maximum value of 1750mV.
+ Default is 1800mV.
+
+Example:
+
+cs35l33: cs35l33@40 {
+ compatible = "cirrus,cs35l33";
+ reg = <0x40>;
+
+ VA-supply = <&ldo5_reg>;
+ VP-supply = <&ldo5_reg>;
+
+ interrupt-parent = <&gpio8>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&cs47l91 34 0>;
+
+ cirrus,ramp-rate = <0x0>;
+ cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */
+ cirrus,boost-ipk = <0xE0>; /* 3600mA */
+ cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */
+
+ cirrus,hg-algo {
+ cirrus,mem-depth = <0x3>;
+ cirrus,release-rate = <0x3>;
+ cirrus,ldo-thld = <0x1>;
+ cirrus,ldo-path-disable = <0x0>;
+ cirrus,ldo-entry-delay=<0x4>;
+ cirrus,vp-hg-auto;
+ cirrus,vp-hg=<0xF>;
+ cirrus,vp-hg-rate=<0x2>;
+ cirrus,vp-hg-va=<0x0>;
+ };
+};
diff --git a/dts/Bindings/sound/cs53l30.txt b/dts/Bindings/sound/cs53l30.txt
new file mode 100644
index 0000000..4dbfb82
--- /dev/null
+++ b/dts/Bindings/sound/cs53l30.txt
@@ -0,0 +1,44 @@
+CS53L30 audio CODEC
+
+Required properties:
+
+ - compatible : "cirrus,cs53l30"
+
+ - reg : the I2C address of the device
+
+ - VA-supply, VP-supply : power supplies for the device,
+ as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
+
+Optional properties:
+
+ - reset-gpios : a GPIO spec for the reset pin.
+
+ - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either
+ GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW, which would be handled
+ by the driver automatically.
+
+ - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin.
+ 0 = Hi-Z
+ 1 = 1.80 V
+ 2 = 2.75 V
+
+ - cirrus,use-sdout2 : This is a boolean property. If present, it indicates
+ the hardware design connects both SDOUT1 and SDOUT2
+ pins to output data. Otherwise, it indicates that
+ only SDOUT1 is connected for data output.
+ * CS53l30 supports 4-channel data output in the same
+ * frame using two different ways:
+ * 1) Normal I2S mode on two data pins -- each SDOUT
+ * carries 2-channel data in the same time.
+ * 2) TDM mode on one signle data pin -- SDOUT1 carries
+ * 4-channel data per frame.
+
+Example:
+
+codec: cs53l30@48 {
+ compatible = "cirrus,cs53l30";
+ reg = <0x48>;
+ reset-gpios = <&gpio 54 0>;
+ VA-supply = <&cs53l30_va>;
+ VP-supply = <&cs53l30_vp>;
+};
diff --git a/dts/Bindings/sound/designware-i2s.txt b/dts/Bindings/sound/designware-i2s.txt
index 7bb5424..6a536d5 100644
--- a/dts/Bindings/sound/designware-i2s.txt
+++ b/dts/Bindings/sound/designware-i2s.txt
@@ -12,6 +12,10 @@ Required properties:
one for receive.
- dma-names : "tx" for the transmit channel, "rx" for the receive channel.
+Optional properties:
+ - interrupts: The interrupt line number for the I2S controller. Add this
+ parameter if the I2S controller that you are using does not support DMA.
+
For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
properties please check:
* resource-names.txt
diff --git a/dts/Bindings/sound/fsl-asoc-card.txt b/dts/Bindings/sound/fsl-asoc-card.txt
index ceaef51..f749e27 100644
--- a/dts/Bindings/sound/fsl-asoc-card.txt
+++ b/dts/Bindings/sound/fsl-asoc-card.txt
@@ -58,7 +58,7 @@ Required properties:
* DMIC (stands for Digital Microphone Jack)
Note: The "Mic Jack" and "AMIC" are redundant while
- coexsiting in order to support the old bindings
+ coexisting in order to support the old bindings
of wm8962 and sgtl5000.
Optional properties:
diff --git a/dts/Bindings/sound/max98504.txt b/dts/Bindings/sound/max98504.txt
new file mode 100644
index 0000000..583ed5f
--- /dev/null
+++ b/dts/Bindings/sound/max98504.txt
@@ -0,0 +1,44 @@
+Maxim MAX98504 class D mono speaker amplifier
+
+This device supports I2C control interface and an IRQ output signal. It features
+a PCM and PDM digital audio interface (DAI) and a differential analog input.
+
+Required properties:
+
+ - compatible : "maxim,max98504"
+ - reg : should contain the I2C slave device address
+ - DVDD-supply, DIOVDD-supply, PVDD-supply: power supplies for the device,
+ as covered in ../regulator/regulator.txt
+ - interrupts : should specify the interrupt line the device is connected to,
+ as described in ../interrupt-controller/interrupts.txt
+
+Optional properties:
+
+ - maxim,brownout-threshold - the PVDD brownout threshold, the value must be
+ from 0, 1...21 range, corresponding to 2.6V, 2.65V...3.65V voltage range
+ - maxim,brownout-attenuation - the brownout attenuation to the speaker gain
+ applied during the "attack hold" and "timed hold" phase, the value must be
+ from 0...6 (dB) range
+ - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms,
+ 0...255 (VBATBROWN_ATTK_HOLD, register 0x0018)
+ - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms,
+ 0...255 (VBATBROWN_TIME_HOLD, register 0x0019)
+ - maxim,brownout-release-rate-ms - the brownout release phase step time in ms,
+ 0...255 (VBATBROWN_RELEASE, register 0x001A)
+
+The default value when the above properties are not specified is 0,
+the maxim,brownout-threshold property must be specified to actually enable
+the PVDD brownout protection.
+
+Example:
+
+ max98504@31 {
+ compatible = "maxim,max98504";
+ reg = <0x31>;
+ interrupt-parent = <&gpio_bank_0>;
+ interrupts = <2 0>;
+
+ DVDD-supply = <&regulator>;
+ DIOVDD-supply = <&regulator>;
+ PVDD-supply = <&regulator>;
+};
diff --git a/dts/Bindings/sound/max9860.txt b/dts/Bindings/sound/max9860.txt
new file mode 100644
index 0000000..e0d4e95
--- /dev/null
+++ b/dts/Bindings/sound/max9860.txt
@@ -0,0 +1,28 @@
+MAX9860 Mono Audio Voice Codec
+
+Required properties:
+
+ - compatible : "maxim,max9860"
+
+ - reg : the I2C address of the device
+
+ - AVDD-supply, DVDD-supply and DVDDIO-supply : power supplies for
+ the device, as covered in bindings/regulator/regulator.txt
+
+ - clock-names : Required element: "mclk".
+
+ - clocks : A clock specifier for the clock connected as MCLK.
+
+Examples:
+
+ max9860: max9860@10 {
+ compatible = "maxim,max9860";
+ reg = <0x10>;
+
+ AVDD-supply = <&reg_1v8>;
+ DVDD-supply = <&reg_1v8>;
+ DVDDIO-supply = <&reg_3v0>;
+
+ clock-names = "mclk";
+ clocks = <&pck2>;
+ };
diff --git a/dts/Bindings/sound/mt2701-afe-pcm.txt b/dts/Bindings/sound/mt2701-afe-pcm.txt
new file mode 100644
index 0000000..3e623a7
--- /dev/null
+++ b/dts/Bindings/sound/mt2701-afe-pcm.txt
@@ -0,0 +1,150 @@
+Mediatek AFE PCM controller for mt2701
+
+Required properties:
+- compatible = "mediatek,mt2701-audio";
+- reg: register location and size
+- interrupts: Should contain AFE interrupt
+- clock-names: should have these clock names:
+ "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_mux1_div",
+ "top_audio_mux2_div",
+ "top_audio_48k_timing",
+ "top_audio_44k_timing",
+ "top_audpll_mux_sel",
+ "top_apll_sel",
+ "top_aud1_pll_98M",
+ "top_aud2_pll_90M",
+ "top_hadds2_pll_98M",
+ "top_hadds2_pll_294M",
+ "top_audpll",
+ "top_audpll_d4",
+ "top_audpll_d8",
+ "top_audpll_d16",
+ "top_audpll_d24",
+ "top_audintbus_sel",
+ "clk_26m",
+ "top_syspll1_d4",
+ "top_aud_k1_src_sel",
+ "top_aud_k2_src_sel",
+ "top_aud_k3_src_sel",
+ "top_aud_k4_src_sel",
+ "top_aud_k5_src_sel",
+ "top_aud_k6_src_sel",
+ "top_aud_k1_src_div",
+ "top_aud_k2_src_div",
+ "top_aud_k3_src_div",
+ "top_aud_k4_src_div",
+ "top_aud_k5_src_div",
+ "top_aud_k6_src_div",
+ "top_aud_i2s1_mclk",
+ "top_aud_i2s2_mclk",
+ "top_aud_i2s3_mclk",
+ "top_aud_i2s4_mclk",
+ "top_aud_i2s5_mclk",
+ "top_aud_i2s6_mclk",
+ "top_asm_m_sel",
+ "top_asm_h_sel",
+ "top_univpll2_d4",
+ "top_univpll2_d2",
+ "top_syspll_d5";
+
+Example:
+
+ afe: mt2701-afe-pcm@11220000 {
+ compatible = "mediatek,mt2701-audio";
+ reg = <0 0x11220000 0 0x2000>,
+ <0 0x112A0000 0 0x20000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
+ <&topckgen CLK_TOP_APLL_SEL>,
+ <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>,
+ <&topckgen CLK_TOP_HADDS2PLL_98M>,
+ <&topckgen CLK_TOP_HADDS2PLL_294M>,
+ <&topckgen CLK_TOP_AUDPLL>,
+ <&topckgen CLK_TOP_AUDPLL_D4>,
+ <&topckgen CLK_TOP_AUDPLL_D8>,
+ <&topckgen CLK_TOP_AUDPLL_D16>,
+ <&topckgen CLK_TOP_AUDPLL_D24>,
+ <&topckgen CLK_TOP_AUDINTBUS_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_SYSPLL1_D4>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
+ <&topckgen CLK_TOP_ASM_M_SEL>,
+ <&topckgen CLK_TOP_ASM_H_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_UNIVPLL2_D2>,
+ <&topckgen CLK_TOP_SYSPLL_D5>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_mux1_div",
+ "top_audio_mux2_div",
+ "top_audio_48k_timing",
+ "top_audio_44k_timing",
+ "top_audpll_mux_sel",
+ "top_apll_sel",
+ "top_aud1_pll_98M",
+ "top_aud2_pll_90M",
+ "top_hadds2_pll_98M",
+ "top_hadds2_pll_294M",
+ "top_audpll",
+ "top_audpll_d4",
+ "top_audpll_d8",
+ "top_audpll_d16",
+ "top_audpll_d24",
+ "top_audintbus_sel",
+ "clk_26m",
+ "top_syspll1_d4",
+ "top_aud_k1_src_sel",
+ "top_aud_k2_src_sel",
+ "top_aud_k3_src_sel",
+ "top_aud_k4_src_sel",
+ "top_aud_k5_src_sel",
+ "top_aud_k6_src_sel",
+ "top_aud_k1_src_div",
+ "top_aud_k2_src_div",
+ "top_aud_k3_src_div",
+ "top_aud_k4_src_div",
+ "top_aud_k5_src_div",
+ "top_aud_k6_src_div",
+ "top_aud_i2s1_mclk",
+ "top_aud_i2s2_mclk",
+ "top_aud_i2s3_mclk",
+ "top_aud_i2s4_mclk",
+ "top_aud_i2s5_mclk",
+ "top_aud_i2s6_mclk",
+ "top_asm_m_sel",
+ "top_asm_h_sel",
+ "top_univpll2_d4",
+ "top_univpll2_d2",
+ "top_syspll_d5";
+ };
diff --git a/dts/Bindings/sound/mt2701-cs42448.txt b/dts/Bindings/sound/mt2701-cs42448.txt
new file mode 100644
index 0000000..0557444
--- /dev/null
+++ b/dts/Bindings/sound/mt2701-cs42448.txt
@@ -0,0 +1,43 @@
+MT2701 with CS42448 CODEC
+
+Required properties:
+- compatible: "mediatek,mt2701-cs42448-machine"
+- mediatek,platform: the phandle of MT2701 ASoC platform
+- audio-routing: a list of the connections between audio
+- mediatek,audio-codec: the phandles of cs42448 codec
+- mediatek,audio-codec-bt-mrg the phandles of bt-sco dummy codec
+- pinctrl-names: Should contain only one value - "default"
+- pinctrl-0: Should specify pin control groups used for this controller.
+- i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to
+ control I2S1-in mux.
+
+Example:
+
+ sound:sound {
+ compatible = "mediatek,mt2701-cs42448-machine";
+ mediatek,platform = <&afe>;
+ /* CS42448 Machine name */
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "AMIC",
+ "AIN1R", "AMIC",
+ "AIN2L", "Tuner In",
+ "AIN2R", "Tuner In",
+ "AIN3L", "Satellite Tuner In",
+ "AIN3R", "Satellite Tuner In",
+ "AIN3L", "AUX In",
+ "AIN3R", "AUX In";
+ mediatek,audio-codec = <&cs42448>;
+ mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&aud_pins_default>;
+ i2s1-in-sel-gpio1 = <&pio 53 0>;
+ i2s1-in-sel-gpio2 = <&pio 54 0>;
+ };
diff --git a/dts/Bindings/sound/mt8173-rt5650.txt b/dts/Bindings/sound/mt8173-rt5650.txt
index 5bfa6b6..29dce2a 100644
--- a/dts/Bindings/sound/mt8173-rt5650.txt
+++ b/dts/Bindings/sound/mt8173-rt5650.txt
@@ -1,8 +1,9 @@
-MT8173 with RT5650 CODECS
+MT8173 with RT5650 CODECS and HDMI via I2S
Required properties:
- compatible : "mediatek,mt8173-rt5650"
- mediatek,audio-codec: the phandles of rt5650 codecs
+ and of the hdmi encoder node
- mediatek,platform: the phandle of MT8173 ASoC platform
Optional subnodes:
@@ -12,12 +13,17 @@ Required codec-capture subnode properties:
<&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1)
<&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2)
+- mediatek,mclk: the MCLK source
+ 0 : external oscillator, MCLK = 12.288M
+ 1 : internal source from mt8173, MCLK = sampling rate*256
+
Example:
sound {
compatible = "mediatek,mt8173-rt5650";
- mediatek,audio-codec = <&rt5650>;
+ mediatek,audio-codec = <&rt5650 &hdmi0>;
mediatek,platform = <&afe>;
+ mediatek,mclk = <0>;
codec-capture {
sound-dai = <&rt5650 1>;
};
diff --git a/dts/Bindings/sound/omap-mcpdm.txt b/dts/Bindings/sound/omap-mcpdm.txt
index 0741dff..6f6c2f8 100644
--- a/dts/Bindings/sound/omap-mcpdm.txt
+++ b/dts/Bindings/sound/omap-mcpdm.txt
@@ -8,6 +8,8 @@ Required properties:
- interrupts: Interrupt number for McPDM
- interrupt-parent: The parent interrupt controller
- ti,hwmods: Name of the hwmod associated to the McPDM
+- clocks: phandle for the pdmclk provider, likely <&twl6040>
+- clock-names: Must be "pdmclk"
Example:
@@ -19,3 +21,11 @@ mcpdm: mcpdm@40132000 {
interrupt-parent = <&gic>;
ti,hwmods = "mcpdm";
};
+
+In board DTS file the pdmclk needs to be added:
+
+&mcpdm {
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+ status = "okay";
+};
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index c7b29df..15a7316 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -373,6 +373,8 @@ Optional properties:
- #clock-cells : it must be 0 if your system has audio_clkout
it must be 1 if your system has audio_clkout0/1/2/3
- clock-frequency : for all audio_clkout0/1/2/3
+- clkout-lr-asynchronous : boolean property. it indicates that audio_clkoutn
+ is asynchronizes with lr-clock.
SSI subnode properties:
- interrupts : Should contain SSI interrupt for PIO transfer
diff --git a/dts/Bindings/sound/rockchip-i2s.txt b/dts/Bindings/sound/rockchip-i2s.txt
index 6e86d8a..4ea29aa 100644
--- a/dts/Bindings/sound/rockchip-i2s.txt
+++ b/dts/Bindings/sound/rockchip-i2s.txt
@@ -23,6 +23,11 @@ Required properties:
- rockchip,playback-channels: max playback channels, if not set, 8 channels default.
- rockchip,capture-channels: max capture channels, if not set, 2 channels default.
+Required properties for controller which support multi channels
+playback/capture:
+
+- rockchip,grf: the phandle of the syscon node for GRF register.
+
Example for rk3288 I2S controller:
i2s@ff890000 {
diff --git a/dts/Bindings/sound/rt5514.txt b/dts/Bindings/sound/rt5514.txt
index e24436f..9cabfc1 100644
--- a/dts/Bindings/sound/rt5514.txt
+++ b/dts/Bindings/sound/rt5514.txt
@@ -8,6 +8,11 @@ Required properties:
- reg : The I2C address of the device.
+Optional properties:
+
+- clocks: The phandle of the master clock to the CODEC
+- clock-names: Should be "mclk"
+
Pins on the device (for linking into audio routes) for RT5514:
* DMIC1L
diff --git a/dts/Bindings/sound/samsung,odroidx2-max98090.txt b/dts/Bindings/sound/samsung,odroidx2-max98090.txt
deleted file mode 100644
index 9148f72..0000000
--- a/dts/Bindings/sound/samsung,odroidx2-max98090.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Samsung Exynos Odroid X2/U3 audio complex with MAX98090 codec
-
-Required properties:
- - compatible : "samsung,odroidx2-audio" - for Odroid X2 board,
- "samsung,odroidu3-audio" - for Odroid U3 board
- - samsung,model : the user-visible name of this sound complex
- - samsung,i2s-controller : the phandle of the I2S controller
- - samsung,audio-codec : the phandle of the MAX98090 audio codec
- - samsung,audio-routing : a list of the connections between audio
- components; each entry is a pair of strings, the first being the
- connection's sink, the second being the connection's source;
- valid names for sources and sinks are the MAX98090's pins (as
- documented in its binding), and the jacks on the board
- For Odroid X2:
- * Headphone Jack
- * Mic Jack
- * DMIC
-
- For Odroid U3:
- * Headphone Jack
- * Speakers
-
-Example:
-
-sound {
- compatible = "samsung,odroidu3-audio";
- samsung,i2s-controller = <&i2s0>;
- samsung,audio-codec = <&max98090>;
- samsung,model = "Odroid-X2";
- samsung,audio-routing =
- "Headphone Jack", "HPL",
- "Headphone Jack", "HPR",
- "IN1", "Mic Jack",
- "Mic Jack", "MICBIAS";
-};
diff --git a/dts/Bindings/sound/sgtl5000.txt b/dts/Bindings/sound/sgtl5000.txt
index 0e5e4eb..5666da7 100644
--- a/dts/Bindings/sound/sgtl5000.txt
+++ b/dts/Bindings/sound/sgtl5000.txt
@@ -7,6 +7,14 @@ Required properties:
- clocks : the clock provider of SYS_MCLK
+- VDDA-supply : the regulator provider of VDDA
+
+- VDDIO-supply: the regulator provider of VDDIO
+
+Optional properties:
+
+- VDDD-supply : the regulator provider of VDDD
+
- micbias-resistor-k-ohms : the bias resistor to be used in kOmhs
The resistor can take values of 2k, 4k or 8k.
If set to 0 it will be off.
@@ -15,17 +23,9 @@ Required properties:
- micbias-voltage-m-volts : the bias voltage to be used in mVolts
The voltage can take values from 1.25V to 3V by 250mV steps
- If this node is not mentionned or the value is unknown, then
+ If this node is not mentioned or the value is unknown, then
the value is set to 1.25V.
-- VDDA-supply : the regulator provider of VDDA
-
-- VDDIO-supply: the regulator provider of VDDIO
-
-Optional properties:
-
-- VDDD-supply : the regulator provider of VDDD
-
Example:
codec: sgtl5000@0a {
diff --git a/dts/Bindings/sound/simple-card.txt b/dts/Bindings/sound/simple-card.txt
index cf3979e..59d8628 100644
--- a/dts/Bindings/sound/simple-card.txt
+++ b/dts/Bindings/sound/simple-card.txt
@@ -30,7 +30,7 @@ Optional subnodes:
sub-nodes. This container may be
omitted when the card has only one
DAI link. See the examples and the
- section bellow.
+ section below.
Dai-link subnode properties and subnodes:
diff --git a/dts/Bindings/sound/st,sti-asoc-card.txt b/dts/Bindings/sound/st,sti-asoc-card.txt
index 4d9a83d..16bcdfb 100644
--- a/dts/Bindings/sound/st,sti-asoc-card.txt
+++ b/dts/Bindings/sound/st,sti-asoc-card.txt
@@ -33,11 +33,11 @@ Required properties:
"tx" for "st,sti-uni-player" compatibility
"rx" for "st,sti-uni-reader" compatibility
- - version: IP version integrated in SOC.
+ - st,version: IP version integrated in SOC.
- dai-name: DAI name that describes the IP.
- - IP mode: IP working mode depending on associated codec.
+ - st,mode: IP working mode depending on associated codec.
"HDMI" connected to HDMI codec and support IEC HDMI formats (player only).
"SPDIF" connected to SPDIF codec and support SPDIF formats (player only).
"PCM" PCM standard mode for I2S or TDM bus.
@@ -47,7 +47,7 @@ Required properties ("st,sti-uni-player" compatibility only):
- clocks: CPU_DAI IP clock source, listed in the same order than the
CPU_DAI properties.
- - uniperiph-id: internal SOC IP instance ID.
+ - st,uniperiph-id: internal SOC IP instance ID.
Optional properties:
- pinctrl-0: defined for CPU_DAI@1 and CPU_DAI@4 to describe I2S PIOs for
@@ -84,9 +84,9 @@ Example:
dmas = <&fdma0 4 0 1>;
dai-name = "Uni Player #2 (DAC)";
dma-names = "tx";
- uniperiph-id = <2>;
- version = <5>;
- mode = "PCM";
+ st,uniperiph-id = <2>;
+ st,version = <5>;
+ st,mode = "PCM";
};
sti_uni_player3: sti-uni-player@3 {
@@ -100,9 +100,9 @@ Example:
dmas = <&fdma0 7 0 1>;
dma-names = "tx";
dai-name = "Uni Player #3 (SPDIF)";
- uniperiph-id = <3>;
- version = <5>;
- mode = "SPDIF";
+ st,uniperiph-id = <3>;
+ st,version = <5>;
+ st,mode = "SPDIF";
};
sti_uni_reader1: sti-uni-reader@1 {
@@ -115,7 +115,7 @@ Example:
dmas = <&fdma0 6 0 1>;
dma-names = "rx";
dai-name = "Uni Reader #1 (HDMI RX)";
- version = <3>;
+ st,version = <3>;
st,mode = "PCM";
};
diff --git a/dts/Bindings/sound/sun4i-i2s.txt b/dts/Bindings/sound/sun4i-i2s.txt
new file mode 100644
index 0000000..7b526ec
--- /dev/null
+++ b/dts/Bindings/sound/sun4i-i2s.txt
@@ -0,0 +1,34 @@
+* Allwinner A10 I2S controller
+
+The I2S bus (Inter-IC sound bus) is a serial link for digital
+audio data transfer between devices in the system.
+
+Required properties:
+
+- compatible: should be one of the followings
+ - "allwinner,sun4i-a10-i2s"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: should contain the I2S interrupt.
+- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: should include "tx" and "rx".
+- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
+- clock-names: should contain followings:
+ - "apb" : clock for the I2S bus interface
+ - "mod" : module clock for the I2S controller
+- #sound-dai-cells : Must be equal to 0
+
+Example:
+
+i2s0: i2s@01c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 3>, <&i2s0_clk>;
+ clock-names = "apb", "mod";
+ dmas = <&dma SUN4I_DMA_NORMAL 3>,
+ <&dma SUN4I_DMA_NORMAL 3>;
+ dma-names = "rx", "tx";
+};
diff --git a/dts/Bindings/spi/fsl-imx-cspi.txt b/dts/Bindings/spi/fsl-imx-cspi.txt
index 523341a..8bc95e2 100644
--- a/dts/Bindings/spi/fsl-imx-cspi.txt
+++ b/dts/Bindings/spi/fsl-imx-cspi.txt
@@ -11,7 +11,6 @@ Required properties:
- "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
- reg : Offset and length of the register set for the device
- interrupts : Should contain CSPI/eCSPI interrupt
-- fsl,spi-num-chipselects : Contains the number of the chipselect
- cs-gpios : Specifies the gpio pins to be used for chipselects.
- clocks : Clock specifiers for both ipg and per clocks.
- clock-names : Clock names should include both "ipg" and "per"
@@ -21,6 +20,9 @@ See the clock consumer binding,
Documentation/devicetree/bindings/dma/dma.txt
- dma-names: DMA request names should include "tx" and "rx" if present.
+Obsolete properties:
+- fsl,spi-num-chipselects : Contains the number of the chipselect
+
Example:
ecspi@70010000 {
@@ -29,7 +31,6 @@ ecspi@70010000 {
compatible = "fsl,imx51-ecspi";
reg = <0x70010000 0x4000>;
interrupts = <36>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
<&gpio3 25 0>; /* GPIO3_25 */
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
diff --git a/dts/Bindings/spi/spi-bus.txt b/dts/Bindings/spi/spi-bus.txt
index 42d5954..1782286 100644
--- a/dts/Bindings/spi/spi-bus.txt
+++ b/dts/Bindings/spi/spi-bus.txt
@@ -8,11 +8,10 @@ in slave mode.
The SPI master node requires the following properties:
- #address-cells - number of cells required to define a chip select
- address on the SPI bus.
+ address on the SPI bus.
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
- recommended practice.
-- cs-gpios - (optional) gpios chip select.
+ recommended practice.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
@@ -22,11 +21,12 @@ assumption that board specific platform code will be used to manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
-Optional property:
-- num-cs : total number of chipselects
+Optional properties:
+- cs-gpios - gpios chip select.
+- num-cs - total number of chipselects.
-If cs-gpios is used the number of chip select will automatically increased
-with max(cs-gpios > hw cs)
+If cs-gpios is used the number of chip selects will be increased automatically
+with max(cs-gpios > hw cs).
So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:
@@ -45,29 +45,30 @@ SPI slave nodes must be children of the SPI master node and can
contain the following properties.
- reg - (required) chip select address of device.
- compatible - (required) name of SPI device following generic names
- recommended practice
-- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
+ recommended practice.
+- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz.
- spi-cpol - (optional) Empty property indicating device requires
- inverse clock polarity (CPOL) mode
+ inverse clock polarity (CPOL) mode.
- spi-cpha - (optional) Empty property indicating device requires
- shifted clock phase (CPHA) mode
+ shifted clock phase (CPHA) mode.
- spi-cs-high - (optional) Empty property indicating device requires
- chip select active high
+ chip select active high.
- spi-3wire - (optional) Empty property indicating device requires
- 3-wire mode.
+ 3-wire mode.
- spi-lsb-first - (optional) Empty property indicating device requires
LSB first mode.
-- spi-tx-bus-width - (optional) The bus width(number of data wires) that
+- spi-tx-bus-width - (optional) The bus width (number of data wires) that is
used for MOSI. Defaults to 1 if not present.
-- spi-rx-bus-width - (optional) The bus width(number of data wires) that
+- spi-rx-bus-width - (optional) The bus width (number of data wires) that is
used for MISO. Defaults to 1 if not present.
- spi-rx-delay-us - (optional) Microsecond delay after a read transfer.
- spi-tx-delay-us - (optional) Microsecond delay after a write transfer.
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
-It allows data in the SPI system to be transferred in 2 wires(DUAL) or 4 wires(QUAD).
+It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
+wires (QUAD).
Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
-only 1(SINGLE), 2(DUAL) and 4(QUAD).
+only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
Dual/Quad mode is not allowed when 3-wire mode is used.
If a gpio chipselect is used for the SPI slave the gpio number will be passed
diff --git a/dts/Bindings/spi/spi-clps711x.txt b/dts/Bindings/spi/spi-clps711x.txt
new file mode 100644
index 0000000..4c3ec13
--- /dev/null
+++ b/dts/Bindings/spi/spi-clps711x.txt
@@ -0,0 +1,33 @@
+Serial Peripheral Interface on Cirrus Logic CL-PS71xx, EP72xx, EP73xx
+
+Required properties
+- #address-cells: must be <1>
+- #size-cells: must be <0>
+- compatible: should include "cirrus,ep7209-spi"
+- reg: Address and length of one register range
+- interrupts: one interrupt line
+- clocks: One entry, refers to the SPI bus clock
+- cs-gpios: Specifies the gpio pins to be used for chipselects.
+ See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+An additional register is present in the system controller,
+which is assumed to be in the same device tree, with and marked
+as compatible with "cirrus,ep7209-syscon3".
+
+Example:
+
+spi@80000500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cirrus,ep7209-spi";
+ reg = <0x80000500 0x4>;
+ interrupts = <15>;
+ clocks = <&clks CLPS711X_CLK_SPI>;
+ status = "disabled";
+};
+
+syscon3: syscon@80002200 {
+ compatible = "cirrus,ep7209-syscon3", "syscon";
+ reg = <0x80002200 0x40>;
+};
+
diff --git a/dts/Bindings/spi/spi-davinci.txt b/dts/Bindings/spi/spi-davinci.txt
index d1e914a..f5916c9 100644
--- a/dts/Bindings/spi/spi-davinci.txt
+++ b/dts/Bindings/spi/spi-davinci.txt
@@ -21,7 +21,7 @@ Required properties:
IP to the interrupt controller within the SoC. Possible values
are 0 and 1. Manual says one of the two possible interrupt
lines can be tied to the interrupt controller. Set this
- based on a specifc SoC configuration.
+ based on a specific SoC configuration.
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
diff --git a/dts/Bindings/spi/spi-orion.txt b/dts/Bindings/spi/spi-orion.txt
index 98bc698..4f629cc 100644
--- a/dts/Bindings/spi/spi-orion.txt
+++ b/dts/Bindings/spi/spi-orion.txt
@@ -8,7 +8,15 @@ Required properties:
- "marvell,armada-380-spi", for the Armada 38x SoCs
- "marvell,armada-390-spi", for the Armada 39x SoCs
- "marvell,armada-xp-spi", for the Armada XP SoCs
-- reg : offset and length of the register set for the device
+- reg : offset and length of the register set for the device.
+ This property can optionally have additional entries to configure
+ the SPI direct access mode that some of the Marvell SoCs support
+ additionally to the normal indirect access (PIO) mode. The values
+ for the MBus "target" and "attribute" are defined in the Marvell
+ SoC "Functional Specifications" Manual in the chapter "Marvell
+ Core Processor Address Decoding".
+ The eight register sets following the control registers refer to
+ chip-select lines 0 through 7 respectively.
- cell-index : Which of multiple SPI controllers is this.
Optional properties:
- interrupts : Is currently not used.
@@ -23,3 +31,42 @@ Example:
interrupts = <23>;
status = "disabled";
};
+
+Example with SPI direct mode support (optionally):
+ spi0: spi@10600 {
+ compatible = "marvell,orion-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
+ <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
+ <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
+ <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
+ <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
+ <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
+ <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
+ <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
+ <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
+ interrupts = <23>;
+ status = "disabled";
+ };
+
+To enable the direct mode, the board specific 'ranges' property in the
+'soc' node needs to add the entries for the desired SPI controllers
+and its chip-selects that are used in the direct mode instead of PIO
+mode. Here an example for this (SPI controller 0, device 1 and SPI
+controller 1, device 2 are used in direct mode. All other SPI device
+are used in the default indirect (PIO) mode):
+ soc {
+ /*
+ * Enable the SPI direct access by configuring an entry
+ * here in the board-specific ranges property
+ */
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
+ <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */
+ <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
+ <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */
+
+For further information on the MBus bindings, please see the MBus
+DT documentation:
+Documentation/devicetree/bindings/bus/mvebu-mbus.txt
diff --git a/dts/Bindings/spi/spi-rockchip.txt b/dts/Bindings/spi/spi-rockchip.txt
index 1b14d69..d2ca153 100644
--- a/dts/Bindings/spi/spi-rockchip.txt
+++ b/dts/Bindings/spi/spi-rockchip.txt
@@ -6,10 +6,13 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
- "rockchip,rk3066-spi" for rk3066.
- "rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.
- "rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.
- "rockchip,rk3399-spi", "rockchip,rk3066-spi" for rk3399.
+ "rockchip,rk3036-spi" for rk3036 SoCS.
+ "rockchip,rk3066-spi" for rk3066 SoCs.
+ "rockchip,rk3188-spi" for rk3188 SoCs.
+ "rockchip,rk3228-spi" for rk3228 SoCS.
+ "rockchip,rk3288-spi" for rk3288 SoCs.
+ "rockchip,rk3368-spi" for rk3368 SoCs.
+ "rockchip,rk3399-spi" for rk3399 SoCs.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The interrupt number to the cpu. The interrupt specifier format
diff --git a/dts/Bindings/spi/spi-samsung.txt b/dts/Bindings/spi/spi-samsung.txt
index 6dbdeb3..49028a4 100644
--- a/dts/Bindings/spi/spi-samsung.txt
+++ b/dts/Bindings/spi/spi-samsung.txt
@@ -9,7 +9,8 @@ Required SoC Specific Properties:
- samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
- samsung,s3c6410-spi: for s3c6410 platforms
- samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
- - samsung,exynos7-spi: for exynos7 platforms
+ - samsung,exynos5433-spi: for exynos5433 compatible controllers
+ - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
- reg: physical base address of the controller and length of memory mapped
region.
@@ -23,6 +24,15 @@ Required SoC Specific Properties:
- dma-names: Names for the dma channels. There must be at least one channel
named "tx" for transmit and named "rx" for receive.
+- clocks: specifies the clock IDs provided to the SPI controller; they are
+ required for interacting with the controller itself, for synchronizing the bus
+ and as I/O clock (the latter is required by exynos5433 and exynos7).
+
+- clock-names: string names of the clocks in the 'clocks' property; for all the
+ the devices the names must be "spi", "spi_busclkN" (where N is determined by
+ "samsung,spi-src-clk"), while Exynos5433 should specify a third clock
+ "spi_ioclk" for the I/O clock.
+
Required Board Specific Properties:
- #address-cells: should be 1.
@@ -40,6 +50,9 @@ Optional Board Specific Properties:
- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
+- no-cs-readback: the CS line is disconnected, therefore the device should not
+ operate based on CS signalling.
+
SPI Controller specific data in SPI slave nodes:
- The spi slave nodes should provide the following information which is required
diff --git a/dts/Bindings/spi/ti_qspi.txt b/dts/Bindings/spi/ti_qspi.txt
index 50b14f6..e65fde4 100644
--- a/dts/Bindings/spi/ti_qspi.txt
+++ b/dts/Bindings/spi/ti_qspi.txt
@@ -20,7 +20,7 @@ Optional properties:
chipselect register and offset of that register.
NOTE: TI QSPI controller requires different pinmux and IODelay
-paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
+parameters for Mode-0 and Mode-3 operations, which needs to be set up by
the bootloader (U-Boot). Default configuration only supports Mode-0
operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
specified in the slave nodes of TI QSPI controller without appropriate
diff --git a/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.txt b/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.txt
index 27cfc7d..8d6e4fd 100644
--- a/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.txt
+++ b/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.txt
@@ -9,7 +9,7 @@ Required properties:
one)
- clocks: phandle to the source clock (usually the AHB clock)
-Optionnal properties:
+Optional properties:
- resets: phandle to a reset controller asserting the timer
Example:
diff --git a/dts/Bindings/timer/cirrus,clps711x-timer.txt b/dts/Bindings/timer/cirrus,clps711x-timer.txt
index cd55b52..d4c62e7 100644
--- a/dts/Bindings/timer/cirrus,clps711x-timer.txt
+++ b/dts/Bindings/timer/cirrus,clps711x-timer.txt
@@ -1,7 +1,7 @@
* Cirrus Logic CLPS711X Timer Counter
Required properties:
-- compatible: Shall contain "cirrus,clps711x-timer".
+- compatible: Shall contain "cirrus,ep7209-timer".
- reg : Address and length of the register set.
- interrupts: The interrupt number of the timer.
- clocks : phandle of timer reference clock.
@@ -15,14 +15,14 @@ Example:
};
timer1: timer@80000300 {
- compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer";
+ compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
reg = <0x80000300 0x4>;
interrupts = <8>;
clocks = <&clks 5>;
};
timer2: timer@80000340 {
- compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer";
+ compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
reg = <0x80000340 0x4>;
interrupts = <9>;
clocks = <&clks 6>;
diff --git a/dts/Bindings/timer/oxsemi,rps-timer.txt b/dts/Bindings/timer/oxsemi,rps-timer.txt
new file mode 100644
index 0000000..3ca89cd
--- /dev/null
+++ b/dts/Bindings/timer/oxsemi,rps-timer.txt
@@ -0,0 +1,17 @@
+Oxford Semiconductor OXNAS SoCs Family RPS Timer
+================================================
+
+Required properties:
+- compatible: Should be "oxsemi,ox810se-rps-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupts of the two timers
+- clocks : The phandle of the timer clock source
+
+example:
+
+timer0: timer@200 {
+ compatible = "oxsemi,ox810se-rps-timer";
+ reg = <0x200 0x40>;
+ clocks = <&rpsclk>;
+ interrupts = <4 5>;
+};
diff --git a/dts/Bindings/timer/rockchip,rk3288-timer.txt b/dts/Bindings/timer/rockchip,rk-timer.txt
index 87f0b00..a41b184 100644
--- a/dts/Bindings/timer/rockchip,rk3288-timer.txt
+++ b/dts/Bindings/timer/rockchip,rk-timer.txt
@@ -1,7 +1,9 @@
-Rockchip rk3288 timer
+Rockchip rk timer
Required properties:
-- compatible: shall be "rockchip,rk3288-timer"
+- compatible: shall be one of:
+ "rockchip,rk3288-timer" - for rk3066, rk3036, rk3188, rk322x, rk3288, rk3368
+ "rockchip,rk3399-timer" - for rk3399
- reg: base address of the timer register starting with TIMERS CONTROL register
- interrupts: should contain the interrupts for Timer0
- clocks : must contain an entry for each entry in clock-names
diff --git a/dts/Bindings/ufs/tc-dwc-g210-pltfrm.txt b/dts/Bindings/ufs/tc-dwc-g210-pltfrm.txt
new file mode 100644
index 0000000..71c0777
--- /dev/null
+++ b/dts/Bindings/ufs/tc-dwc-g210-pltfrm.txt
@@ -0,0 +1,26 @@
+* Universal Flash Storage (UFS) DesignWare Host Controller
+
+DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible : compatible list must contain the PHY type & version:
+ "snps,g210-tc-6.00-20bit"
+ "snps,g210-tc-6.00-40bit"
+ complemented with the Controller IP version:
+ "snps,dwc-ufshcd-1.40a"
+ complemented with the JEDEC version:
+ "jedec,ufs-1.1"
+ "jedec,ufs-2.0"
+
+- reg : <registers mapping>
+- interrupts : <interrupt mapping for UFS host controller IRQ>
+
+Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
+ dwc-ufs@d0000000 {
+ compatible = "snps,g210-tc-6.00-40bit",
+ "snps,dwc-ufshcd-1.40a",
+ "jedec,ufs-2.0";
+ reg = < 0xd0000000 0x10000 >;
+ interrupts = < 24 >;
+ };
diff --git a/dts/Bindings/ufs/ufshcd-pltfrm.txt b/dts/Bindings/ufs/ufshcd-pltfrm.txt
index 66f6adf..a99ed55 100644
--- a/dts/Bindings/ufs/ufshcd-pltfrm.txt
+++ b/dts/Bindings/ufs/ufshcd-pltfrm.txt
@@ -4,8 +4,8 @@ UFSHC nodes are defined to describe on-chip UFS host controllers.
Each UFS controller instance should have its own node.
Required properties:
-- compatible : must contain "jedec,ufs-1.1", may also list one or more
- of the following:
+- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may
+ also list one or more of the following:
"qcom,msm8994-ufshc"
"qcom,msm8996-ufshc"
"qcom,ufshc"
diff --git a/dts/Bindings/usb/atmel-usb.txt b/dts/Bindings/usb/atmel-usb.txt
index 5883b73..f4262ed 100644
--- a/dts/Bindings/usb/atmel-usb.txt
+++ b/dts/Bindings/usb/atmel-usb.txt
@@ -113,13 +113,13 @@ usb2: gadget@fff78000 {
clock-names = "hclk", "pclk";
atmel,vbus-gpio = <&pioB 19 0>;
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@@ -127,7 +127,7 @@ usb2: gadget@fff78000 {
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@@ -135,21 +135,21 @@ usb2: gadget@fff78000 {
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@@ -157,7 +157,7 @@ usb2: gadget@fff78000 {
atmel,can-isoc;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
diff --git a/dts/Bindings/usb/ci-hdrc-usb2.txt b/dts/Bindings/usb/ci-hdrc-usb2.txt
index 1084e2b..341dc67 100644
--- a/dts/Bindings/usb/ci-hdrc-usb2.txt
+++ b/dts/Bindings/usb/ci-hdrc-usb2.txt
@@ -93,7 +93,7 @@ Example:
phys = <&usb_phy0>;
phy-names = "usb-phy";
vbus-supply = <&reg_usb0_vbus>;
- gadget-itc-setting = <0x4>; /* 4 micro-frames */
+ itc-setting = <0x4>; /* 4 micro-frames */
/* Incremental burst of unspecified length */
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>; /* 64 bytes */
diff --git a/dts/Bindings/usb/nvidia,tegra124-xusb.txt b/dts/Bindings/usb/nvidia,tegra124-xusb.txt
index d28295a..3eee9e5 100644
--- a/dts/Bindings/usb/nvidia,tegra124-xusb.txt
+++ b/dts/Bindings/usb/nvidia,tegra124-xusb.txt
@@ -104,10 +104,10 @@ Example:
nvidia,xusb-padctl = <&padctl>;
- phys = <&{/padctl@0,7009f000/pads/usb2/usb2-1}>, /* mini-PCIe USB */
- <&{/padctl@0,7009f000/pads/usb2/usb2-2}>, /* USB A */
- <&{/padctl@0,7009f000/pads/pcie/pcie-0}>; /* USB A */
- phy-names = "utmi-1", "utmi-2", "usb3-0";
+ phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
+ <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
+ <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
+ phy-names = "usb2-1", "usb2-2", "usb3-0";
avddio-pex-supply = <&vdd_1v05_run>;
dvddio-pex-supply = <&vdd_1v05_run>;
diff --git a/dts/Bindings/usb/usb-ohci.txt b/dts/Bindings/usb/usb-ohci.txt
index 19233b7..9df4569 100644
--- a/dts/Bindings/usb/usb-ohci.txt
+++ b/dts/Bindings/usb/usb-ohci.txt
@@ -14,7 +14,7 @@ Optional properties:
- clocks : a list of phandle + clock specifier pairs
- phys : phandle + phy specifier pair
- phy-names : "usb"
-- resets : phandle + reset specifier pair
+- resets : a list of phandle + reset specifier pairs
Example:
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index 2c2500d..1992aa9 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -128,6 +128,7 @@ idt Integrated Device Technologies, Inc.
ifi Ingenieurburo Fur Ic-Technologie (I/F/I)
iom Iomega Corporation
img Imagination Technologies Ltd.
+infineon Infineon Technologies
inforce Inforce Computing
ingenic Ingenic Semiconductor
innolux Innolux Corporation
@@ -214,6 +215,7 @@ raidsonic RaidSonic Technology GmbH
ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International
raspberrypi Raspberry Pi Foundation
+raydium Raydium Semiconductor Corp.
realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation
richtek Richtek Technology Corporation
@@ -236,6 +238,7 @@ simtek
sii Seiko Instruments, Inc.
silergy Silergy Corp.
sirf SiRF Technology, Inc.
+sis Silicon Integrated Systems Corp.
sitronix Sitronix Technology Corporation
skyworks Skyworks Solutions, Inc.
smsc Standard Microsystems Corporation
@@ -247,6 +250,7 @@ sony Sony Corporation
spansion Spansion Inc.
sprd Spreadtrum Communications Inc.
st STMicroelectronics
+starry Starry Electronic Technology (ShenZhen) Co., LTD
startek Startek
ste ST-Ericsson
stericsson ST-Ericsson
@@ -254,6 +258,7 @@ syna Synaptics Inc.
synology Synology, Inc.
SUNW Sun Microsystems, Inc
tbs TBS Technologies
+tcg Trusted Computing Group
tcl Toby Churchill Ltd.
technexion TechNexion
technologic Technologic Systems
diff --git a/dts/Bindings/watchdog/aspeed-wdt.txt b/dts/Bindings/watchdog/aspeed-wdt.txt
new file mode 100644
index 0000000..c5e74d7
--- /dev/null
+++ b/dts/Bindings/watchdog/aspeed-wdt.txt
@@ -0,0 +1,16 @@
+Aspeed Watchdog Timer
+
+Required properties:
+ - compatible: must be one of:
+ - "aspeed,ast2400-wdt"
+ - "aspeed,ast2500-wdt"
+
+ - reg: physical base address of the controller and length of memory mapped
+ region
+
+Example:
+
+ wdt1: watchdog@1e785000 {
+ compatible = "aspeed,ast2400-wdt";
+ reg = <0x1e785000 0x1c>;
+ };
diff --git a/dts/Bindings/watchdog/meson-gxbb-wdt.txt b/dts/Bindings/watchdog/meson-gxbb-wdt.txt
new file mode 100644
index 0000000..c7fe36f
--- /dev/null
+++ b/dts/Bindings/watchdog/meson-gxbb-wdt.txt
@@ -0,0 +1,16 @@
+Meson GXBB SoCs Watchdog timer
+
+Required properties:
+
+- compatible : should be "amlogic,meson-gxbb-wdt"
+- reg : Specifies base physical address and size of the registers.
+- clocks : Should be a phandle to the Watchdog clock source, for GXBB the xtal
+ is the default clock source.
+
+Example:
+
+wdt: watchdog@98d0 {
+ compatible = "amlogic,meson-gxbb-wdt";
+ reg = <0 0x98d0 0x0 0x10>;
+ clocks = <&xtal>;
+};
diff --git a/dts/Bindings/watchdog/qcom-wdt.txt b/dts/Bindings/watchdog/qcom-wdt.txt
index 4726924..41aeaa2 100644
--- a/dts/Bindings/watchdog/qcom-wdt.txt
+++ b/dts/Bindings/watchdog/qcom-wdt.txt
@@ -7,6 +7,10 @@ Required properties :
"qcom,kpss-wdt-msm8960"
"qcom,kpss-wdt-apq8064"
"qcom,kpss-wdt-ipq8064"
+ "qcom,kpss-wdt-ipq4019"
+ "qcom,kpss-timer"
+ "qcom,scss-timer"
+ "qcom,kpss-wdt"
- reg : shall contain base register location and length
- clocks : shall contain the input clock
diff --git a/dts/Bindings/watchdog/renesas-wdt.txt b/dts/Bindings/watchdog/renesas-wdt.txt
index b9512f1..da24e31 100644
--- a/dts/Bindings/watchdog/renesas-wdt.txt
+++ b/dts/Bindings/watchdog/renesas-wdt.txt
@@ -1,7 +1,11 @@
Renesas Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be "renesas,r8a7795-wdt", or "renesas,rcar-gen3-wdt"
+- compatible : Should be "renesas,<soctype>-wdt", and
+ "renesas,rcar-gen3-wdt" as fallback.
+ Examples with soctypes are:
+ - "renesas,r8a7795-wdt" (R-Car H3)
+ - "renesas,r8a7796-wdt" (R-Car M3-W)
When compatible with the generic version, nodes must list the SoC-specific
version corresponding to the platform first, followed by the generic