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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-06-17 22:16:07 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-06-19 09:41:51 +0200 |
| commit | 9313920df6d3d55fbd03ce8ec1c0da9a10c29824 (patch) | |
| tree | ef80d80abbaf46293b777ead52caddd9d5d97644 /dts/include/dt-bindings/clock/exynos5410.h | |
| parent | 83e875e1f45beffe399cff0ff6128e0fca9da168 (diff) | |
| download | barebox-9313920df6d3d55fbd03ce8ec1c0da9a10c29824.tar.gz barebox-9313920df6d3d55fbd03ce8ec1c0da9a10c29824.tar.xz | |
dts: update to v3.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include/dt-bindings/clock/exynos5410.h')
| -rw-r--r-- | dts/include/dt-bindings/clock/exynos5410.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/dts/include/dt-bindings/clock/exynos5410.h b/dts/include/dt-bindings/clock/exynos5410.h new file mode 100644 index 0000000000..9b180f032e --- /dev/null +++ b/dts/include/dt-bindings/clock/exynos5410.h @@ -0,0 +1,33 @@ +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_BPLL 5 +#define CLK_FOUT_KPLL 6 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 + +/* gate clocks */ +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_MCT 315 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 + +#define CLK_NR_CLKS 512 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ |