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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-04-25 11:22:32 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-04-28 09:08:46 +0200 |
| commit | 00ce25c6dcdae5582ae4be37147ab33678adc995 (patch) | |
| tree | 41c93102ae304a61738c31353e3cb5336ef0b297 /dts/include/dt-bindings/clock/exynos5440.h | |
| parent | 0af79fbb6779921d3f1962773adb7fb57d3c89d4 (diff) | |
| download | barebox-00ce25c6dcdae5582ae4be37147ab33678adc995.tar.gz barebox-00ce25c6dcdae5582ae4be37147ab33678adc995.tar.xz | |
Add devicetree source files as of Linux-3.15-rc2
This adds the Linux dts files to barebox. The dts files are
generated from Ian Campbells device-tree-rebasing.git:
git://xenbits.xen.org/people/ianc/device-tree-rebasing.git
The dts are found in dts/ in the barebox repository and
will be updated from upstream regularly, probably for each upstream
-rc.
To keep the synchronization with upstream easy no changes to
the original files are allowed under dts/. Instead changes to
upstream dts files will be done using overlays in arch/$ARCH/dts/.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include/dt-bindings/clock/exynos5440.h')
| -rw-r--r-- | dts/include/dt-bindings/clock/exynos5440.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/dts/include/dt-bindings/clock/exynos5440.h b/dts/include/dt-bindings/clock/exynos5440.h new file mode 100644 index 0000000000..70cd85077f --- /dev/null +++ b/dts/include/dt-bindings/clock/exynos5440.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5440 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H + +#define CLK_XTAL 1 +#define CLK_ARM_CLK 2 +#define CLK_SPI_BAUD 16 +#define CLK_PB0_250 17 +#define CLK_PR0_250 18 +#define CLK_PR1_250 19 +#define CLK_B_250 20 +#define CLK_B_125 21 +#define CLK_B_200 22 +#define CLK_SATA 23 +#define CLK_USB 24 +#define CLK_GMAC0 25 +#define CLK_CS250 26 +#define CLK_PB0_250_O 27 +#define CLK_PR0_250_O 28 +#define CLK_PR1_250_O 29 +#define CLK_B_250_O 30 +#define CLK_B_125_O 31 +#define CLK_B_200_O 32 +#define CLK_SATA_O 33 +#define CLK_USB_O 34 +#define CLK_GMAC0_O 35 +#define CLK_CS250_O 36 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 37 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ |