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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 08:26:30 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 17:23:13 +0200 |
| commit | 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch) | |
| tree | dd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/include/dt-bindings/clock/exynos5440.h | |
| parent | 625eea2765d94aee016cf25d9cabecde8eae0775 (diff) | |
| download | barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.xz | |
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include/dt-bindings/clock/exynos5440.h')
| -rw-r--r-- | dts/include/dt-bindings/clock/exynos5440.h | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/dts/include/dt-bindings/clock/exynos5440.h b/dts/include/dt-bindings/clock/exynos5440.h deleted file mode 100644 index 842cdc0adf..0000000000 --- a/dts/include/dt-bindings/clock/exynos5440.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda <a.hajda@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Exynos5440 clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H - -#define CLK_XTAL 1 -#define CLK_ARM_CLK 2 -#define CLK_CPLLA 3 -#define CLK_CPLLB 4 -#define CLK_SPI_BAUD 16 -#define CLK_PB0_250 17 -#define CLK_PR0_250 18 -#define CLK_PR1_250 19 -#define CLK_B_250 20 -#define CLK_B_125 21 -#define CLK_B_200 22 -#define CLK_SATA 23 -#define CLK_USB 24 -#define CLK_GMAC0 25 -#define CLK_CS250 26 -#define CLK_PB0_250_O 27 -#define CLK_PR0_250_O 28 -#define CLK_PR1_250_O 29 -#define CLK_B_250_O 30 -#define CLK_B_125_O 31 -#define CLK_B_200_O 32 -#define CLK_SATA_O 33 -#define CLK_USB_O 34 -#define CLK_GMAC0_O 35 -#define CLK_CS250_O 36 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 37 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ |