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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-02-11 10:48:09 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-02-11 10:48:09 +0100 |
commit | 8633e581123ea7163bcdcb6afb098ac57c48f94e (patch) | |
tree | 657eb340bfce34c2cea74137856a21391a52e9fe /dts/include/dt-bindings/clock | |
parent | 4e2b3070d81de54c79c67e276e4293a8a1148b4a (diff) | |
download | barebox-8633e581123ea7163bcdcb6afb098ac57c48f94e.tar.gz barebox-8633e581123ea7163bcdcb6afb098ac57c48f94e.tar.xz |
dts: update to v5.0-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include/dt-bindings/clock')
-rw-r--r-- | dts/include/dt-bindings/clock/imx8mq-clock.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/dts/include/dt-bindings/clock/imx8mq-clock.h b/dts/include/dt-bindings/clock/imx8mq-clock.h index b53be41929..04f7ac3459 100644 --- a/dts/include/dt-bindings/clock/imx8mq-clock.h +++ b/dts/include/dt-bindings/clock/imx8mq-clock.h @@ -350,7 +350,7 @@ #define IMX8MQ_CLK_VPU_G2_ROOT 241 /* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 232 +#define IMX8MQ_SYS1_PLL_OUT 242 #define IMX8MQ_SYS2_PLL_OUT 243 #define IMX8MQ_SYS3_PLL_OUT 244 #define IMX8MQ_DRAM_PLL_OUT 245 @@ -372,24 +372,24 @@ /* txesc clock */ #define IMX8MQ_CLK_DSI_IPG_DIV 256 -#define IMX8MQ_CLK_TMU_ROOT 265 +#define IMX8MQ_CLK_TMU_ROOT 257 /* Display root clocks */ -#define IMX8MQ_CLK_DISP_AXI_ROOT 266 -#define IMX8MQ_CLK_DISP_APB_ROOT 267 -#define IMX8MQ_CLK_DISP_RTRM_ROOT 268 +#define IMX8MQ_CLK_DISP_AXI_ROOT 258 +#define IMX8MQ_CLK_DISP_APB_ROOT 259 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 260 -#define IMX8MQ_CLK_OCOTP_ROOT 269 +#define IMX8MQ_CLK_OCOTP_ROOT 261 -#define IMX8MQ_CLK_DRAM_ALT_ROOT 270 -#define IMX8MQ_CLK_DRAM_CORE 271 +#define IMX8MQ_CLK_DRAM_ALT_ROOT 262 +#define IMX8MQ_CLK_DRAM_CORE 263 -#define IMX8MQ_CLK_MU_ROOT 272 -#define IMX8MQ_VIDEO2_PLL_OUT 273 +#define IMX8MQ_CLK_MU_ROOT 264 +#define IMX8MQ_VIDEO2_PLL_OUT 265 -#define IMX8MQ_CLK_CLKO2 274 +#define IMX8MQ_CLK_CLKO2 266 -#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275 +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 267 -#define IMX8MQ_CLK_END 276 +#define IMX8MQ_CLK_END 268 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ |