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authorSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
commitebde8820a04dd73a09f50ba84b8cf8ec3773d6ba (patch)
tree031d15dcd26f5b737adddc5042a3ddabbb6051f7 /dts/include/dt-bindings/clock
parent15af9fc8cc9e18409893d2375271d64cac76924a (diff)
downloadbarebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.gz
barebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.xz
dts: update to v4.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include/dt-bindings/clock')
-rw-r--r--dts/include/dt-bindings/clock/gxbb-aoclkc.h1
-rw-r--r--dts/include/dt-bindings/clock/gxbb-clkc.h63
-rw-r--r--dts/include/dt-bindings/clock/meson8b-clkc.h70
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8996.h2
-rw-r--r--dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h57
-rw-r--r--dts/include/dt-bindings/clock/rk3228-cru.h1
-rw-r--r--dts/include/dt-bindings/clock/rv1108-cru.h125
-rw-r--r--dts/include/dt-bindings/clock/stm32h7-clks.h165
-rw-r--r--dts/include/dt-bindings/clock/sun4i-a10-ccu.h200
-rw-r--r--dts/include/dt-bindings/clock/sun7i-a20-ccu.h53
-rw-r--r--dts/include/dt-bindings/clock/sun8i-r40-ccu.h187
11 files changed, 908 insertions, 16 deletions
diff --git a/dts/include/dt-bindings/clock/gxbb-aoclkc.h b/dts/include/dt-bindings/clock/gxbb-aoclkc.h
index 31751482d1..9d15e2221f 100644
--- a/dts/include/dt-bindings/clock/gxbb-aoclkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -62,5 +62,6 @@
#define CLKID_AO_UART1 3
#define CLKID_AO_UART2 4
#define CLKID_AO_IR_BLASTER 5
+#define CLKID_AO_CEC_32K 6
#endif
diff --git a/dts/include/dt-bindings/clock/gxbb-clkc.h b/dts/include/dt-bindings/clock/gxbb-clkc.h
index e3e9f7919c..c04a76d8fa 100644
--- a/dts/include/dt-bindings/clock/gxbb-clkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-clkc.h
@@ -5,37 +5,96 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
+#define CLKID_SYS_PLL 0
#define CLKID_HDMI_PLL 2
+#define CLKID_FIXED_PLL 3
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
+#define CLKID_FCLK_DIV5 7
+#define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
+#define CLKID_MPLL0 13
+#define CLKID_MPLL1 14
#define CLKID_MPLL2 15
+#define CLKID_DDR 16
+#define CLKID_DOS 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
+#define CLKID_SDHC 27
+#define CLKID_STREAM 28
+#define CLKID_ASYNC_FIFO 29
+#define CLKID_SDIO 30
+#define CLKID_ABUF 31
+#define CLKID_HIU_IFACE 32
+#define CLKID_ASSIST_MISC 33
#define CLKID_SPI 34
#define CLKID_ETH 36
+#define CLKID_I2S_SPDIF 35
+#define CLKID_DEMUX 37
#define CLKID_AIU_GLUE 38
#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40
+#define CLKID_AMCLK 41
+#define CLKID_AIFIFO2 42
+#define CLKID_MIXER 43
#define CLKID_MIXER_IFACE 44
+#define CLKID_ADC 45
+#define CLKID_BLKMV 46
#define CLKID_AIU 47
#define CLKID_UART1 48
+#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
+#define CLKID_RESET 52
+#define CLKID_NAND 53
+#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
+#define CLKID_VDIN1 56
+#define CLKID_AHB_ARB0 57
+#define CLKID_EFUSE 58
+#define CLKID_BOOT_ROM 59
+#define CLKID_AHB_DATA_BUS 60
+#define CLKID_AHB_CTRL_BUS 61
+#define CLKID_HDMI_INTR_SYNC 62
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_MMC_PCLK 66
+#define CLKID_DVIN 67
#define CLKID_UART2 68
#define CLKID_SANA 69
+#define CLKID_VPU_INTR 70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53 72
+#define CLKID_VCLK2_VENCI0 73
+#define CLKID_VCLK2_VENCI1 74
+#define CLKID_VCLK2_VENCP0 75
+#define CLKID_VCLK2_VENCP1 76
#define CLKID_GCLK_VENCI_INT0 77
+#define CLKID_GCLK_VENCI_INT 78
+#define CLKID_DAC_CLK 79
#define CLKID_AOCLK_GATE 80
#define CLKID_IEC958_GATE 81
+#define CLKID_ENC480P 82
+#define CLKID_RNG1 83
+#define CLKID_GCLK_VENCI_INT1 84
+#define CLKID_VCLK2_VENCLMCC 85
+#define CLKID_VCLK2_VENCL 86
+#define CLKID_VCLK_OTHER 87
+#define CLKID_EDP 88
+#define CLKID_AO_MEDIA_CPU 89
+#define CLKID_AO_AHB_SRAM 90
+#define CLKID_AO_AHB_BUS 91
+#define CLKID_AO_IFACE 92
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
@@ -50,5 +109,9 @@
#define CLKID_CTS_AMCLK 107
#define CLKID_CTS_MCLK_I958 110
#define CLKID_CTS_I958 113
+#define CLKID_32K_CLK 114
+#define CLKID_SD_EMMC_A_CLK0 119
+#define CLKID_SD_EMMC_B_CLK0 122
+#define CLKID_SD_EMMC_C_CLK0 125
#endif /* __GXBB_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h
index e29227fb52..a9c0306330 100644
--- a/dts/include/dt-bindings/clock/meson8b-clkc.h
+++ b/dts/include/dt-bindings/clock/meson8b-clkc.h
@@ -21,15 +21,85 @@
#define CLKID_ZERO 13
#define CLKID_MPEG_SEL 14
#define CLKID_MPEG_DIV 15
+#define CLKID_DDR 16
+#define CLKID_DOS 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
+#define CLKID_SPICC 21
+#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
+#define CLKID_UART0 26
+#define CLKID_SDHC 27
+#define CLKID_STREAM 28
+#define CLKID_ASYNC_FIFO 29
#define CLKID_SDIO 30
+#define CLKID_ABUF 31
+#define CLKID_HIU_IFACE 32
+#define CLKID_ASSIST_MISC 33
+#define CLKID_SPI 34
+#define CLKID_I2S_SPDIF 35
#define CLKID_ETH 36
+#define CLKID_DEMUX 37
+#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
+#define CLKID_I2S_OUT 40
+#define CLKID_AMCLK 41
+#define CLKID_AIFIFO2 42
+#define CLKID_MIXER 43
+#define CLKID_MIXER_IFACE 44
+#define CLKID_ADC 45
+#define CLKID_BLKMV 46
+#define CLKID_AIU 47
+#define CLKID_UART1 48
+#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
+#define CLKID_RESET 52
+#define CLKID_NAND 53
+#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
+#define CLKID_VDIN1 56
+#define CLKID_AHB_ARB0 57
+#define CLKID_EFUSE 58
+#define CLKID_BOOT_ROM 59
+#define CLKID_AHB_DATA_BUS 60
+#define CLKID_AHB_CTRL_BUS 61
+#define CLKID_HDMI_INTR_SYNC 62
+#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_MMC_PCLK 66
+#define CLKID_DVIN 67
+#define CLKID_UART2 68
#define CLKID_SANA 69
+#define CLKID_VPU_INTR 70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A9 72
+#define CLKID_VCLK2_VENCI0 73
+#define CLKID_VCLK2_VENCI1 74
+#define CLKID_VCLK2_VENCP0 75
+#define CLKID_VCLK2_VENCP1 76
+#define CLKID_GCLK_VENCI_INT 77
+#define CLKID_GCLK_VENCP_INT 78
+#define CLKID_DAC_CLK 79
+#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
+#define CLKID_ENC480P 82
+#define CLKID_RNG1 83
+#define CLKID_GCLK_VENCL_INT 84
+#define CLKID_VCLK2_VENCLMCC 85
+#define CLKID_VCLK2_VENCL 86
+#define CLKID_VCLK2_OTHER 87
+#define CLKID_EDP 88
+#define CLKID_AO_MEDIA_CPU 89
+#define CLKID_AO_AHB_SRAM 90
+#define CLKID_AO_AHB_BUS 91
+#define CLKID_AO_IFACE 92
+#define CLKID_MPLL0 93
+#define CLKID_MPLL1 94
+#define CLKID_MPLL2 95
#endif /* __MESON8B_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h b/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 1f5c422547..75b07cf5ee 100644
--- a/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -233,6 +233,8 @@
#define GCC_PCIE_CLKREF_CLK 216
#define GCC_RX2_USB2_CLKREF_CLK 217
#define GCC_RX1_USB2_CLKREF_CLK 218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
diff --git a/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index 0000000000..4e8ae3dee5
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2 0
+#define R8A77995_CLK_ZG 1
+#define R8A77995_CLK_ZTR 2
+#define R8A77995_CLK_ZT 3
+#define R8A77995_CLK_ZX 4
+#define R8A77995_CLK_S0D1 5
+#define R8A77995_CLK_S1D1 6
+#define R8A77995_CLK_S1D2 7
+#define R8A77995_CLK_S1D4 8
+#define R8A77995_CLK_S2D1 9
+#define R8A77995_CLK_S2D2 10
+#define R8A77995_CLK_S2D4 11
+#define R8A77995_CLK_S3D1 12
+#define R8A77995_CLK_S3D2 13
+#define R8A77995_CLK_S3D4 14
+#define R8A77995_CLK_S1D4C 15
+#define R8A77995_CLK_S3D1C 16
+#define R8A77995_CLK_S3D2C 17
+#define R8A77995_CLK_S3D4C 18
+#define R8A77995_CLK_LB 19
+#define R8A77995_CLK_CL 20
+#define R8A77995_CLK_ZB3 21
+#define R8A77995_CLK_ZB3D2 22
+#define R8A77995_CLK_CR 23
+#define R8A77995_CLK_CRD2 24
+#define R8A77995_CLK_SD0H 25
+#define R8A77995_CLK_SD0 26
+#define R8A77995_CLK_SSP2 27
+#define R8A77995_CLK_SSP1 28
+#define R8A77995_CLK_RPC 29
+#define R8A77995_CLK_RPCD2 30
+#define R8A77995_CLK_ZA2 31
+#define R8A77995_CLK_ZA8 32
+#define R8A77995_CLK_Z2D 33
+#define R8A77995_CLK_CANFD 34
+#define R8A77995_CLK_MSO 35
+#define R8A77995_CLK_R 36
+#define R8A77995_CLK_OSC 37
+#define R8A77995_CLK_LV0 38
+#define R8A77995_CLK_LV1 39
+#define R8A77995_CLK_CP 40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/rk3228-cru.h b/dts/include/dt-bindings/clock/rk3228-cru.h
index 56f841c228..55655ab0a4 100644
--- a/dts/include/dt-bindings/clock/rk3228-cru.h
+++ b/dts/include/dt-bindings/clock/rk3228-cru.h
@@ -49,6 +49,7 @@
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
+#define SCLK_SDIO_SRC 120
#define SCLK_EMMC_SAMPLE 121
#define SCLK_VOP 122
#define SCLK_HDMI_HDCP 123
diff --git a/dts/include/dt-bindings/clock/rv1108-cru.h b/dts/include/dt-bindings/clock/rv1108-cru.h
index ae26f81059..d8d0e0456d 100644
--- a/dts/include/dt-bindings/clock/rv1108-cru.h
+++ b/dts/include/dt-bindings/clock/rv1108-cru.h
@@ -43,12 +43,74 @@
#define SCLK_SDMMC_SAMPLE 84
#define SCLK_SDIO_SAMPLE 85
#define SCLK_EMMC_SAMPLE 86
+#define SCLK_VENC_CORE 87
+#define SCLK_HEVC_CORE 88
+#define SCLK_HEVC_CABAC 89
+#define SCLK_PWM0_PMU 90
+#define SCLK_I2C0_PMU 91
+#define SCLK_WIFI 92
+#define SCLK_CIFOUT 93
+#define SCLK_MIPI_CSI_OUT 94
+#define SCLK_CIF0 95
+#define SCLK_CIF1 96
+#define SCLK_CIF2 97
+#define SCLK_CIF3 98
+#define SCLK_DSP 99
+#define SCLK_DSP_IOP 100
+#define SCLK_DSP_EPP 101
+#define SCLK_DSP_EDP 102
+#define SCLK_DSP_EDAP 103
+#define SCLK_CVBS_HOST 104
+#define SCLK_HDMI_SFR 105
+#define SCLK_HDMI_CEC 106
+#define SCLK_CRYPTO 107
+#define SCLK_SPI 108
+#define SCLK_SARADC 109
+#define SCLK_TSADC 110
+#define SCLK_MAC_PRE 111
+#define SCLK_MAC 112
+#define SCLK_MAC_RX 113
+#define SCLK_MAC_REF 114
+#define SCLK_MAC_REFOUT 115
+#define SCLK_DSP_PFM 116
+#define SCLK_RGA 117
+#define SCLK_I2C1 118
+#define SCLK_I2C2 119
+#define SCLK_I2C3 120
+#define SCLK_PWM 121
+#define SCLK_ISP 122
+#define SCLK_USBPHY 123
+#define SCLK_I2S0_SRC 124
+#define SCLK_I2S1_SRC 125
+#define SCLK_I2S2_SRC 126
+#define SCLK_UART0_SRC 127
+#define SCLK_UART1_SRC 128
+#define SCLK_UART2_SRC 129
+
+#define DCLK_VOP_SRC 185
+#define DCLK_HDMIPHY 186
+#define DCLK_VOP 187
/* aclk gates */
#define ACLK_DMAC 192
#define ACLK_PRE 193
#define ACLK_CORE 194
#define ACLK_ENMCORE 195
+#define ACLK_RKVENC 196
+#define ACLK_RKVDEC 197
+#define ACLK_VPU 198
+#define ACLK_CIF0 199
+#define ACLK_VIO0 200
+#define ACLK_VIO1 201
+#define ACLK_VOP 202
+#define ACLK_IEP 203
+#define ACLK_RGA 204
+#define ACLK_ISP 205
+#define ACLK_CIF1 206
+#define ACLK_CIF2 207
+#define ACLK_CIF3 208
+#define ACLK_PERI 209
+#define ACLK_GMAC 210
/* pclk gates */
#define PCLK_GPIO1 256
@@ -67,10 +129,24 @@
#define PCLK_PWM 269
#define PCLK_TIMER 270
#define PCLK_PERI 271
+#define PCLK_GPIO0_PMU 272
+#define PCLK_I2C0_PMU 273
+#define PCLK_PWM0_PMU 274
+#define PCLK_ISP 275
+#define PCLK_VIO 276
+#define PCLK_MIPI_DSI 277
+#define PCLK_HDMI_CTRL 278
+#define PCLK_SARADC 279
+#define PCLK_DSP_CFG 280
+#define PCLK_BUS 281
+#define PCLK_EFUSE0 282
+#define PCLK_EFUSE1 283
+#define PCLK_WDT 284
+#define PCLK_GMAC 285
/* hclk gates */
#define HCLK_I2S0_8CH 320
-#define HCLK_I2S1_8CH 321
+#define HCLK_I2S1_2CH 321
#define HCLK_I2S2_2CH 322
#define HCLK_NANDC 323
#define HCLK_SDMMC 324
@@ -78,20 +154,37 @@
#define HCLK_EMMC 326
#define HCLK_PERI 327
#define HCLK_SFC 328
+#define HCLK_RKVENC 329
+#define HCLK_RKVDEC 330
+#define HCLK_CIF0 331
+#define HCLK_VIO 332
+#define HCLK_VOP 333
+#define HCLK_IEP 334
+#define HCLK_RGA 335
+#define HCLK_ISP 336
+#define HCLK_CRYPTO_MST 337
+#define HCLK_CRYPTO_SLV 338
+#define HCLK_HOST0 339
+#define HCLK_OTG 340
+#define HCLK_CIF1 341
+#define HCLK_CIF2 342
+#define HCLK_CIF3 343
+#define HCLK_BUS 344
+#define HCLK_VPU 345
-#define CLK_NR_CLKS (HCLK_SFC + 1)
+#define CLK_NR_CLKS (HCLK_VPU + 1)
/* reset id */
-#define SRST_CORE_PO_AD 0
+#define SRST_CORE_PO_AD 0
#define SRST_CORE_AD 1
#define SRST_L2_AD 2
-#define SRST_CPU_NIU_AD 3
+#define SRST_CPU_NIU_AD 3
#define SRST_CORE_PO 4
#define SRST_CORE 5
-#define SRST_L2 6
+#define SRST_L2 6
#define SRST_CORE_DBG 8
#define PRST_DBG 9
-#define RST_DAP 10
+#define RST_DAP 10
#define PRST_DBG_NIU 11
#define ARST_STRC_SYS_AD 15
@@ -158,9 +251,9 @@
#define HRST_SYSBUS 75
#define PRST_USBGRF 76
-#define ARST_PERIPH_NIU 80
-#define HRST_PERIPH_NIU 81
-#define PRST_PERIPH_NIU 82
+#define ARST_PERIPH_NIU 80
+#define HRST_PERIPH_NIU 81
+#define PRST_PERIPH_NIU 82
#define HRST_PERIPH 83
#define HRST_SDMMC 84
#define HRST_SDIO 85
@@ -178,7 +271,7 @@
#define HRST_HOST0_AUX 96
#define HRST_HOST0_ARB 97
#define SRST_HOST0_EHCIPHY 98
-#define SRST_HOST0_UTMI 99
+#define SRST_HOST0_UTMI 99
#define SRST_USBPOR 100
#define SRST_UTMI0 101
#define SRST_UTMI1 102
@@ -225,21 +318,21 @@
#define HRST_VPU_NIU 141
#define ARST_VPU 142
#define HRST_VPU 143
-#define ARST_RKVDEC_NIU 144
-#define HRST_RKVDEC_NIU 145
+#define ARST_RKVDEC_NIU 144
+#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC 146
#define HRST_RKVDEC 147
#define SRST_RKVDEC_CABAC 148
#define SRST_RKVDEC_CORE 149
-#define ARST_RKVENC_NIU 150
-#define HRST_RKVENC_NIU 151
+#define ARST_RKVENC_NIU 150
+#define HRST_RKVENC_NIU 151
#define ARST_RKVENC 152
#define HRST_RKVENC 153
#define SRST_RKVENC_CORE 154
#define SRST_DSP_CORE 156
#define SRST_DSP_SYS 157
-#define SRST_DSP_GLOBAL 158
+#define SRST_DSP_GLOBAL 158
#define SRST_DSP_OECM 159
#define PRST_DSP_IOP_NIU 160
#define ARST_DSP_EPP_NIU 161
@@ -257,7 +350,7 @@
#define SRST_PMU_I2C0 173
#define PRST_PMU_I2C0 174
#define PRST_PMU_GPIO0 175
-#define PRST_PMU_INTMEM 176
+#define PRST_PMU_INTMEM 176
#define PRST_PMU_PWM0 177
#define SRST_PMU_PWM0 178
#define PRST_PMU_GRF 179
diff --git a/dts/include/dt-bindings/clock/stm32h7-clks.h b/dts/include/dt-bindings/clock/stm32h7-clks.h
new file mode 100644
index 0000000000..6637272b32
--- /dev/null
+++ b/dts/include/dt-bindings/clock/stm32h7-clks.h
@@ -0,0 +1,165 @@
+/* SYS, CORE AND BUS CLOCKS */
+#define SYS_D1CPRE 0
+#define HCLK 1
+#define PCLK1 2
+#define PCLK2 3
+#define PCLK3 4
+#define PCLK4 5
+#define HSI_DIV 6
+#define HSE_1M 7
+#define I2S_CKIN 8
+#define CK_DSI_PHY 9
+#define HSE_CK 10
+#define LSE_CK 11
+#define CSI_KER_DIV122 12
+#define RTC_CK 13
+#define CPU_SYSTICK 14
+
+/* OSCILLATOR BANK */
+#define OSC_BANK 18
+#define HSI_CK 18
+#define HSI_KER_CK 19
+#define CSI_CK 20
+#define CSI_KER_CK 21
+#define RC48_CK 22
+#define LSI_CK 23
+
+/* MCLOCK BANK */
+#define MCLK_BANK 28
+#define PER_CK 28
+#define PLLSRC 29
+#define SYS_CK 30
+#define TRACEIN_CK 31
+
+/* ODF BANK */
+#define ODF_BANK 32
+#define PLL1_P 32
+#define PLL1_Q 33
+#define PLL1_R 34
+#define PLL2_P 35
+#define PLL2_Q 36
+#define PLL2_R 37
+#define PLL3_P 38
+#define PLL3_Q 39
+#define PLL3_R 40
+
+/* MCO BANK */
+#define MCO_BANK 41
+#define MCO1 41
+#define MCO2 42
+
+/* PERIF BANK */
+#define PERIF_BANK 50
+#define D1SRAM1_CK 50
+#define ITCM_CK 51
+#define DTCM2_CK 52
+#define DTCM1_CK 53
+#define FLITF_CK 54
+#define JPGDEC_CK 55
+#define DMA2D_CK 56
+#define MDMA_CK 57
+#define USB2ULPI_CK 58
+#define USB1ULPI_CK 59
+#define ETH1RX_CK 60
+#define ETH1TX_CK 61
+#define ETH1MAC_CK 62
+#define ART_CK 63
+#define DMA2_CK 64
+#define DMA1_CK 65
+#define D2SRAM3_CK 66
+#define D2SRAM2_CK 67
+#define D2SRAM1_CK 68
+#define HASH_CK 69
+#define CRYPT_CK 70
+#define CAMITF_CK 71
+#define BKPRAM_CK 72
+#define HSEM_CK 73
+#define BDMA_CK 74
+#define CRC_CK 75
+#define GPIOK_CK 76
+#define GPIOJ_CK 77
+#define GPIOI_CK 78
+#define GPIOH_CK 79
+#define GPIOG_CK 80
+#define GPIOF_CK 81
+#define GPIOE_CK 82
+#define GPIOD_CK 83
+#define GPIOC_CK 84
+#define GPIOB_CK 85
+#define GPIOA_CK 86
+#define WWDG1_CK 87
+#define DAC12_CK 88
+#define WWDG2_CK 89
+#define TIM14_CK 90
+#define TIM13_CK 91
+#define TIM12_CK 92
+#define TIM7_CK 93
+#define TIM6_CK 94
+#define TIM5_CK 95
+#define TIM4_CK 96
+#define TIM3_CK 97
+#define TIM2_CK 98
+#define MDIOS_CK 99
+#define OPAMP_CK 100
+#define CRS_CK 101
+#define TIM17_CK 102
+#define TIM16_CK 103
+#define TIM15_CK 104
+#define TIM8_CK 105
+#define TIM1_CK 106
+#define TMPSENS_CK 107
+#define RTCAPB_CK 108
+#define VREF_CK 109
+#define COMP12_CK 110
+#define SYSCFG_CK 111
+
+/* KERNEL BANK */
+#define KERN_BANK 120
+#define SDMMC1_CK 120
+#define QUADSPI_CK 121
+#define FMC_CK 122
+#define USB2OTG_CK 123
+#define USB1OTG_CK 124
+#define ADC12_CK 125
+#define SDMMC2_CK 126
+#define RNG_CK 127
+#define ADC3_CK 128
+#define DSI_CK 129
+#define LTDC_CK 130
+#define USART8_CK 131
+#define USART7_CK 132
+#define HDMICEC_CK 133
+#define I2C3_CK 134
+#define I2C2_CK 135
+#define I2C1_CK 136
+#define UART5_CK 137
+#define UART4_CK 138
+#define USART3_CK 139
+#define USART2_CK 140
+#define SPDIFRX_CK 141
+#define SPI3_CK 142
+#define SPI2_CK 143
+#define LPTIM1_CK 144
+#define FDCAN_CK 145
+#define SWP_CK 146
+#define HRTIM_CK 147
+#define DFSDM1_CK 148
+#define SAI3_CK 149
+#define SAI2_CK 150
+#define SAI1_CK 151
+#define SPI5_CK 152
+#define SPI4_CK 153
+#define SPI1_CK 154
+#define USART6_CK 155
+#define USART1_CK 156
+#define SAI4B_CK 157
+#define SAI4A_CK 158
+#define LPTIM5_CK 159
+#define LPTIM4_CK 160
+#define LPTIM3_CK 161
+#define LPTIM2_CK 162
+#define I2C4_CK 163
+#define SPI6_CK 164
+#define LPUART1_CK 165
+
+#define STM32H7_MAX_CLKS 166
diff --git a/dts/include/dt-bindings/clock/sun4i-a10-ccu.h b/dts/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 0000000000..c5a53f38d6
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC 1
+#define CLK_CPU 20
+
+/* AHB Gates */
+#define CLK_AHB_OTG 26
+#define CLK_AHB_EHCI0 27
+#define CLK_AHB_OHCI0 28
+#define CLK_AHB_EHCI1 29
+#define CLK_AHB_OHCI1 30
+#define CLK_AHB_SS 31
+#define CLK_AHB_DMA 32
+#define CLK_AHB_BIST 33
+#define CLK_AHB_MMC0 34
+#define CLK_AHB_MMC1 35
+#define CLK_AHB_MMC2 36
+#define CLK_AHB_MMC3 37
+#define CLK_AHB_MS 38
+#define CLK_AHB_NAND 39
+#define CLK_AHB_SDRAM 40
+#define CLK_AHB_ACE 41
+#define CLK_AHB_EMAC 42
+#define CLK_AHB_TS 43
+#define CLK_AHB_SPI0 44
+#define CLK_AHB_SPI1 45
+#define CLK_AHB_SPI2 46
+#define CLK_AHB_SPI3 47
+#define CLK_AHB_PATA 48
+#define CLK_AHB_SATA 49
+#define CLK_AHB_GPS 50
+#define CLK_AHB_HSTIMER 51
+#define CLK_AHB_VE 52
+#define CLK_AHB_TVD 53
+#define CLK_AHB_TVE0 54
+#define CLK_AHB_TVE1 55
+#define CLK_AHB_LCD0 56
+#define CLK_AHB_LCD1 57
+#define CLK_AHB_CSI0 58
+#define CLK_AHB_CSI1 59
+#define CLK_AHB_HDMI0 60
+#define CLK_AHB_HDMI1 61
+#define CLK_AHB_DE_BE0 62
+#define CLK_AHB_DE_BE1 63
+#define CLK_AHB_DE_FE0 64
+#define CLK_AHB_DE_FE1 65
+#define CLK_AHB_GMAC 66
+#define CLK_AHB_MP 67
+#define CLK_AHB_GPU 68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC 69
+#define CLK_APB0_SPDIF 70
+#define CLK_APB0_I2S0 71
+#define CLK_APB0_AC97 72
+#define CLK_APB0_I2S1 73
+#define CLK_APB0_PIO 74
+#define CLK_APB0_IR0 75
+#define CLK_APB0_IR1 76
+#define CLK_APB0_I2S2 77
+#define CLK_APB0_KEYPAD 78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0 79
+#define CLK_APB1_I2C1 80
+#define CLK_APB1_I2C2 81
+#define CLK_APB1_I2C3 82
+#define CLK_APB1_CAN 83
+#define CLK_APB1_SCR 84
+#define CLK_APB1_PS20 85
+#define CLK_APB1_PS21 86
+#define CLK_APB1_I2C4 87
+#define CLK_APB1_UART0 88
+#define CLK_APB1_UART1 89
+#define CLK_APB1_UART2 90
+#define CLK_APB1_UART3 91
+#define CLK_APB1_UART4 92
+#define CLK_APB1_UART5 93
+#define CLK_APB1_UART6 94
+#define CLK_APB1_UART7 95
+
+/* IP clocks */
+#define CLK_NAND 96
+#define CLK_MS 97
+#define CLK_MMC0 98
+#define CLK_MMC0_OUTPUT 99
+#define CLK_MMC0_SAMPLE 100
+#define CLK_MMC1 101
+#define CLK_MMC1_OUTPUT 102
+#define CLK_MMC1_SAMPLE 103
+#define CLK_MMC2 104
+#define CLK_MMC2_OUTPUT 105
+#define CLK_MMC2_SAMPLE 106
+#define CLK_MMC3 107
+#define CLK_MMC3_OUTPUT 108
+#define CLK_MMC3_SAMPLE 109
+#define CLK_TS 110
+#define CLK_SS 111
+#define CLK_SPI0 112
+#define CLK_SPI1 113
+#define CLK_SPI2 114
+#define CLK_PATA 115
+#define CLK_IR0 116
+#define CLK_IR1 117
+#define CLK_I2S0 118
+#define CLK_AC97 119
+#define CLK_SPDIF 120
+#define CLK_KEYPAD 121
+#define CLK_SATA 122
+#define CLK_USB_OHCI0 123
+#define CLK_USB_OHCI1 124
+#define CLK_USB_PHY 125
+#define CLK_GPS 126
+#define CLK_SPI3 127
+#define CLK_I2S1 128
+#define CLK_I2S2 129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE 130
+#define CLK_DRAM_CSI0 131
+#define CLK_DRAM_CSI1 132
+#define CLK_DRAM_TS 133
+#define CLK_DRAM_TVD 134
+#define CLK_DRAM_TVE0 135
+#define CLK_DRAM_TVE1 136
+#define CLK_DRAM_OUT 137
+#define CLK_DRAM_DE_FE1 138
+#define CLK_DRAM_DE_FE0 139
+#define CLK_DRAM_DE_BE0 140
+#define CLK_DRAM_DE_BE1 141
+#define CLK_DRAM_MP 142
+#define CLK_DRAM_ACE 143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0 144
+#define CLK_DE_BE1 145
+#define CLK_DE_FE0 146
+#define CLK_DE_FE1 147
+#define CLK_DE_MP 148
+#define CLK_TCON0_CH0 149
+#define CLK_TCON1_CH0 150
+#define CLK_CSI_SCLK 151
+#define CLK_TVD_SCLK2 152
+#define CLK_TVD 153
+#define CLK_TCON0_CH1_SCLK2 154
+#define CLK_TCON0_CH1 155
+#define CLK_TCON1_CH1_SCLK2 156
+#define CLK_TCON1_CH1 157
+#define CLK_CSI0 158
+#define CLK_CSI1 159
+#define CLK_CODEC 160
+#define CLK_VE 161
+#define CLK_AVS 162
+#define CLK_ACE 163
+#define CLK_HDMI 164
+#define CLK_GPU 165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/dts/include/dt-bindings/clock/sun7i-a20-ccu.h b/dts/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 0000000000..045a5178da
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS 166
+#define CLK_HDMI1_SLOW 167
+#define CLK_HDMI1 168
+#define CLK_OUT_A 169
+#define CLK_OUT_B 170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/dts/include/dt-bindings/clock/sun8i-r40-ccu.h b/dts/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 0000000000..4fa5f69fc2
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_CPU 24
+
+#define CLK_BUS_MIPI_DSI 29
+#define CLK_BUS_CE 30
+#define CLK_BUS_DMA 31
+#define CLK_BUS_MMC0 32
+#define CLK_BUS_MMC1 33
+#define CLK_BUS_MMC2 34
+#define CLK_BUS_MMC3 35
+#define CLK_BUS_NAND 36
+#define CLK_BUS_DRAM 37
+#define CLK_BUS_EMAC 38
+#define CLK_BUS_TS 39
+#define CLK_BUS_HSTIMER 40
+#define CLK_BUS_SPI0 41
+#define CLK_BUS_SPI1 42
+#define CLK_BUS_SPI2 43
+#define CLK_BUS_SPI3 44
+#define CLK_BUS_SATA 45
+#define CLK_BUS_OTG 46
+#define CLK_BUS_EHCI0 47
+#define CLK_BUS_EHCI1 48
+#define CLK_BUS_EHCI2 49
+#define CLK_BUS_OHCI0 50
+#define CLK_BUS_OHCI1 51
+#define CLK_BUS_OHCI2 52
+#define CLK_BUS_VE 53
+#define CLK_BUS_MP 54
+#define CLK_BUS_DEINTERLACE 55
+#define CLK_BUS_CSI0 56
+#define CLK_BUS_CSI1 57
+#define CLK_BUS_HDMI1 58
+#define CLK_BUS_HDMI0 59
+#define CLK_BUS_DE 60
+#define CLK_BUS_TVE0 61
+#define CLK_BUS_TVE1 62
+#define CLK_BUS_TVE_TOP 63
+#define CLK_BUS_GMAC 64
+#define CLK_BUS_GPU 65
+#define CLK_BUS_TVD0 66
+#define CLK_BUS_TVD1 67
+#define CLK_BUS_TVD2 68
+#define CLK_BUS_TVD3 69
+#define CLK_BUS_TVD_TOP 70
+#define CLK_BUS_TCON_LCD0 71
+#define CLK_BUS_TCON_LCD1 72
+#define CLK_BUS_TCON_TV0 73
+#define CLK_BUS_TCON_TV1 74
+#define CLK_BUS_TCON_TOP 75
+#define CLK_BUS_CODEC 76
+#define CLK_BUS_SPDIF 77
+#define CLK_BUS_AC97 78
+#define CLK_BUS_PIO 79
+#define CLK_BUS_IR0 80
+#define CLK_BUS_IR1 81
+#define CLK_BUS_THS 82
+#define CLK_BUS_KEYPAD 83
+#define CLK_BUS_I2S0 84
+#define CLK_BUS_I2S1 85
+#define CLK_BUS_I2S2 86
+#define CLK_BUS_I2C0 87
+#define CLK_BUS_I2C1 88
+#define CLK_BUS_I2C2 89
+#define CLK_BUS_I2C3 90
+#define CLK_BUS_CAN 91
+#define CLK_BUS_SCR 92
+#define CLK_BUS_PS20 93
+#define CLK_BUS_PS21 94
+#define CLK_BUS_I2C4 95
+#define CLK_BUS_UART0 96
+#define CLK_BUS_UART1 97
+#define CLK_BUS_UART2 98
+#define CLK_BUS_UART3 99
+#define CLK_BUS_UART4 100
+#define CLK_BUS_UART5 101
+#define CLK_BUS_UART6 102
+#define CLK_BUS_UART7 103
+#define CLK_BUS_DBG 104
+
+#define CLK_THS 105
+#define CLK_NAND 106
+#define CLK_MMC0 107
+#define CLK_MMC1 108
+#define CLK_MMC2 109
+#define CLK_MMC3 110
+#define CLK_TS 111
+#define CLK_CE 112
+#define CLK_SPI0 113
+#define CLK_SPI1 114
+#define CLK_SPI2 115
+#define CLK_SPI3 116
+#define CLK_I2S0 117
+#define CLK_I2S1 118
+#define CLK_I2S2 119
+#define CLK_AC97 120
+#define CLK_SPDIF 121
+#define CLK_KEYPAD 122
+#define CLK_SATA 123
+#define CLK_USB_PHY0 124
+#define CLK_USB_PHY1 125
+#define CLK_USB_PHY2 126
+#define CLK_USB_OHCI0 127
+#define CLK_USB_OHCI1 128
+#define CLK_USB_OHCI2 129
+#define CLK_IR0 130
+#define CLK_IR1 131
+
+#define CLK_DRAM_VE 133
+#define CLK_DRAM_CSI0 134
+#define CLK_DRAM_CSI1 135
+#define CLK_DRAM_TS 136
+#define CLK_DRAM_TVD 137
+#define CLK_DRAM_MP 138
+#define CLK_DRAM_DEINTERLACE 139
+#define CLK_DE 140
+#define CLK_MP 141
+#define CLK_TCON_LCD0 142
+#define CLK_TCON_LCD1 143
+#define CLK_TCON_TV0 144
+#define CLK_TCON_TV1 145
+#define CLK_DEINTERLACE 146
+#define CLK_CSI1_MCLK 147
+#define CLK_CSI_SCLK 148
+#define CLK_CSI0_MCLK 149
+#define CLK_VE 150
+#define CLK_CODEC 151
+#define CLK_AVS 152
+#define CLK_HDMI 153
+#define CLK_HDMI_SLOW 154
+
+#define CLK_DSI_DPHY 156
+#define CLK_TVE0 157
+#define CLK_TVE1 158
+#define CLK_TVD0 159
+#define CLK_TVD1 160
+#define CLK_TVD2 161
+#define CLK_TVD3 162
+#define CLK_GPU 163
+#define CLK_OUTA 164
+#define CLK_OUTB 165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */