Add devicetree source files as of Linux-3.15-rc2

This adds the Linux dts files to barebox. The dts files are
generated from Ian Campbells device-tree-rebasing.git:

git://xenbits.xen.org/people/ianc/device-tree-rebasing.git

The dts are found in dts/ in the barebox repository and
will be updated from upstream regularly, probably for each upstream
-rc.

To keep the synchronization with upstream easy no changes to
the original files are allowed under dts/. Instead changes to
upstream dts files will be done using overlays in arch/$ARCH/dts/.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

5 files changed, 503 insertions, 0 deletions

diff --git a/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h b/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h
new file mode 100644
index 0000000000..a83282fe54
--- /dev/null
+++ b/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8660_H
+
+#define AFAB_CORE_RESET					0
+#define SCSS_SYS_RESET					1
+#define SCSS_SYS_POR_RESET				2
+#define AFAB_SMPSS_S_RESET				3
+#define AFAB_SMPSS_M1_RESET				4
+#define AFAB_SMPSS_M0_RESET				5
+#define AFAB_EBI1_S_RESET				6
+#define SFAB_CORE_RESET					7
+#define SFAB_ADM0_M0_RESET				8
+#define SFAB_ADM0_M1_RESET				9
+#define SFAB_ADM0_M2_RESET				10
+#define ADM0_C2_RESET					11
+#define ADM0_C1_RESET					12
+#define ADM0_C0_RESET					13
+#define ADM0_PBUS_RESET					14
+#define ADM0_RESET					15
+#define SFAB_ADM1_M0_RESET				16
+#define SFAB_ADM1_M1_RESET				17
+#define SFAB_ADM1_M2_RESET				18
+#define MMFAB_ADM1_M3_RESET				19
+#define ADM1_C3_RESET					20
+#define ADM1_C2_RESET					21
+#define ADM1_C1_RESET					22
+#define ADM1_C0_RESET					23
+#define ADM1_PBUS_RESET					24
+#define ADM1_RESET					25
+#define IMEM0_RESET					26
+#define SFAB_LPASS_Q6_RESET				27
+#define SFAB_AFAB_M_RESET				28
+#define AFAB_SFAB_M0_RESET				29
+#define AFAB_SFAB_M1_RESET				30
+#define DFAB_CORE_RESET					31
+#define SFAB_DFAB_M_RESET				32
+#define DFAB_SFAB_M_RESET				33
+#define DFAB_SWAY0_RESET				34
+#define DFAB_SWAY1_RESET				35
+#define DFAB_ARB0_RESET					36
+#define DFAB_ARB1_RESET					37
+#define PPSS_PROC_RESET					38
+#define PPSS_RESET					39
+#define PMEM_RESET					40
+#define DMA_BAM_RESET					41
+#define SIC_RESET					42
+#define SPS_TIC_RESET					43
+#define CFBP0_RESET					44
+#define CFBP1_RESET					45
+#define CFBP2_RESET					46
+#define EBI2_RESET					47
+#define SFAB_CFPB_M_RESET				48
+#define CFPB_MASTER_RESET				49
+#define SFAB_CFPB_S_RESET				50
+#define CFPB_SPLITTER_RESET				51
+#define TSIF_RESET					52
+#define CE1_RESET					53
+#define CE2_RESET					54
+#define SFAB_SFPB_M_RESET				55
+#define SFAB_SFPB_S_RESET				56
+#define RPM_PROC_RESET					57
+#define RPM_BUS_RESET					58
+#define RPM_MSG_RAM_RESET				59
+#define PMIC_ARB0_RESET					60
+#define PMIC_ARB1_RESET					61
+#define PMIC_SSBI2_RESET				62
+#define SDC1_RESET					63
+#define SDC2_RESET					64
+#define SDC3_RESET					65
+#define SDC4_RESET					66
+#define SDC5_RESET					67
+#define USB_HS1_RESET					68
+#define USB_HS2_XCVR_RESET				69
+#define USB_HS2_RESET					70
+#define USB_FS1_XCVR_RESET				71
+#define USB_FS1_RESET					72
+#define USB_FS2_XCVR_RESET				73
+#define USB_FS2_RESET					74
+#define GSBI1_RESET					75
+#define GSBI2_RESET					76
+#define GSBI3_RESET					77
+#define GSBI4_RESET					78
+#define GSBI5_RESET					79
+#define GSBI6_RESET					80
+#define GSBI7_RESET					81
+#define GSBI8_RESET					82
+#define GSBI9_RESET					83
+#define GSBI10_RESET					84
+#define GSBI11_RESET					85
+#define GSBI12_RESET					86
+#define SPDM_RESET					87
+#define SEC_CTRL_RESET					88
+#define TLMM_H_RESET					89
+#define TLMM_RESET					90
+#define MARRM_PWRON_RESET				91
+#define MARM_RESET					92
+#define MAHB1_RESET					93
+#define SFAB_MSS_S_RESET				94
+#define MAHB2_RESET					95
+#define MODEM_SW_AHB_RESET				96
+#define MODEM_RESET					97
+#define SFAB_MSS_MDM1_RESET				98
+#define SFAB_MSS_MDM0_RESET				99
+#define MSS_SLP_RESET					100
+#define MSS_MARM_SAW_RESET				101
+#define MSS_WDOG_RESET					102
+#define TSSC_RESET					103
+#define PDM_RESET					104
+#define SCSS_CORE0_RESET				105
+#define SCSS_CORE0_POR_RESET				106
+#define SCSS_CORE1_RESET				107
+#define SCSS_CORE1_POR_RESET				108
+#define MPM_RESET					109
+#define EBI1_1X_DIV_RESET				110
+#define EBI1_RESET					111
+#define SFAB_SMPSS_S_RESET				112
+#define USB_PHY0_RESET					113
+#define USB_PHY1_RESET					114
+#define PRNG_RESET					115
+
+#endif
diff --git a/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h b/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h
new file mode 100644
index 0000000000..a840e68032
--- /dev/null
+++ b/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8960_H
+
+#define SFAB_MSS_Q6_SW_RESET				0
+#define SFAB_MSS_Q6_FW_RESET				1
+#define QDSS_STM_RESET					2
+#define AFAB_SMPSS_S_RESET				3
+#define AFAB_SMPSS_M1_RESET				4
+#define AFAB_SMPSS_M0_RESET				5
+#define AFAB_EBI1_CH0_RESET				6
+#define AFAB_EBI1_CH1_RESET				7
+#define SFAB_ADM0_M0_RESET				8
+#define SFAB_ADM0_M1_RESET				9
+#define SFAB_ADM0_M2_RESET				10
+#define ADM0_C2_RESET					11
+#define ADM0_C1_RESET					12
+#define ADM0_C0_RESET					13
+#define ADM0_PBUS_RESET					14
+#define ADM0_RESET					15
+#define QDSS_CLKS_SW_RESET				16
+#define QDSS_POR_RESET					17
+#define QDSS_TSCTR_RESET				18
+#define QDSS_HRESET_RESET				19
+#define QDSS_AXI_RESET					20
+#define QDSS_DBG_RESET					21
+#define PCIE_A_RESET					22
+#define PCIE_AUX_RESET					23
+#define PCIE_H_RESET					24
+#define SFAB_PCIE_M_RESET				25
+#define SFAB_PCIE_S_RESET				26
+#define SFAB_MSS_M_RESET				27
+#define SFAB_USB3_M_RESET				28
+#define SFAB_RIVA_M_RESET				29
+#define SFAB_LPASS_RESET				30
+#define SFAB_AFAB_M_RESET				31
+#define AFAB_SFAB_M0_RESET				32
+#define AFAB_SFAB_M1_RESET				33
+#define SFAB_SATA_S_RESET				34
+#define SFAB_DFAB_M_RESET				35
+#define DFAB_SFAB_M_RESET				36
+#define DFAB_SWAY0_RESET				37
+#define DFAB_SWAY1_RESET				38
+#define DFAB_ARB0_RESET					39
+#define DFAB_ARB1_RESET					40
+#define PPSS_PROC_RESET					41
+#define PPSS_RESET					42
+#define DMA_BAM_RESET					43
+#define SIC_TIC_RESET					44
+#define SLIMBUS_H_RESET					45
+#define SFAB_CFPB_M_RESET				46
+#define SFAB_CFPB_S_RESET				47
+#define TSIF_H_RESET					48
+#define CE1_H_RESET					49
+#define CE1_CORE_RESET					50
+#define CE1_SLEEP_RESET					51
+#define CE2_H_RESET					52
+#define CE2_CORE_RESET					53
+#define SFAB_SFPB_M_RESET				54
+#define SFAB_SFPB_S_RESET				55
+#define RPM_PROC_RESET					56
+#define PMIC_SSBI2_RESET				57
+#define SDC1_RESET					58
+#define SDC2_RESET					59
+#define SDC3_RESET					60
+#define SDC4_RESET					61
+#define SDC5_RESET					62
+#define DFAB_A2_RESET					63
+#define USB_HS1_RESET					64
+#define USB_HSIC_RESET					65
+#define USB_FS1_XCVR_RESET				66
+#define USB_FS1_RESET					67
+#define USB_FS2_XCVR_RESET				68
+#define USB_FS2_RESET					69
+#define GSBI1_RESET					70
+#define GSBI2_RESET					71
+#define GSBI3_RESET					72
+#define GSBI4_RESET					73
+#define GSBI5_RESET					74
+#define GSBI6_RESET					75
+#define GSBI7_RESET					76
+#define GSBI8_RESET					77
+#define GSBI9_RESET					78
+#define GSBI10_RESET					79
+#define GSBI11_RESET					80
+#define GSBI12_RESET					81
+#define SPDM_RESET					82
+#define TLMM_H_RESET					83
+#define SFAB_MSS_S_RESET				84
+#define MSS_SLP_RESET					85
+#define MSS_Q6SW_JTAG_RESET				86
+#define MSS_Q6FW_JTAG_RESET				87
+#define MSS_RESET					88
+#define SATA_H_RESET					89
+#define SATA_RXOOB_RESE					90
+#define SATA_PMALIVE_RESET				91
+#define SATA_SFAB_M_RESET				92
+#define TSSC_RESET					93
+#define PDM_RESET					94
+#define MPM_H_RESET					95
+#define MPM_RESET					96
+#define SFAB_SMPSS_S_RESET				97
+#define PRNG_RESET					98
+#define RIVA_RESET					99
+
+#endif
diff --git a/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h b/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h
new file mode 100644
index 0000000000..9bdf543229
--- /dev/null
+++ b/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8974_H
+
+#define GCC_SYSTEM_NOC_BCR			0
+#define GCC_CONFIG_NOC_BCR			1
+#define GCC_PERIPH_NOC_BCR			2
+#define GCC_IMEM_BCR				3
+#define GCC_MMSS_BCR				4
+#define GCC_QDSS_BCR				5
+#define GCC_USB_30_BCR				6
+#define GCC_USB3_PHY_BCR			7
+#define GCC_USB_HS_HSIC_BCR			8
+#define GCC_USB_HS_BCR				9
+#define GCC_USB2A_PHY_BCR			10
+#define GCC_USB2B_PHY_BCR			11
+#define GCC_SDCC1_BCR				12
+#define GCC_SDCC2_BCR				13
+#define GCC_SDCC3_BCR				14
+#define GCC_SDCC4_BCR				15
+#define GCC_BLSP1_BCR				16
+#define GCC_BLSP1_QUP1_BCR			17
+#define GCC_BLSP1_UART1_BCR			18
+#define GCC_BLSP1_QUP2_BCR			19
+#define GCC_BLSP1_UART2_BCR			20
+#define GCC_BLSP1_QUP3_BCR			21
+#define GCC_BLSP1_UART3_BCR			22
+#define GCC_BLSP1_QUP4_BCR			23
+#define GCC_BLSP1_UART4_BCR			24
+#define GCC_BLSP1_QUP5_BCR			25
+#define GCC_BLSP1_UART5_BCR			26
+#define GCC_BLSP1_QUP6_BCR			27
+#define GCC_BLSP1_UART6_BCR			28
+#define GCC_BLSP2_BCR				29
+#define GCC_BLSP2_QUP1_BCR			30
+#define GCC_BLSP2_UART1_BCR			31
+#define GCC_BLSP2_QUP2_BCR			32
+#define GCC_BLSP2_UART2_BCR			33
+#define GCC_BLSP2_QUP3_BCR			34
+#define GCC_BLSP2_UART3_BCR			35
+#define GCC_BLSP2_QUP4_BCR			36
+#define GCC_BLSP2_UART4_BCR			37
+#define GCC_BLSP2_QUP5_BCR			38
+#define GCC_BLSP2_UART5_BCR			39
+#define GCC_BLSP2_QUP6_BCR			40
+#define GCC_BLSP2_UART6_BCR			41
+#define GCC_PDM_BCR				42
+#define GCC_BAM_DMA_BCR				43
+#define GCC_TSIF_BCR				44
+#define GCC_TCSR_BCR				45
+#define GCC_BOOT_ROM_BCR			46
+#define GCC_MSG_RAM_BCR				47
+#define GCC_TLMM_BCR				48
+#define GCC_MPM_BCR				49
+#define GCC_SEC_CTRL_BCR			50
+#define GCC_SPMI_BCR				51
+#define GCC_SPDM_BCR				52
+#define GCC_CE1_BCR				53
+#define GCC_CE2_BCR				54
+#define GCC_BIMC_BCR				55
+#define GCC_MPM_NON_AHB_RESET			56
+#define GCC_MPM_AHB_RESET			57
+#define GCC_SNOC_BUS_TIMEOUT0_BCR		58
+#define GCC_SNOC_BUS_TIMEOUT2_BCR		59
+#define GCC_PNOC_BUS_TIMEOUT0_BCR		60
+#define GCC_PNOC_BUS_TIMEOUT1_BCR		61
+#define GCC_PNOC_BUS_TIMEOUT2_BCR		62
+#define GCC_PNOC_BUS_TIMEOUT3_BCR		63
+#define GCC_PNOC_BUS_TIMEOUT4_BCR		64
+#define GCC_CNOC_BUS_TIMEOUT0_BCR		65
+#define GCC_CNOC_BUS_TIMEOUT1_BCR		66
+#define GCC_CNOC_BUS_TIMEOUT2_BCR		67
+#define GCC_CNOC_BUS_TIMEOUT3_BCR		68
+#define GCC_CNOC_BUS_TIMEOUT4_BCR		69
+#define GCC_CNOC_BUS_TIMEOUT5_BCR		70
+#define GCC_CNOC_BUS_TIMEOUT6_BCR		71
+#define GCC_DEHR_BCR				72
+#define GCC_RBCPR_BCR				73
+#define GCC_MSS_RESTART				74
+#define GCC_LPASS_RESTART			75
+#define GCC_WCSS_RESTART			76
+#define GCC_VENUS_RESTART			77
+
+#endif
diff --git a/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h
new file mode 100644
index 0000000000..ba36ec6801
--- /dev/null
+++ b/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H
+#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H
+
+#define VPE_AXI_RESET					0
+#define IJPEG_AXI_RESET					1
+#define MPD_AXI_RESET					2
+#define VFE_AXI_RESET					3
+#define SP_AXI_RESET					4
+#define VCODEC_AXI_RESET				5
+#define ROT_AXI_RESET					6
+#define VCODEC_AXI_A_RESET				7
+#define VCODEC_AXI_B_RESET				8
+#define FAB_S3_AXI_RESET				9
+#define FAB_S2_AXI_RESET				10
+#define FAB_S1_AXI_RESET				11
+#define FAB_S0_AXI_RESET				12
+#define SMMU_GFX3D_ABH_RESET				13
+#define SMMU_VPE_AHB_RESET				14
+#define SMMU_VFE_AHB_RESET				15
+#define SMMU_ROT_AHB_RESET				16
+#define SMMU_VCODEC_B_AHB_RESET				17
+#define SMMU_VCODEC_A_AHB_RESET				18
+#define SMMU_MDP1_AHB_RESET				19
+#define SMMU_MDP0_AHB_RESET				20
+#define SMMU_JPEGD_AHB_RESET				21
+#define SMMU_IJPEG_AHB_RESET				22
+#define SMMU_GFX2D0_AHB_RESET				23
+#define SMMU_GFX2D1_AHB_RESET				24
+#define APU_AHB_RESET					25
+#define CSI_AHB_RESET					26
+#define TV_ENC_AHB_RESET				27
+#define VPE_AHB_RESET					28
+#define FABRIC_AHB_RESET				29
+#define GFX2D0_AHB_RESET				30
+#define GFX2D1_AHB_RESET				31
+#define GFX3D_AHB_RESET					32
+#define HDMI_AHB_RESET					33
+#define MSSS_IMEM_AHB_RESET				34
+#define IJPEG_AHB_RESET					35
+#define DSI_M_AHB_RESET					36
+#define DSI_S_AHB_RESET					37
+#define JPEGD_AHB_RESET					38
+#define MDP_AHB_RESET					39
+#define ROT_AHB_RESET					40
+#define VCODEC_AHB_RESET				41
+#define VFE_AHB_RESET					42
+#define DSI2_M_AHB_RESET				43
+#define DSI2_S_AHB_RESET				44
+#define CSIPHY2_RESET					45
+#define CSI_PIX1_RESET					46
+#define CSIPHY0_RESET					47
+#define CSIPHY1_RESET					48
+#define DSI2_RESET					49
+#define VFE_CSI_RESET					50
+#define MDP_RESET					51
+#define AMP_RESET					52
+#define JPEGD_RESET					53
+#define CSI1_RESET					54
+#define VPE_RESET					55
+#define MMSS_FABRIC_RESET				56
+#define VFE_RESET					57
+#define GFX2D0_RESET					58
+#define GFX2D1_RESET					59
+#define GFX3D_RESET					60
+#define HDMI_RESET					61
+#define MMSS_IMEM_RESET					62
+#define IJPEG_RESET					63
+#define CSI0_RESET					64
+#define DSI_RESET					65
+#define VCODEC_RESET					66
+#define MDP_TV_RESET					67
+#define MDP_VSYNC_RESET					68
+#define ROT_RESET					69
+#define TV_HDMI_RESET					70
+#define TV_ENC_RESET					71
+#define CSI2_RESET					72
+#define CSI_RDI1_RESET					73
+#define CSI_RDI2_RESET					74
+
+#endif
diff --git a/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h
new file mode 100644
index 0000000000..da3ec37f1b
--- /dev/null
+++ b/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H
+#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H
+
+#define SPDM_RESET			0
+#define SPDM_RM_RESET			1
+#define VENUS0_RESET			2
+#define MDSS_RESET			3
+#define CAMSS_PHY0_RESET		4
+#define CAMSS_PHY1_RESET		5
+#define CAMSS_PHY2_RESET		6
+#define CAMSS_CSI0_RESET		7
+#define CAMSS_CSI0PHY_RESET		8
+#define CAMSS_CSI0RDI_RESET		9
+#define CAMSS_CSI0PIX_RESET		10
+#define CAMSS_CSI1_RESET		11
+#define CAMSS_CSI1PHY_RESET		12
+#define CAMSS_CSI1RDI_RESET		13
+#define CAMSS_CSI1PIX_RESET		14
+#define CAMSS_CSI2_RESET		15
+#define CAMSS_CSI2PHY_RESET		16
+#define CAMSS_CSI2RDI_RESET		17
+#define CAMSS_CSI2PIX_RESET		18
+#define CAMSS_CSI3_RESET		19
+#define CAMSS_CSI3PHY_RESET		20
+#define CAMSS_CSI3RDI_RESET		21
+#define CAMSS_CSI3PIX_RESET		22
+#define CAMSS_ISPIF_RESET		23
+#define CAMSS_CCI_RESET			24
+#define CAMSS_MCLK0_RESET		25
+#define CAMSS_MCLK1_RESET		26
+#define CAMSS_MCLK2_RESET		27
+#define CAMSS_MCLK3_RESET		28
+#define CAMSS_GP0_RESET			29
+#define CAMSS_GP1_RESET			30
+#define CAMSS_TOP_RESET			31
+#define CAMSS_MICRO_RESET		32
+#define CAMSS_JPEG_RESET		33
+#define CAMSS_VFE_RESET			34
+#define CAMSS_CSI_VFE0_RESET		35
+#define CAMSS_CSI_VFE1_RESET		36
+#define OXILI_RESET			37
+#define OXILICX_RESET			38
+#define OCMEMCX_RESET			39
+#define MMSS_RBCRP_RESET		40
+#define MMSSNOCAHB_RESET		41
+#define MMSSNOCAXI_RESET		42
+#define OCMEMNOC_RESET			43
+
+#endif