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authorSascha Hauer <s.hauer@pengutronix.de>2017-01-10 08:26:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-01-10 08:48:45 +0100
commita40531fb3c11dc4ee8cca43c91b471da1fd3c1ab (patch)
tree35f886d87a77df7bac8a587a04647691db541a2e /dts/include/dt-bindings
parent81462901ce3d677ce318150f7027e2ce1cf97c41 (diff)
downloadbarebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.gz
barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.xz
dts: update to v4.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include/dt-bindings')
-rw-r--r--dts/include/dt-bindings/clock/hi3516cv300-clock.h48
-rw-r--r--dts/include/dt-bindings/clock/histb-clock.h66
-rw-r--r--dts/include/dt-bindings/clock/imx6ul-clock.h15
-rw-r--r--dts/include/dt-bindings/clock/oxsemi,ox810se.h30
-rw-r--r--dts/include/dt-bindings/clock/oxsemi,ox820.h40
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8994.h137
-rw-r--r--dts/include/dt-bindings/clock/qcom,rpmcc.h69
-rw-r--r--dts/include/dt-bindings/clock/r7s72100-clock.h7
-rw-r--r--dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h43
-rw-r--r--dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h44
-rw-r--r--dts/include/dt-bindings/clock/r8a7794-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/rk1108-cru.h269
-rw-r--r--dts/include/dt-bindings/clock/rk3188-cru-common.h8
-rw-r--r--dts/include/dt-bindings/clock/stih415-clks.h16
-rw-r--r--dts/include/dt-bindings/clock/sun50i-a64-ccu.h134
-rw-r--r--dts/include/dt-bindings/clock/tegra186-clock.h940
-rw-r--r--dts/include/dt-bindings/gpio/meson-gxl-gpio.h131
-rw-r--r--dts/include/dt-bindings/mailbox/tegra186-hsp.h24
-rw-r--r--dts/include/dt-bindings/mfd/tps65217.h26
-rw-r--r--dts/include/dt-bindings/net/mscc-phy-vsc8531.h21
-rw-r--r--dts/include/dt-bindings/pinctrl/at91.h2
-rw-r--r--dts/include/dt-bindings/pinctrl/bcm2835.h5
-rw-r--r--dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h4
-rw-r--r--dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h6
-rw-r--r--dts/include/dt-bindings/pinctrl/rockchip.h33
-rw-r--r--dts/include/dt-bindings/power/mt2701-power.h27
-rw-r--r--dts/include/dt-bindings/power/r8a7743-sysc.h25
-rw-r--r--dts/include/dt-bindings/power/r8a7745-sysc.h25
-rw-r--r--dts/include/dt-bindings/power/tegra186-powergate.h39
-rw-r--r--dts/include/dt-bindings/reset/oxsemi,ox810se.h53
-rw-r--r--dts/include/dt-bindings/reset/oxsemi,ox820.h53
-rw-r--r--dts/include/dt-bindings/reset/sun50i-a64-ccu.h98
-rw-r--r--dts/include/dt-bindings/reset/tegra186-reset.h217
-rw-r--r--dts/include/dt-bindings/sound/cs42l42.h73
34 files changed, 2690 insertions, 41 deletions
diff --git a/dts/include/dt-bindings/clock/hi3516cv300-clock.h b/dts/include/dt-bindings/clock/hi3516cv300-clock.h
new file mode 100644
index 0000000000..5ba51b8388
--- /dev/null
+++ b/dts/include/dt-bindings/clock/hi3516cv300-clock.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3516CV300_CLOCK_H
+#define __DTS_HI3516CV300_CLOCK_H
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_APB_CLK 0
+#define HI3516CV300_UART0_CLK 1
+#define HI3516CV300_UART1_CLK 2
+#define HI3516CV300_UART2_CLK 3
+#define HI3516CV300_SPI0_CLK 4
+#define HI3516CV300_SPI1_CLK 5
+#define HI3516CV300_FMC_CLK 6
+#define HI3516CV300_MMC0_CLK 7
+#define HI3516CV300_MMC1_CLK 8
+#define HI3516CV300_MMC2_CLK 9
+#define HI3516CV300_MMC3_CLK 10
+#define HI3516CV300_ETH_CLK 11
+#define HI3516CV300_ETH_MACIF_CLK 12
+#define HI3516CV300_DMAC_CLK 13
+#define HI3516CV300_PWM_CLK 14
+#define HI3516CV300_USB2_BUS_CLK 15
+#define HI3516CV300_USB2_OHCI48M_CLK 16
+#define HI3516CV300_USB2_OHCI12M_CLK 17
+#define HI3516CV300_USB2_OTG_UTMI_CLK 18
+#define HI3516CV300_USB2_HST_PHY_CLK 19
+#define HI3516CV300_USB2_UTMI0_CLK 20
+#define HI3516CV300_USB2_PHY_CLK 21
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_WDT_CLK 1
+
+#endif /* __DTS_HI3516CV300_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/histb-clock.h b/dts/include/dt-bindings/clock/histb-clock.h
new file mode 100644
index 0000000000..181c0f070f
--- /dev/null
+++ b/dts/include/dt-bindings/clock/histb-clock.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK 0
+#define HISTB_APB_CLK 1
+#define HISTB_AHB_CLK 2
+#define HISTB_UART1_CLK 3
+#define HISTB_UART2_CLK 4
+#define HISTB_UART3_CLK 5
+#define HISTB_I2C0_CLK 6
+#define HISTB_I2C1_CLK 7
+#define HISTB_I2C2_CLK 8
+#define HISTB_I2C3_CLK 9
+#define HISTB_I2C4_CLK 10
+#define HISTB_I2C5_CLK 11
+#define HISTB_SPI0_CLK 12
+#define HISTB_SPI1_CLK 13
+#define HISTB_SPI2_CLK 14
+#define HISTB_SCI_CLK 15
+#define HISTB_FMC_CLK 16
+#define HISTB_MMC_BIU_CLK 17
+#define HISTB_MMC_CIU_CLK 18
+#define HISTB_MMC_DRV_CLK 19
+#define HISTB_MMC_SAMPLE_CLK 20
+#define HISTB_SDIO0_BIU_CLK 21
+#define HISTB_SDIO0_CIU_CLK 22
+#define HISTB_SDIO0_DRV_CLK 23
+#define HISTB_SDIO0_SAMPLE_CLK 24
+#define HISTB_PCIE_AUX_CLK 25
+#define HISTB_PCIE_PIPE_CLK 26
+#define HISTB_PCIE_SYS_CLK 27
+#define HISTB_PCIE_BUS_CLK 28
+#define HISTB_ETH0_MAC_CLK 29
+#define HISTB_ETH0_MACIF_CLK 30
+#define HISTB_ETH1_MAC_CLK 31
+#define HISTB_ETH1_MACIF_CLK 32
+#define HISTB_COMBPHY1_CLK 33
+
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK 1
+#define HISTB_IR_CLK 2
+#define HISTB_TIMER01_CLK 3
+#define HISTB_LEDC_CLK 4
+#define HISTB_UART0_CLK 5
+#define HISTB_LSADC_CLK 6
+
+#endif /* __DTS_HISTB_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/imx6ul-clock.h b/dts/include/dt-bindings/clock/imx6ul-clock.h
index fd8aee8f64..ee9f1a508d 100644
--- a/dts/include/dt-bindings/clock/imx6ul-clock.h
+++ b/dts/include/dt-bindings/clock/imx6ul-clock.h
@@ -236,6 +236,19 @@
#define IMX6UL_CLK_PLL3_120M 223
#define IMX6UL_CLK_KPP 224
-#define IMX6UL_CLK_END 225
+/* For i.MX6ULL */
+#define IMX6ULL_CLK_ESAI_PRED 225
+#define IMX6ULL_CLK_ESAI_PODF 226
+#define IMX6ULL_CLK_ESAI_EXTAL 227
+#define IMX6ULL_CLK_ESAI_MEM 228
+#define IMX6ULL_CLK_ESAI_IPG 229
+#define IMX6ULL_CLK_DCP_CLK 230
+#define IMX6ULL_CLK_EPDC_PRE_SEL 231
+#define IMX6ULL_CLK_EPDC_SEL 232
+#define IMX6ULL_CLK_EPDC_PODF 233
+#define IMX6ULL_CLK_EPDC_ACLK 234
+#define IMX6ULL_CLK_EPDC_PIX 235
+#define IMX6ULL_CLK_ESAI_SEL 236
+#define IMX6UL_CLK_END 237
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/dts/include/dt-bindings/clock/oxsemi,ox810se.h b/dts/include/dt-bindings/clock/oxsemi,ox810se.h
new file mode 100644
index 0000000000..d5facb5e83
--- /dev/null
+++ b/dts/include/dt-bindings/clock/oxsemi,ox810se.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_CLOCK_OXSEMI_OX810SE_H
+#define DT_CLOCK_OXSEMI_OX810SE_H
+
+#define CLK_810_LEON 0
+#define CLK_810_DMA_SGDMA 1
+#define CLK_810_CIPHER 2
+#define CLK_810_SATA 3
+#define CLK_810_AUDIO 4
+#define CLK_810_USBMPH 5
+#define CLK_810_ETHA 6
+#define CLK_810_PCIEA 7
+#define CLK_810_NAND 8
+
+#endif /* DT_CLOCK_OXSEMI_OX810SE_H */
diff --git a/dts/include/dt-bindings/clock/oxsemi,ox820.h b/dts/include/dt-bindings/clock/oxsemi,ox820.h
new file mode 100644
index 0000000000..f661ecc8d7
--- /dev/null
+++ b/dts/include/dt-bindings/clock/oxsemi,ox820.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_CLOCK_OXSEMI_OX820_H
+#define DT_CLOCK_OXSEMI_OX820_H
+
+/* PLLs */
+#define CLK_820_PLLA 0
+#define CLK_820_PLLB 1
+
+/* Gate Clocks */
+#define CLK_820_LEON 2
+#define CLK_820_DMA_SGDMA 3
+#define CLK_820_CIPHER 4
+#define CLK_820_SD 5
+#define CLK_820_SATA 6
+#define CLK_820_AUDIO 7
+#define CLK_820_USBMPH 8
+#define CLK_820_ETHA 9
+#define CLK_820_PCIEA 10
+#define CLK_820_NAND 11
+#define CLK_820_PCIEB 12
+#define CLK_820_ETHB 13
+#define CLK_820_REF600 14
+#define CLK_820_USBDEV 15
+
+#endif /* DT_CLOCK_OXSEMI_OX820_H */
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-msm8994.h b/dts/include/dt-bindings/clock/qcom,gcc-msm8994.h
new file mode 100644
index 0000000000..8fa535be2e
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
+
+#define GPLL0_EARLY 0
+#define GPLL0 1
+#define GPLL4_EARLY 2
+#define GPLL4 3
+#define UFS_AXI_CLK_SRC 4
+#define USB30_MASTER_CLK_SRC 5
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
+#define BLSP1_UART1_APPS_CLK_SRC 18
+#define BLSP1_UART2_APPS_CLK_SRC 19
+#define BLSP1_UART3_APPS_CLK_SRC 20
+#define BLSP1_UART4_APPS_CLK_SRC 21
+#define BLSP1_UART5_APPS_CLK_SRC 22
+#define BLSP1_UART6_APPS_CLK_SRC 23
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
+#define BLSP2_UART1_APPS_CLK_SRC 36
+#define BLSP2_UART2_APPS_CLK_SRC 37
+#define BLSP2_UART3_APPS_CLK_SRC 38
+#define BLSP2_UART4_APPS_CLK_SRC 39
+#define BLSP2_UART5_APPS_CLK_SRC 40
+#define BLSP2_UART6_APPS_CLK_SRC 41
+#define GP1_CLK_SRC 42
+#define GP2_CLK_SRC 43
+#define GP3_CLK_SRC 44
+#define PCIE_0_AUX_CLK_SRC 45
+#define PCIE_0_PIPE_CLK_SRC 46
+#define PCIE_1_AUX_CLK_SRC 47
+#define PCIE_1_PIPE_CLK_SRC 48
+#define PDM2_CLK_SRC 49
+#define SDCC1_APPS_CLK_SRC 50
+#define SDCC2_APPS_CLK_SRC 51
+#define SDCC3_APPS_CLK_SRC 52
+#define SDCC4_APPS_CLK_SRC 53
+#define TSIF_REF_CLK_SRC 54
+#define USB30_MOCK_UTMI_CLK_SRC 55
+#define USB3_PHY_AUX_CLK_SRC 56
+#define USB_HS_SYSTEM_CLK_SRC 57
+#define GCC_BLSP1_AHB_CLK 58
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
+#define GCC_BLSP1_UART1_APPS_CLK 71
+#define GCC_BLSP1_UART2_APPS_CLK 72
+#define GCC_BLSP1_UART3_APPS_CLK 73
+#define GCC_BLSP1_UART4_APPS_CLK 74
+#define GCC_BLSP1_UART5_APPS_CLK 75
+#define GCC_BLSP1_UART6_APPS_CLK 76
+#define GCC_BLSP2_AHB_CLK 77
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
+#define GCC_BLSP2_UART1_APPS_CLK 90
+#define GCC_BLSP2_UART2_APPS_CLK 91
+#define GCC_BLSP2_UART3_APPS_CLK 92
+#define GCC_BLSP2_UART4_APPS_CLK 93
+#define GCC_BLSP2_UART5_APPS_CLK 94
+#define GCC_BLSP2_UART6_APPS_CLK 95
+#define GCC_GP1_CLK 96
+#define GCC_GP2_CLK 97
+#define GCC_GP3_CLK 98
+#define GCC_PCIE_0_AUX_CLK 99
+#define GCC_PCIE_0_PIPE_CLK 100
+#define GCC_PCIE_1_AUX_CLK 101
+#define GCC_PCIE_1_PIPE_CLK 102
+#define GCC_PDM2_CLK 103
+#define GCC_SDCC1_APPS_CLK 104
+#define GCC_SDCC2_APPS_CLK 105
+#define GCC_SDCC3_APPS_CLK 106
+#define GCC_SDCC4_APPS_CLK 107
+#define GCC_SYS_NOC_UFS_AXI_CLK 108
+#define GCC_SYS_NOC_USB3_AXI_CLK 109
+#define GCC_TSIF_REF_CLK 110
+#define GCC_UFS_AXI_CLK 111
+#define GCC_UFS_RX_CFG_CLK 112
+#define GCC_UFS_TX_CFG_CLK 113
+#define GCC_USB30_MASTER_CLK 114
+#define GCC_USB30_MOCK_UTMI_CLK 115
+#define GCC_USB3_PHY_AUX_CLK 116
+#define GCC_USB_HS_SYSTEM_CLK 117
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,rpmcc.h b/dts/include/dt-bindings/clock/qcom,rpmcc.h
new file mode 100644
index 0000000000..5924cdb713
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,rpmcc.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
+#define _DT_BINDINGS_CLK_MSM_RPMCC_H
+
+/* apq8064 */
+#define RPM_PXO_CLK 0
+#define RPM_PXO_A_CLK 1
+#define RPM_CXO_CLK 2
+#define RPM_CXO_A_CLK 3
+#define RPM_APPS_FABRIC_CLK 4
+#define RPM_APPS_FABRIC_A_CLK 5
+#define RPM_CFPB_CLK 6
+#define RPM_CFPB_A_CLK 7
+#define RPM_QDSS_CLK 8
+#define RPM_QDSS_A_CLK 9
+#define RPM_DAYTONA_FABRIC_CLK 10
+#define RPM_DAYTONA_FABRIC_A_CLK 11
+#define RPM_EBI1_CLK 12
+#define RPM_EBI1_A_CLK 13
+#define RPM_MM_FABRIC_CLK 14
+#define RPM_MM_FABRIC_A_CLK 15
+#define RPM_MMFPB_CLK 16
+#define RPM_MMFPB_A_CLK 17
+#define RPM_SYS_FABRIC_CLK 18
+#define RPM_SYS_FABRIC_A_CLK 19
+#define RPM_SFPB_CLK 20
+#define RPM_SFPB_A_CLK 21
+
+/* msm8916 */
+#define RPM_SMD_XO_CLK_SRC 0
+#define RPM_SMD_XO_A_CLK_SRC 1
+#define RPM_SMD_PCNOC_CLK 2
+#define RPM_SMD_PCNOC_A_CLK 3
+#define RPM_SMD_SNOC_CLK 4
+#define RPM_SMD_SNOC_A_CLK 5
+#define RPM_SMD_BIMC_CLK 6
+#define RPM_SMD_BIMC_A_CLK 7
+#define RPM_SMD_QDSS_CLK 8
+#define RPM_SMD_QDSS_A_CLK 9
+#define RPM_SMD_BB_CLK1 10
+#define RPM_SMD_BB_CLK1_A 11
+#define RPM_SMD_BB_CLK2 12
+#define RPM_SMD_BB_CLK2_A 13
+#define RPM_SMD_RF_CLK1 14
+#define RPM_SMD_RF_CLK1_A 15
+#define RPM_SMD_RF_CLK2 16
+#define RPM_SMD_RF_CLK2_A 17
+#define RPM_SMD_BB_CLK1_PIN 18
+#define RPM_SMD_BB_CLK1_A_PIN 19
+#define RPM_SMD_BB_CLK2_PIN 20
+#define RPM_SMD_BB_CLK2_A_PIN 21
+#define RPM_SMD_RF_CLK1_PIN 22
+#define RPM_SMD_RF_CLK1_A_PIN 23
+#define RPM_SMD_RF_CLK2_PIN 24
+#define RPM_SMD_RF_CLK2_A_PIN 25
+
+#endif
diff --git a/dts/include/dt-bindings/clock/r7s72100-clock.h b/dts/include/dt-bindings/clock/r7s72100-clock.h
index 3cd813896d..29e01ed10e 100644
--- a/dts/include/dt-bindings/clock/r7s72100-clock.h
+++ b/dts/include/dt-bindings/clock/r7s72100-clock.h
@@ -28,6 +28,9 @@
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
+/* MSTP8 */
+#define R7S72100_CLK_MMCIF 4
+
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6
@@ -41,4 +44,8 @@
#define R7S72100_CLK_SPI3 4
#define R7S72100_CLK_SPI4 3
+/* MSTP12 */
+#define R7S72100_CLK_SDHI0 3
+#define R7S72100_CLK_SDHI1 2
+
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h
new file mode 100644
index 0000000000..e1d1f3c6a9
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7743 CPG Core Clocks */
+#define R8A7743_CLK_Z 0
+#define R8A7743_CLK_ZG 1
+#define R8A7743_CLK_ZTR 2
+#define R8A7743_CLK_ZTRD2 3
+#define R8A7743_CLK_ZT 4
+#define R8A7743_CLK_ZX 5
+#define R8A7743_CLK_ZS 6
+#define R8A7743_CLK_HP 7
+#define R8A7743_CLK_B 9
+#define R8A7743_CLK_LB 10
+#define R8A7743_CLK_P 11
+#define R8A7743_CLK_CL 12
+#define R8A7743_CLK_M2 13
+#define R8A7743_CLK_ZB3 15
+#define R8A7743_CLK_ZB3D2 16
+#define R8A7743_CLK_DDR 17
+#define R8A7743_CLK_SDH 18
+#define R8A7743_CLK_SD0 19
+#define R8A7743_CLK_SD2 20
+#define R8A7743_CLK_SD3 21
+#define R8A7743_CLK_MMC0 22
+#define R8A7743_CLK_MP 23
+#define R8A7743_CLK_QSPI 26
+#define R8A7743_CLK_CP 27
+#define R8A7743_CLK_RCAN 28
+#define R8A7743_CLK_R 29
+#define R8A7743_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h
new file mode 100644
index 0000000000..56ad6f0c67
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7745 CPG Core Clocks */
+#define R8A7745_CLK_Z2 0
+#define R8A7745_CLK_ZG 1
+#define R8A7745_CLK_ZTR 2
+#define R8A7745_CLK_ZTRD2 3
+#define R8A7745_CLK_ZT 4
+#define R8A7745_CLK_ZX 5
+#define R8A7745_CLK_ZS 6
+#define R8A7745_CLK_HP 7
+#define R8A7745_CLK_B 9
+#define R8A7745_CLK_LB 10
+#define R8A7745_CLK_P 11
+#define R8A7745_CLK_CL 12
+#define R8A7745_CLK_CP 13
+#define R8A7745_CLK_M2 14
+#define R8A7745_CLK_ZB3 16
+#define R8A7745_CLK_ZB3D2 17
+#define R8A7745_CLK_DDR 18
+#define R8A7745_CLK_SDH 19
+#define R8A7745_CLK_SD0 20
+#define R8A7745_CLK_SD2 21
+#define R8A7745_CLK_SD3 22
+#define R8A7745_CLK_MMC0 23
+#define R8A7745_CLK_MP 24
+#define R8A7745_CLK_QSPI 25
+#define R8A7745_CLK_CPEX 26
+#define R8A7745_CLK_RCAN 27
+#define R8A7745_CLK_R 28
+#define R8A7745_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7794-clock.h b/dts/include/dt-bindings/clock/r8a7794-clock.h
index 9d02f5317c..88e64846cf 100644
--- a/dts/include/dt-bindings/clock/r8a7794-clock.h
+++ b/dts/include/dt-bindings/clock/r8a7794-clock.h
@@ -20,8 +20,7 @@
#define R8A7794_CLK_QSPI 5
#define R8A7794_CLK_SDH 6
#define R8A7794_CLK_SD0 7
-#define R8A7794_CLK_Z 8
-#define R8A7794_CLK_RCAN 9
+#define R8A7794_CLK_RCAN 8
/* MSTP0 */
#define R8A7794_CLK_MSIOF0 0
diff --git a/dts/include/dt-bindings/clock/rk1108-cru.h b/dts/include/dt-bindings/clock/rk1108-cru.h
new file mode 100644
index 0000000000..9350a5527a
--- /dev/null
+++ b/dts/include/dt-bindings/clock/rk1108-cru.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
+
+/* pll id */
+#define PLL_APLL 0
+#define PLL_DPLL 1
+#define PLL_GPLL 2
+#define ARMCLK 3
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0 65
+#define SCLK_NANDC 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_UART0 72
+#define SCLK_UART1 73
+#define SCLK_UART2 74
+#define SCLK_I2S0 75
+#define SCLK_I2S1 76
+#define SCLK_I2S2 77
+#define SCLK_TIMER0 78
+#define SCLK_TIMER1 79
+#define SCLK_SFC 80
+#define SCLK_SDMMC_DRV 81
+#define SCLK_SDIO_DRV 82
+#define SCLK_EMMC_DRV 83
+#define SCLK_SDMMC_SAMPLE 84
+#define SCLK_SDIO_SAMPLE 85
+#define SCLK_EMMC_SAMPLE 86
+
+/* aclk gates */
+#define ACLK_DMAC 192
+#define ACLK_PRE 193
+#define ACLK_CORE 194
+#define ACLK_ENMCORE 195
+
+/* pclk gates */
+#define PCLK_GPIO1 256
+#define PCLK_GPIO2 257
+#define PCLK_GPIO3 258
+#define PCLK_GRF 259
+#define PCLK_I2C1 260
+#define PCLK_I2C2 261
+#define PCLK_I2C3 262
+#define PCLK_SPI 263
+#define PCLK_SFC 264
+#define PCLK_UART0 265
+#define PCLK_UART1 266
+#define PCLK_UART2 267
+#define PCLK_TSADC 268
+#define PCLK_PWM 269
+#define PCLK_TIMER 270
+#define PCLK_PERI 271
+
+/* hclk gates */
+#define HCLK_I2S0_8CH 320
+#define HCLK_I2S1_8CH 321
+#define HCLK_I2S2_2CH 322
+#define HCLK_NANDC 323
+#define HCLK_SDMMC 324
+#define HCLK_SDIO 325
+#define HCLK_EMMC 326
+#define HCLK_PERI 327
+#define HCLK_SFC 328
+
+#define CLK_NR_CLKS (HCLK_SFC + 1)
+
+/* reset id */
+#define SRST_CORE_PO_AD 0
+#define SRST_CORE_AD 1
+#define SRST_L2_AD 2
+#define SRST_CPU_NIU_AD 3
+#define SRST_CORE_PO 4
+#define SRST_CORE 5
+#define SRST_L2 6
+#define SRST_CORE_DBG 8
+#define PRST_DBG 9
+#define RST_DAP 10
+#define PRST_DBG_NIU 11
+#define ARST_STRC_SYS_AD 15
+
+#define SRST_DDRPHY_CLKDIV 16
+#define SRST_DDRPHY 17
+#define PRST_DDRPHY 18
+#define PRST_HDMIPHY 19
+#define PRST_VDACPHY 20
+#define PRST_VADCPHY 21
+#define PRST_MIPI_CSI_PHY 22
+#define PRST_MIPI_DSI_PHY 23
+#define PRST_ACODEC 24
+#define ARST_BUS_NIU 25
+#define PRST_TOP_NIU 26
+#define ARST_INTMEM 27
+#define HRST_ROM 28
+#define ARST_DMAC 29
+#define SRST_MSCH_NIU 30
+#define PRST_MSCH_NIU 31
+
+#define PRST_DDRUPCTL 32
+#define NRST_DDRUPCTL 33
+#define PRST_DDRMON 34
+#define HRST_I2S0_8CH 35
+#define MRST_I2S0_8CH 36
+#define HRST_I2S1_2CH 37
+#define MRST_IS21_2CH 38
+#define HRST_I2S2_2CH 39
+#define MRST_I2S2_2CH 40
+#define HRST_CRYPTO 41
+#define SRST_CRYPTO 42
+#define PRST_SPI 43
+#define SRST_SPI 44
+#define PRST_UART0 45
+#define PRST_UART1 46
+#define PRST_UART2 47
+
+#define SRST_UART0 48
+#define SRST_UART1 49
+#define SRST_UART2 50
+#define PRST_I2C1 51
+#define PRST_I2C2 52
+#define PRST_I2C3 53
+#define SRST_I2C1 54
+#define SRST_I2C2 55
+#define SRST_I2C3 56
+#define PRST_PWM1 58
+#define SRST_PWM1 60
+#define PRST_WDT 61
+#define PRST_GPIO1 62
+#define PRST_GPIO2 63
+
+#define PRST_GPIO3 64
+#define PRST_GRF 65
+#define PRST_EFUSE 66
+#define PRST_EFUSE512 67
+#define PRST_TIMER0 68
+#define SRST_TIMER0 69
+#define SRST_TIMER1 70
+#define PRST_TSADC 71
+#define SRST_TSADC 72
+#define PRST_SARADC 73
+#define SRST_SARADC 74
+#define HRST_SYSBUS 75
+#define PRST_USBGRF 76
+
+#define ARST_PERIPH_NIU 80
+#define HRST_PERIPH_NIU 81
+#define PRST_PERIPH_NIU 82
+#define HRST_PERIPH 83
+#define HRST_SDMMC 84
+#define HRST_SDIO 85
+#define HRST_EMMC 86
+#define HRST_NANDC 87
+#define NRST_NANDC 88
+#define HRST_SFC 89
+#define SRST_SFC 90
+#define ARST_GMAC 91
+#define HRST_OTG 92
+#define SRST_OTG 93
+#define SRST_OTG_ADP 94
+#define HRST_HOST0 95
+
+#define HRST_HOST0_AUX 96
+#define HRST_HOST0_ARB 97
+#define SRST_HOST0_EHCIPHY 98
+#define SRST_HOST0_UTMI 99
+#define SRST_USBPOR 100
+#define SRST_UTMI0 101
+#define SRST_UTMI1 102
+
+#define ARST_VIO0_NIU 102
+#define ARST_VIO1_NIU 103
+#define HRST_VIO_NIU 104
+#define PRST_VIO_NIU 105
+#define ARST_VOP 106
+#define HRST_VOP 107
+#define DRST_VOP 108
+#define ARST_IEP 109
+#define HRST_IEP 110
+#define ARST_RGA 111
+#define HRST_RGA 112
+#define SRST_RGA 113
+#define PRST_CVBS 114
+#define PRST_HDMI 115
+#define SRST_HDMI 116
+#define PRST_MIPI_DSI 117
+
+#define ARST_ISP_NIU 118
+#define HRST_ISP_NIU 119
+#define HRST_ISP 120
+#define SRST_ISP 121
+#define ARST_VIP0 122
+#define HRST_VIP0 123
+#define PRST_VIP0 124
+#define ARST_VIP1 125
+#define HRST_VIP1 126
+#define PRST_VIP1 127
+#define ARST_VIP2 128
+#define HRST_VIP2 129
+#define PRST_VIP2 120
+#define ARST_VIP3 121
+#define HRST_VIP3 122
+#define PRST_VIP4 123
+
+#define PRST_CIF1TO4 124
+#define SRST_CVBS_CLK 125
+#define HRST_CVBS 126
+
+#define ARST_VPU_NIU 140
+#define HRST_VPU_NIU 141
+#define ARST_VPU 142
+#define HRST_VPU 143
+#define ARST_RKVDEC_NIU 144
+#define HRST_RKVDEC_NIU 145
+#define ARST_RKVDEC 146
+#define HRST_RKVDEC 147
+#define SRST_RKVDEC_CABAC 148
+#define SRST_RKVDEC_CORE 149
+#define ARST_RKVENC_NIU 150
+#define HRST_RKVENC_NIU 151
+#define ARST_RKVENC 152
+#define HRST_RKVENC 153
+#define SRST_RKVENC_CORE 154
+
+#define SRST_DSP_CORE 156
+#define SRST_DSP_SYS 157
+#define SRST_DSP_GLOBAL 158
+#define SRST_DSP_OECM 159
+#define PRST_DSP_IOP_NIU 160
+#define ARST_DSP_EPP_NIU 161
+#define ARST_DSP_EDP_NIU 162
+#define PRST_DSP_DBG_NIU 163
+#define PRST_DSP_CFG_NIU 164
+#define PRST_DSP_GRF 165
+#define PRST_DSP_MAILBOX 166
+#define PRST_DSP_INTC 167
+#define PRST_DSP_PFM_MON 169
+#define SRST_DSP_PFM_MON 170
+#define ARST_DSP_EDAP_NIU 171
+
+#define SRST_PMU 172
+#define SRST_PMU_I2C0 173
+#define PRST_PMU_I2C0 174
+#define PRST_PMU_GPIO0 175
+#define PRST_PMU_INTMEM 176
+#define PRST_PMU_PWM0 177
+#define SRST_PMU_PWM0 178
+#define PRST_PMU_GRF 179
+#define SRST_PMU_NIU 180
+#define SRST_PMU_PVTM 181
+#define ARST_DSP_EDP_PERF 184
+#define ARST_DSP_EPP_PERF 185
+
+#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */
diff --git a/dts/include/dt-bindings/clock/rk3188-cru-common.h b/dts/include/dt-bindings/clock/rk3188-cru-common.h
index 4f53e70f68..d141c1f0c7 100644
--- a/dts/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/dts/include/dt-bindings/clock/rk3188-cru-common.h
@@ -72,6 +72,8 @@
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
+#define ACLK_CPU 203
+#define ACLK_PERI 204
/* pclk gates */
#define PCLK_GRF 320
@@ -104,6 +106,8 @@
#define PCLK_EFUSE 347
#define PCLK_TZPC 348
#define PCLK_TSADC 349
+#define PCLK_CPU 350
+#define PCLK_PERI 351
/* hclk gates */
#define HCLK_SDMMC 448
@@ -126,8 +130,10 @@
#define HCLK_IPP 465
#define HCLK_RGA 466
#define HCLK_NANDC0 467
+#define HCLK_CPU 468
+#define HCLK_PERI 469
-#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
+#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_MCORE 2
diff --git a/dts/include/dt-bindings/clock/stih415-clks.h b/dts/include/dt-bindings/clock/stih415-clks.h
deleted file mode 100644
index d80caa68ae..0000000000
--- a/dts/include/dt-bindings/clock/stih415-clks.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH415 SoC.
- */
-#ifndef _CLK_STIH415
-#define _CLK_STIH415
-
-/* CLOCKGEN A0 */
-#define CLK_ICN_REG 0
-#define CLK_ETH1_PHY 4
-
-/* CLOCKGEN A1 */
-#define CLK_ICN_IF_2 0
-#define CLK_GMAC0_PHY 3
-
-#endif
diff --git a/dts/include/dt-bindings/clock/sun50i-a64-ccu.h b/dts/include/dt-bindings/clock/sun50i-a64-ccu.h
new file mode 100644
index 0000000000..370c0a0473
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_BUS_MIPI_DSI 28
+#define CLK_BUS_CE 29
+#define CLK_BUS_DMA 30
+#define CLK_BUS_MMC0 31
+#define CLK_BUS_MMC1 32
+#define CLK_BUS_MMC2 33
+#define CLK_BUS_NAND 34
+#define CLK_BUS_DRAM 35
+#define CLK_BUS_EMAC 36
+#define CLK_BUS_TS 37
+#define CLK_BUS_HSTIMER 38
+#define CLK_BUS_SPI0 39
+#define CLK_BUS_SPI1 40
+#define CLK_BUS_OTG 41
+#define CLK_BUS_EHCI0 42
+#define CLK_BUS_EHCI1 43
+#define CLK_BUS_OHCI0 44
+#define CLK_BUS_OHCI1 45
+#define CLK_BUS_VE 46
+#define CLK_BUS_TCON0 47
+#define CLK_BUS_TCON1 48
+#define CLK_BUS_DEINTERLACE 49
+#define CLK_BUS_CSI 50
+#define CLK_BUS_HDMI 51
+#define CLK_BUS_DE 52
+#define CLK_BUS_GPU 53
+#define CLK_BUS_MSGBOX 54
+#define CLK_BUS_SPINLOCK 55
+#define CLK_BUS_CODEC 56
+#define CLK_BUS_SPDIF 57
+#define CLK_BUS_PIO 58
+#define CLK_BUS_THS 59
+#define CLK_BUS_I2S0 60
+#define CLK_BUS_I2S1 61
+#define CLK_BUS_I2S2 62
+#define CLK_BUS_I2C0 63
+#define CLK_BUS_I2C1 64
+#define CLK_BUS_I2C2 65
+#define CLK_BUS_SCR 66
+#define CLK_BUS_UART0 67
+#define CLK_BUS_UART1 68
+#define CLK_BUS_UART2 69
+#define CLK_BUS_UART3 70
+#define CLK_BUS_UART4 71
+#define CLK_BUS_DBG 72
+#define CLK_THS 73
+#define CLK_NAND 74
+#define CLK_MMC0 75
+#define CLK_MMC1 76
+#define CLK_MMC2 77
+#define CLK_TS 78
+#define CLK_CE 79
+#define CLK_SPI0 80
+#define CLK_SPI1 81
+#define CLK_I2S0 82
+#define CLK_I2S1 83
+#define CLK_I2S2 84
+#define CLK_SPDIF 85
+#define CLK_USB_PHY0 86
+#define CLK_USB_PHY1 87
+#define CLK_USB_HSIC 88
+#define CLK_USB_HSIC_12M 89
+
+#define CLK_USB_OHCI0 91
+
+#define CLK_USB_OHCI1 93
+
+#define CLK_DRAM_VE 95
+#define CLK_DRAM_CSI 96
+#define CLK_DRAM_DEINTERLACE 97
+#define CLK_DRAM_TS 98
+#define CLK_DE 99
+#define CLK_TCON0 100
+#define CLK_TCON1 101
+#define CLK_DEINTERLACE 102
+#define CLK_CSI_MISC 103
+#define CLK_CSI_SCLK 104
+#define CLK_CSI_MCLK 105
+#define CLK_VE 106
+#define CLK_AC_DIG 107
+#define CLK_AC_DIG_4X 108
+#define CLK_AVS 109
+#define CLK_HDMI 110
+#define CLK_HDMI_DDC 111
+
+#define CLK_DSI_DPHY 113
+#define CLK_GPU 114
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
diff --git a/dts/include/dt-bindings/clock/tegra186-clock.h b/dts/include/dt-bindings/clock/tegra186-clock.h
new file mode 100644
index 0000000000..f73d32098f
--- /dev/null
+++ b/dts/include/dt-bindings/clock/tegra186-clock.h
@@ -0,0 +1,940 @@
+/** @file */
+
+#ifndef _MACH_T186_CLK_T186_H
+#define _MACH_T186_CLK_T186_H
+
+/**
+ * @defgroup clock_ids Clock Identifiers
+ * @{
+ * @defgroup extern_input external input clocks
+ * @{
+ * @def TEGRA186_CLK_OSC
+ * @def TEGRA186_CLK_CLK_32K
+ * @def TEGRA186_CLK_DTV_INPUT
+ * @def TEGRA186_CLK_SOR0_PAD_CLKOUT
+ * @def TEGRA186_CLK_SOR1_PAD_CLKOUT
+ * @def TEGRA186_CLK_I2S1_SYNC_INPUT
+ * @def TEGRA186_CLK_I2S2_SYNC_INPUT
+ * @def TEGRA186_CLK_I2S3_SYNC_INPUT
+ * @def TEGRA186_CLK_I2S4_SYNC_INPUT
+ * @def TEGRA186_CLK_I2S5_SYNC_INPUT
+ * @def TEGRA186_CLK_I2S6_SYNC_INPUT
+ * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
+ * @}
+ *
+ * @defgroup extern_output external output clocks
+ * @{
+ * @def TEGRA186_CLK_EXTPERIPH1
+ * @def TEGRA186_CLK_EXTPERIPH2
+ * @def TEGRA186_CLK_EXTPERIPH3
+ * @def TEGRA186_CLK_EXTPERIPH4
+ * @}
+ *
+ * @defgroup display_clks display related clocks
+ * @{
+ * @def TEGRA186_CLK_CEC
+ * @def TEGRA186_CLK_DSIC
+ * @def TEGRA186_CLK_DSIC_LP
+ * @def TEGRA186_CLK_DSID
+ * @def TEGRA186_CLK_DSID_LP
+ * @def TEGRA186_CLK_DPAUX1
+ * @def TEGRA186_CLK_DPAUX
+ * @def TEGRA186_CLK_HDA2HDMICODEC
+ * @def TEGRA186_CLK_NVDISPLAY_DISP
+ * @def TEGRA186_CLK_NVDISPLAY_DSC
+ * @def TEGRA186_CLK_NVDISPLAY_P0
+ * @def TEGRA186_CLK_NVDISPLAY_P1
+ * @def TEGRA186_CLK_NVDISPLAY_P2
+ * @def TEGRA186_CLK_NVDISPLAYHUB
+ * @def TEGRA186_CLK_SOR_SAFE
+ * @def TEGRA186_CLK_SOR0
+ * @def TEGRA186_CLK_SOR0_OUT
+ * @def TEGRA186_CLK_SOR1
+ * @def TEGRA186_CLK_SOR1_OUT
+ * @def TEGRA186_CLK_DSI
+ * @def TEGRA186_CLK_MIPI_CAL
+ * @def TEGRA186_CLK_DSIA_LP
+ * @def TEGRA186_CLK_DSIB
+ * @def TEGRA186_CLK_DSIB_LP
+ * @}
+ *
+ * @defgroup camera_clks camera related clocks
+ * @{
+ * @def TEGRA186_CLK_NVCSI
+ * @def TEGRA186_CLK_NVCSILP
+ * @def TEGRA186_CLK_VI
+ * @}
+ *
+ * @defgroup audio_clks audio related clocks
+ * @{
+ * @def TEGRA186_CLK_ACLK
+ * @def TEGRA186_CLK_ADSP
+ * @def TEGRA186_CLK_ADSPNEON
+ * @def TEGRA186_CLK_AHUB
+ * @def TEGRA186_CLK_APE
+ * @def TEGRA186_CLK_APB2APE
+ * @def TEGRA186_CLK_AUD_MCLK
+ * @def TEGRA186_CLK_DMIC1
+ * @def TEGRA186_CLK_DMIC2
+ * @def TEGRA186_CLK_DMIC3
+ * @def TEGRA186_CLK_DMIC4
+ * @def TEGRA186_CLK_DSPK1
+ * @def TEGRA186_CLK_DSPK2
+ * @def TEGRA186_CLK_HDA
+ * @def TEGRA186_CLK_HDA2CODEC_2X
+ * @def TEGRA186_CLK_I2S1
+ * @def TEGRA186_CLK_I2S2
+ * @def TEGRA186_CLK_I2S3
+ * @def TEGRA186_CLK_I2S4
+ * @def TEGRA186_CLK_I2S5
+ * @def TEGRA186_CLK_I2S6
+ * @def TEGRA186_CLK_MAUD
+ * @def TEGRA186_CLK_PLL_A_OUT0
+ * @def TEGRA186_CLK_SPDIF_DOUBLER
+ * @def TEGRA186_CLK_SPDIF_IN
+ * @def TEGRA186_CLK_SPDIF_OUT
+ * @def TEGRA186_CLK_SYNC_DMIC1
+ * @def TEGRA186_CLK_SYNC_DMIC2
+ * @def TEGRA186_CLK_SYNC_DMIC3
+ * @def TEGRA186_CLK_SYNC_DMIC4
+ * @def TEGRA186_CLK_SYNC_DMIC5
+ * @def TEGRA186_CLK_SYNC_DSPK1
+ * @def TEGRA186_CLK_SYNC_DSPK2
+ * @def TEGRA186_CLK_SYNC_I2S1
+ * @def TEGRA186_CLK_SYNC_I2S2
+ * @def TEGRA186_CLK_SYNC_I2S3
+ * @def TEGRA186_CLK_SYNC_I2S4
+ * @def TEGRA186_CLK_SYNC_I2S5
+ * @def TEGRA186_CLK_SYNC_I2S6
+ * @def TEGRA186_CLK_SYNC_SPDIF
+ * @}
+ *
+ * @defgroup uart_clks UART clocks
+ * @{
+ * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
+ * @def TEGRA186_CLK_UARTA
+ * @def TEGRA186_CLK_UARTB
+ * @def TEGRA186_CLK_UARTC
+ * @def TEGRA186_CLK_UARTD
+ * @def TEGRA186_CLK_UARTE
+ * @def TEGRA186_CLK_UARTF
+ * @def TEGRA186_CLK_UARTG
+ * @def TEGRA186_CLK_UART_FST_MIPI_CAL
+ * @}
+ *
+ * @defgroup i2c_clks I2C clocks
+ * @{
+ * @def TEGRA186_CLK_AON_I2C_SLOW
+ * @def TEGRA186_CLK_I2C1
+ * @def TEGRA186_CLK_I2C2
+ * @def TEGRA186_CLK_I2C3
+ * @def TEGRA186_CLK_I2C4
+ * @def TEGRA186_CLK_I2C5
+ * @def TEGRA186_CLK_I2C6
+ * @def TEGRA186_CLK_I2C8
+ * @def TEGRA186_CLK_I2C9
+ * @def TEGRA186_CLK_I2C1
+ * @def TEGRA186_CLK_I2C12
+ * @def TEGRA186_CLK_I2C13
+ * @def TEGRA186_CLK_I2C14
+ * @def TEGRA186_CLK_I2C_SLOW
+ * @def TEGRA186_CLK_VI_I2C
+ * @}
+ *
+ * @defgroup spi_clks SPI clocks
+ * @{
+ * @def TEGRA186_CLK_SPI1
+ * @def TEGRA186_CLK_SPI2
+ * @def TEGRA186_CLK_SPI3
+ * @def TEGRA186_CLK_SPI4
+ * @}
+ *
+ * @defgroup storage storage related clocks
+ * @{
+ * @def TEGRA186_CLK_SATA
+ * @def TEGRA186_CLK_SATA_OOB
+ * @def TEGRA186_CLK_SATA_IOBIST
+ * @def TEGRA186_CLK_SDMMC_LEGACY_TM
+ * @def TEGRA186_CLK_SDMMC1
+ * @def TEGRA186_CLK_SDMMC2
+ * @def TEGRA186_CLK_SDMMC3
+ * @def TEGRA186_CLK_SDMMC4
+ * @def TEGRA186_CLK_QSPI
+ * @def TEGRA186_CLK_QSPI_OUT
+ * @def TEGRA186_CLK_UFSDEV_REF
+ * @def TEGRA186_CLK_UFSHC
+ * @}
+ *
+ * @defgroup pwm_clks PWM clocks
+ * @{
+ * @def TEGRA186_CLK_PWM1
+ * @def TEGRA186_CLK_PWM2
+ * @def TEGRA186_CLK_PWM3
+ * @def TEGRA186_CLK_PWM4
+ * @def TEGRA186_CLK_PWM5
+ * @def TEGRA186_CLK_PWM6
+ * @def TEGRA186_CLK_PWM7
+ * @def TEGRA186_CLK_PWM8
+ * @}
+ *
+ * @defgroup plls PLLs and related clocks
+ * @{
+ * @def TEGRA186_CLK_PLLREFE_OUT_GATED
+ * @def TEGRA186_CLK_PLLREFE_OUT1
+ * @def TEGRA186_CLK_PLLD_OUT1
+ * @def TEGRA186_CLK_PLLP_OUT0
+ * @def TEGRA186_CLK_PLLP_OUT5
+ * @def TEGRA186_CLK_PLLA
+ * @def TEGRA186_CLK_PLLE_PWRSEQ
+ * @def TEGRA186_CLK_PLLA_OUT1
+ * @def TEGRA186_CLK_PLLREFE_REF
+ * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
+ * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
+ * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
+ * @def TEGRA186_CLK_PLLREFE_PEX
+ * @def TEGRA186_CLK_PLLREFE_IDDQ
+ * @def TEGRA186_CLK_PLLC_OUT_AON
+ * @def TEGRA186_CLK_PLLC_OUT_ISP
+ * @def TEGRA186_CLK_PLLC_OUT_VE
+ * @def TEGRA186_CLK_PLLC4_OUT
+ * @def TEGRA186_CLK_PLLREFE_OUT
+ * @def TEGRA186_CLK_PLLREFE_PLL_REF
+ * @def TEGRA186_CLK_PLLE
+ * @def TEGRA186_CLK_PLLC
+ * @def TEGRA186_CLK_PLLP
+ * @def TEGRA186_CLK_PLLD
+ * @def TEGRA186_CLK_PLLD2
+ * @def TEGRA186_CLK_PLLREFE_VCO
+ * @def TEGRA186_CLK_PLLC2
+ * @def TEGRA186_CLK_PLLC3
+ * @def TEGRA186_CLK_PLLDP
+ * @def TEGRA186_CLK_PLLC4_VCO
+ * @def TEGRA186_CLK_PLLA1
+ * @def TEGRA186_CLK_PLLNVCSI
+ * @def TEGRA186_CLK_PLLDISPHUB
+ * @def TEGRA186_CLK_PLLD3
+ * @def TEGRA186_CLK_PLLBPMPCAM
+ * @def TEGRA186_CLK_PLLAON
+ * @def TEGRA186_CLK_PLLU
+ * @def TEGRA186_CLK_PLLC4_VCO_DIV2
+ * @def TEGRA186_CLK_PLL_REF
+ * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
+ * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
+ * @def TEGRA186_CLK_PLL_U_48M
+ * @def TEGRA186_CLK_PLL_U_480M
+ * @def TEGRA186_CLK_PLLC4_OUT0
+ * @def TEGRA186_CLK_PLLC4_OUT1
+ * @def TEGRA186_CLK_PLLC4_OUT2
+ * @def TEGRA186_CLK_PLLC4_OUT_MUX
+ * @def TEGRA186_CLK_DFLLDISP_DIV
+ * @def TEGRA186_CLK_PLLDISPHUB_DIV
+ * @def TEGRA186_CLK_PLLP_DIV8
+ * @}
+ *
+ * @defgroup nafll_clks NAFLL clock sources
+ * @{
+ * @def TEGRA186_CLK_NAFLL_AXI_CBB
+ * @def TEGRA186_CLK_NAFLL_BCPU
+ * @def TEGRA186_CLK_NAFLL_BPMP
+ * @def TEGRA186_CLK_NAFLL_DISP
+ * @def TEGRA186_CLK_NAFLL_GPU
+ * @def TEGRA186_CLK_NAFLL_ISP
+ * @def TEGRA186_CLK_NAFLL_MCPU
+ * @def TEGRA186_CLK_NAFLL_NVDEC
+ * @def TEGRA186_CLK_NAFLL_NVENC
+ * @def TEGRA186_CLK_NAFLL_NVJPG
+ * @def TEGRA186_CLK_NAFLL_SCE
+ * @def TEGRA186_CLK_NAFLL_SE
+ * @def TEGRA186_CLK_NAFLL_TSEC
+ * @def TEGRA186_CLK_NAFLL_TSECB
+ * @def TEGRA186_CLK_NAFLL_VI
+ * @def TEGRA186_CLK_NAFLL_VIC
+ * @}
+ *
+ * @defgroup mphy MPHY related clocks
+ * @{
+ * @def TEGRA186_CLK_MPHY_L0_RX_SYMB
+ * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
+ * @def TEGRA186_CLK_MPHY_L0_TX_SYMB
+ * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
+ * @def TEGRA186_CLK_MPHY_L0_RX_ANA
+ * @def TEGRA186_CLK_MPHY_L1_RX_ANA
+ * @def TEGRA186_CLK_MPHY_IOBIST
+ * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
+ * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
+ * @}
+ *
+ * @defgroup eavb EAVB related clocks
+ * @{
+ * @def TEGRA186_CLK_EQOS_AXI
+ * @def TEGRA186_CLK_EQOS_PTP_REF
+ * @def TEGRA186_CLK_EQOS_RX
+ * @def TEGRA186_CLK_EQOS_RX_INPUT
+ * @def TEGRA186_CLK_EQOS_TX
+ * @}
+ *
+ * @defgroup usb USB related clocks
+ * @{
+ * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
+ * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
+ * @def TEGRA186_CLK_HSIC_TRK
+ * @def TEGRA186_CLK_USB2_TRK
+ * @def TEGRA186_CLK_USB2_HSIC_TRK
+ * @def TEGRA186_CLK_XUSB_CORE_SS
+ * @def TEGRA186_CLK_XUSB_CORE_DEV
+ * @def TEGRA186_CLK_XUSB_FALCON
+ * @def TEGRA186_CLK_XUSB_FS
+ * @def TEGRA186_CLK_XUSB
+ * @def TEGRA186_CLK_XUSB_DEV
+ * @def TEGRA186_CLK_XUSB_HOST
+ * @def TEGRA186_CLK_XUSB_SS
+ * @}
+ *
+ * @defgroup bigblock compute block related clocks
+ * @{
+ * @def TEGRA186_CLK_GPCCLK
+ * @def TEGRA186_CLK_GPC2CLK
+ * @def TEGRA186_CLK_GPU
+ * @def TEGRA186_CLK_HOST1X
+ * @def TEGRA186_CLK_ISP
+ * @def TEGRA186_CLK_NVDEC
+ * @def TEGRA186_CLK_NVENC
+ * @def TEGRA186_CLK_NVJPG
+ * @def TEGRA186_CLK_SE
+ * @def TEGRA186_CLK_TSEC
+ * @def TEGRA186_CLK_TSECB
+ * @def TEGRA186_CLK_VIC
+ * @}
+ *
+ * @defgroup can CAN bus related clocks
+ * @{
+ * @def TEGRA186_CLK_CAN1
+ * @def TEGRA186_CLK_CAN1_HOST
+ * @def TEGRA186_CLK_CAN2
+ * @def TEGRA186_CLK_CAN2_HOST
+ * @}
+ *
+ * @defgroup system basic system clocks
+ * @{
+ * @def TEGRA186_CLK_ACTMON
+ * @def TEGRA186_CLK_AON_APB
+ * @def TEGRA186_CLK_AON_CPU_NIC
+ * @def TEGRA186_CLK_AON_NIC
+ * @def TEGRA186_CLK_AXI_CBB
+ * @def TEGRA186_CLK_BPMP_APB
+ * @def TEGRA186_CLK_BPMP_CPU_NIC
+ * @def TEGRA186_CLK_BPMP_NIC_RATE
+ * @def TEGRA186_CLK_CLK_M
+ * @def TEGRA186_CLK_EMC
+ * @def TEGRA186_CLK_MSS_ENCRYPT
+ * @def TEGRA186_CLK_SCE_APB
+ * @def TEGRA186_CLK_SCE_CPU_NIC
+ * @def TEGRA186_CLK_SCE_NIC
+ * @def TEGRA186_CLK_TSC
+ * @}
+ *
+ * @defgroup pcie_clks PCIe related clocks
+ * @{
+ * @def TEGRA186_CLK_AFI
+ * @def TEGRA186_CLK_PCIE
+ * @def TEGRA186_CLK_PCIE2_IOBIST
+ * @def TEGRA186_CLK_PCIERX0
+ * @def TEGRA186_CLK_PCIERX1
+ * @def TEGRA186_CLK_PCIERX2
+ * @def TEGRA186_CLK_PCIERX3
+ * @def TEGRA186_CLK_PCIERX4
+ * @}
+ */
+
+/** @brief output of gate CLK_ENB_FUSE */
+#define TEGRA186_CLK_FUSE 0
+/**
+ * @brief It's not what you think
+ * @details output of gate CLK_ENB_GPU. This output connects to the GPU
+ * pwrclk. @warning: This is almost certainly not the clock you think
+ * it is. If you're looking for the clock of the graphics engine, see
+ * TEGRA186_GPCCLK
+ */
+#define TEGRA186_CLK_GPU 1
+/** @brief output of gate CLK_ENB_PCIE */
+#define TEGRA186_CLK_PCIE 3
+/** @brief output of the divider IPFS_CLK_DIVISOR */
+#define TEGRA186_CLK_AFI 4
+/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
+#define TEGRA186_CLK_PCIE2_IOBIST 5
+/** @brief output of gate CLK_ENB_PCIERX0*/
+#define TEGRA186_CLK_PCIERX0 6
+/** @brief output of gate CLK_ENB_PCIERX1*/
+#define TEGRA186_CLK_PCIERX1 7
+/** @brief output of gate CLK_ENB_PCIERX2*/
+#define TEGRA186_CLK_PCIERX2 8
+/** @brief output of gate CLK_ENB_PCIERX3*/
+#define TEGRA186_CLK_PCIERX3 9
+/** @brief output of gate CLK_ENB_PCIERX4*/
+#define TEGRA186_CLK_PCIERX4 10
+/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
+#define TEGRA186_CLK_PLLC_OUT_ISP 11
+/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
+#define TEGRA186_CLK_PLLC_OUT_VE 12
+/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
+#define TEGRA186_CLK_PLLC_OUT_AON 13
+/** @brief output of gate CLK_ENB_SOR_SAFE */
+#define TEGRA186_CLK_SOR_SAFE 39
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
+#define TEGRA186_CLK_I2S2 42
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
+#define TEGRA186_CLK_I2S3 43
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
+#define TEGRA186_CLK_SPDIF_IN 44
+/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
+#define TEGRA186_CLK_SPDIF_DOUBLER 45
+/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
+#define TEGRA186_CLK_SPI3 46
+/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
+#define TEGRA186_CLK_I2C1 47
+/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
+#define TEGRA186_CLK_I2C5 48
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
+#define TEGRA186_CLK_SPI1 49
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
+#define TEGRA186_CLK_ISP 50
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
+#define TEGRA186_CLK_VI 51
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
+#define TEGRA186_CLK_SDMMC1 52
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
+#define TEGRA186_CLK_SDMMC2 53
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
+#define TEGRA186_CLK_SDMMC4 54
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
+#define TEGRA186_CLK_UARTA 55
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
+#define TEGRA186_CLK_UARTB 56
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
+#define TEGRA186_CLK_HOST1X 57
+/**
+ * @brief controls the EMC clock frequency.
+ * @details Doing a clk_set_rate on this clock will select the
+ * appropriate clock source, program the source rate and execute a
+ * specific sequence to switch to the new clock source for both memory
+ * controllers. This can be used to control the balance between memory
+ * throughput and memory controller power.
+ */
+#define TEGRA186_CLK_EMC 58
+/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
+#define TEGRA186_CLK_EXTPERIPH4 73
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
+#define TEGRA186_CLK_SPI4 74
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA186_CLK_I2C3 75
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
+#define TEGRA186_CLK_SDMMC3 76
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
+#define TEGRA186_CLK_UARTD 77
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
+#define TEGRA186_CLK_I2S1 79
+/** output of gate CLK_ENB_DTV */
+#define TEGRA186_CLK_DTV 80
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
+#define TEGRA186_CLK_TSEC 81
+/** @brief output of gate CLK_ENB_DP2 */
+#define TEGRA186_CLK_DP2 82
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
+#define TEGRA186_CLK_I2S4 84
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
+#define TEGRA186_CLK_I2S5 85
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA186_CLK_I2C4 86
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
+#define TEGRA186_CLK_AHUB 87
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
+#define TEGRA186_CLK_HDA2CODEC_2X 88
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
+#define TEGRA186_CLK_EXTPERIPH1 89
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
+#define TEGRA186_CLK_EXTPERIPH2 90
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
+#define TEGRA186_CLK_EXTPERIPH3 91
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
+#define TEGRA186_CLK_I2C_SLOW 92
+/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
+#define TEGRA186_CLK_SOR1 93
+/** @brief output of gate CLK_ENB_CEC */
+#define TEGRA186_CLK_CEC 94
+/** @brief output of gate CLK_ENB_DPAUX1 */
+#define TEGRA186_CLK_DPAUX1 95
+/** @brief output of gate CLK_ENB_DPAUX */
+#define TEGRA186_CLK_DPAUX 96
+/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
+#define TEGRA186_CLK_SOR0 97
+/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
+#define TEGRA186_CLK_HDA2HDMICODEC 98
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
+#define TEGRA186_CLK_SATA 99
+/** @brief output of gate CLK_ENB_SATA_OOB */
+#define TEGRA186_CLK_SATA_OOB 100
+/** @brief output of gate CLK_ENB_SATA_IOBIST */
+#define TEGRA186_CLK_SATA_IOBIST 101
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
+#define TEGRA186_CLK_HDA 102
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
+#define TEGRA186_CLK_SE 103
+/** @brief output of gate CLK_ENB_APB2APE */
+#define TEGRA186_CLK_APB2APE 104
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
+#define TEGRA186_CLK_APE 105
+/** @brief output of gate CLK_ENB_IQC1 */
+#define TEGRA186_CLK_IQC1 106
+/** @brief output of gate CLK_ENB_IQC2 */
+#define TEGRA186_CLK_IQC2 107
+/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
+#define TEGRA186_CLK_PLLREFE_OUT 108
+/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
+#define TEGRA186_CLK_PLLREFE_PLL_REF 109
+/** @brief output of gate CLK_ENB_PLLC4_OUT */
+#define TEGRA186_CLK_PLLC4_OUT 110
+/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB 111
+/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_DEV 112
+/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_HOST 113
+/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_SS 114
+/** @brief output of gate CLK_ENB_DSI */
+#define TEGRA186_CLK_DSI 115
+/** @brief output of gate CLK_ENB_MIPI_CAL */
+#define TEGRA186_CLK_MIPI_CAL 116
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
+#define TEGRA186_CLK_DSIA_LP 117
+/** @brief output of gate CLK_ENB_DSIB */
+#define TEGRA186_CLK_DSIB 118
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
+#define TEGRA186_CLK_DSIB_LP 119
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
+#define TEGRA186_CLK_DMIC1 122
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
+#define TEGRA186_CLK_DMIC2 123
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
+#define TEGRA186_CLK_AUD_MCLK 124
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA186_CLK_I2C6 125
+/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
+#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
+#define TEGRA186_CLK_VIC 127
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
+#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
+#define TEGRA186_CLK_NVDEC 129
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
+#define TEGRA186_CLK_NVJPG 130
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
+#define TEGRA186_CLK_NVENC 131
+/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
+#define TEGRA186_CLK_QSPI 132
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
+#define TEGRA186_CLK_VI_I2C 133
+/** @brief output of gate CLK_ENB_HSIC_TRK */
+#define TEGRA186_CLK_HSIC_TRK 134
+/** @brief output of gate CLK_ENB_USB2_TRK */
+#define TEGRA186_CLK_USB2_TRK 135
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
+#define TEGRA186_CLK_MAUD 136
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
+#define TEGRA186_CLK_TSECB 137
+/** @brief output of gate CLK_ENB_ADSP */
+#define TEGRA186_CLK_ADSP 138
+/** @brief output of gate CLK_ENB_ADSPNEON */
+#define TEGRA186_CLK_ADSPNEON 139
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
+#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
+/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
+#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
+#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
+/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
+#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
+/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
+#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
+/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
+#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
+#define TEGRA186_CLK_MPHY_IOBIST 146
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
+#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
+#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
+#define TEGRA186_CLK_AXI_CBB 149
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
+#define TEGRA186_CLK_DMIC3 150
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
+#define TEGRA186_CLK_DMIC4 151
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
+#define TEGRA186_CLK_DSPK1 152
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
+#define TEGRA186_CLK_DSPK2 153
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA186_CLK_I2S6 154
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
+#define TEGRA186_CLK_NVDISPLAY_P0 155
+/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
+#define TEGRA186_CLK_NVDISPLAY_DISP 156
+/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
+#define TEGRA186_CLK_NVDISPLAY_DSC 157
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
+#define TEGRA186_CLK_NVDISPLAYHUB 158
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
+#define TEGRA186_CLK_NVDISPLAY_P1 159
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
+#define TEGRA186_CLK_NVDISPLAY_P2 160
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
+#define TEGRA186_CLK_TACH 166
+/** @brief output of gate CLK_ENB_EQOS */
+#define TEGRA186_CLK_EQOS_AXI 167
+/** @brief output of gate CLK_ENB_EQOS_RX */
+#define TEGRA186_CLK_EQOS_RX 168
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
+#define TEGRA186_CLK_UFSHC 178
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
+#define TEGRA186_CLK_UFSDEV_REF 179
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
+#define TEGRA186_CLK_NVCSI 180
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
+#define TEGRA186_CLK_NVCSILP 181
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA186_CLK_I2C7 182
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA186_CLK_I2C9 183
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
+#define TEGRA186_CLK_I2C12 184
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
+#define TEGRA186_CLK_I2C13 185
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
+#define TEGRA186_CLK_I2C14 186
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA186_CLK_PWM1 187
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA186_CLK_PWM2 188
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA186_CLK_PWM3 189
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA186_CLK_PWM5 190
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA186_CLK_PWM6 191
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA186_CLK_PWM7 192
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA186_CLK_PWM8 193
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
+#define TEGRA186_CLK_UARTE 194
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
+#define TEGRA186_CLK_UARTF 195
+/** @deprecated */
+#define TEGRA186_CLK_DBGAPB 196
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
+#define TEGRA186_CLK_BPMP_CPU_NIC 197
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
+#define TEGRA186_CLK_BPMP_APB 199
+/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
+#define TEGRA186_CLK_ACTMON 201
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
+#define TEGRA186_CLK_AON_CPU_NIC 208
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
+#define TEGRA186_CLK_CAN1 210
+/** @brief output of gate CLK_ENB_CAN1_HOST */
+#define TEGRA186_CLK_CAN1_HOST 211
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
+#define TEGRA186_CLK_CAN2 212
+/** @brief output of gate CLK_ENB_CAN2_HOST */
+#define TEGRA186_CLK_CAN2_HOST 213
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
+#define TEGRA186_CLK_AON_APB 214
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
+#define TEGRA186_CLK_UARTC 215
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
+#define TEGRA186_CLK_UARTG 216
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
+#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA186_CLK_I2C2 218
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA186_CLK_I2C8 219
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
+#define TEGRA186_CLK_I2C10 220
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
+#define TEGRA186_CLK_AON_I2C_SLOW 221
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
+#define TEGRA186_CLK_SPI2 222
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
+#define TEGRA186_CLK_DMIC5 223
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
+#define TEGRA186_CLK_AON_TOUCH 224
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA186_CLK_PWM4 225
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
+#define TEGRA186_CLK_TSC 226
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
+#define TEGRA186_CLK_MSS_ENCRYPT 227
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
+#define TEGRA186_CLK_SCE_CPU_NIC 228
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
+#define TEGRA186_CLK_SCE_APB 230
+/** @brief output of gate CLK_ENB_DSIC */
+#define TEGRA186_CLK_DSIC 231
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
+#define TEGRA186_CLK_DSIC_LP 232
+/** @brief output of gate CLK_ENB_DSID */
+#define TEGRA186_CLK_DSID 233
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
+#define TEGRA186_CLK_DSID_LP 234
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
+#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
+#define TEGRA186_CLK_SPDIF_OUT 238
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
+#define TEGRA186_CLK_EQOS_PTP_REF 239
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
+#define TEGRA186_CLK_EQOS_TX 240
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
+#define TEGRA186_CLK_USB2_HSIC_TRK 241
+/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_CORE_SS 242
+/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_CORE_DEV 243
+/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_FALCON 244
+/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_FS 245
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
+#define TEGRA186_CLK_PLL_A_OUT0 246
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
+#define TEGRA186_CLK_SYNC_I2S1 247
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
+#define TEGRA186_CLK_SYNC_I2S2 248
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
+#define TEGRA186_CLK_SYNC_I2S3 249
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
+#define TEGRA186_CLK_SYNC_I2S4 250
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
+#define TEGRA186_CLK_SYNC_I2S5 251
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
+#define TEGRA186_CLK_SYNC_I2S6 252
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
+#define TEGRA186_CLK_SYNC_DSPK1 253
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
+#define TEGRA186_CLK_SYNC_DSPK2 254
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
+#define TEGRA186_CLK_SYNC_DMIC1 255
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
+#define TEGRA186_CLK_SYNC_DMIC2 256
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
+#define TEGRA186_CLK_SYNC_DMIC3 257
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
+#define TEGRA186_CLK_SYNC_DMIC4 259
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
+#define TEGRA186_CLK_SYNC_SPDIF 260
+/** @brief output of gate CLK_ENB_PLLREFE_OUT */
+#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
+/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
+ * * VCO/pdiv defined by this clock object
+ * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
+ */
+#define TEGRA186_CLK_PLLREFE_OUT1 262
+#define TEGRA186_CLK_PLLD_OUT1 267
+/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
+#define TEGRA186_CLK_PLLP_OUT0 269
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
+#define TEGRA186_CLK_PLLP_OUT5 270
+/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
+#define TEGRA186_CLK_PLLA 271
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
+#define TEGRA186_CLK_ACLK 273
+/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLL_U_48M 274
+/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLL_U_480M 275
+/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
+#define TEGRA186_CLK_PLLC4_OUT0 276
+/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
+#define TEGRA186_CLK_PLLC4_OUT1 277
+/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
+#define TEGRA186_CLK_PLLC4_OUT2 278
+/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
+#define TEGRA186_CLK_PLLC4_OUT_MUX 279
+/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
+#define TEGRA186_CLK_DFLLDISP_DIV 284
+/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
+#define TEGRA186_CLK_PLLDISPHUB_DIV 285
+/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
+#define TEGRA186_CLK_PLLP_DIV8 286
+/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
+#define TEGRA186_CLK_BPMP_NIC 287
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
+#define TEGRA186_CLK_PLL_A_OUT1 288
+/** @deprecated */
+#define TEGRA186_CLK_GPC2CLK 289
+/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
+#define TEGRA186_CLK_KFUSE 293
+/**
+ * @brief controls the PLLE hardware sequencer.
+ * @details This clock only has enable and disable methods. When the
+ * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
+ * hw based on the control signals from the PCIe, SATA and XUSB
+ * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
+ * is controlled by sw using clk_enable/clk_disable on
+ * TEGRA186_CLK_PLLE.
+ */
+#define TEGRA186_CLK_PLLE_PWRSEQ 294
+/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLLREFE_REF 295
+/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
+#define TEGRA186_CLK_SOR0_OUT 296
+/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
+#define TEGRA186_CLK_SOR1_OUT 297
+/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
+#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
+/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
+#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
+#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
+#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
+/** @brief controls the UPHY_PLL0 hardware sqeuencer */
+#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
+/** @brief controls the UPHY_PLL1 hardware sqeuencer */
+#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
+/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
+#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
+/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
+#define TEGRA186_CLK_PLLREFE_PEX 307
+/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
+#define TEGRA186_CLK_PLLREFE_IDDQ 308
+/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
+#define TEGRA186_CLK_QSPI_OUT 309
+/**
+ * @brief GPC2CLK-div-2
+ * @details fixed /2 divider. Output frequency is
+ * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
+ * frequency at which the GPU graphics engine runs. */
+#define TEGRA186_CLK_GPCCLK 310
+/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
+#define TEGRA186_CLK_AON_NIC 450
+/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
+#define TEGRA186_CLK_SCE_NIC 451
+/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
+#define TEGRA186_CLK_PLLE 512
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
+#define TEGRA186_CLK_PLLC 513
+/** Fixed 408MHz PLL for use by peripheral clocks */
+#define TEGRA186_CLK_PLLP 516
+/** @deprecated */
+#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
+#define TEGRA186_CLK_PLLD 518
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
+#define TEGRA186_CLK_PLLD2 519
+/**
+ * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
+ * @details Note that this clock only controls the VCO output, before
+ * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
+ * information.
+ */
+#define TEGRA186_CLK_PLLREFE_VCO 520
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
+#define TEGRA186_CLK_PLLC2 521
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
+#define TEGRA186_CLK_PLLC3 522
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
+#define TEGRA186_CLK_PLLDP 523
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
+#define TEGRA186_CLK_PLLC4_VCO 524
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
+#define TEGRA186_CLK_PLLA1 525
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
+#define TEGRA186_CLK_PLLNVCSI 526
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
+#define TEGRA186_CLK_PLLDISPHUB 527
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
+#define TEGRA186_CLK_PLLD3 528
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
+#define TEGRA186_CLK_PLLBPMPCAM 531
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
+#define TEGRA186_CLK_PLLAON 532
+/** Fixed frequency 960MHz PLL for USB and EAVB */
+#define TEGRA186_CLK_PLLU 533
+/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
+#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
+/** @brief NAFLL clock source for AXI_CBB */
+#define TEGRA186_CLK_NAFLL_AXI_CBB 564
+/** @brief NAFLL clock source for BPMP */
+#define TEGRA186_CLK_NAFLL_BPMP 565
+/** @brief NAFLL clock source for ISP */
+#define TEGRA186_CLK_NAFLL_ISP 566
+/** @brief NAFLL clock source for NVDEC */
+#define TEGRA186_CLK_NAFLL_NVDEC 567
+/** @brief NAFLL clock source for NVENC */
+#define TEGRA186_CLK_NAFLL_NVENC 568
+/** @brief NAFLL clock source for NVJPG */
+#define TEGRA186_CLK_NAFLL_NVJPG 569
+/** @brief NAFLL clock source for SCE */
+#define TEGRA186_CLK_NAFLL_SCE 570
+/** @brief NAFLL clock source for SE */
+#define TEGRA186_CLK_NAFLL_SE 571
+/** @brief NAFLL clock source for TSEC */
+#define TEGRA186_CLK_NAFLL_TSEC 572
+/** @brief NAFLL clock source for TSECB */
+#define TEGRA186_CLK_NAFLL_TSECB 573
+/** @brief NAFLL clock source for VI */
+#define TEGRA186_CLK_NAFLL_VI 574
+/** @brief NAFLL clock source for VIC */
+#define TEGRA186_CLK_NAFLL_VIC 575
+/** @brief NAFLL clock source for DISP */
+#define TEGRA186_CLK_NAFLL_DISP 576
+/** @brief NAFLL clock source for GPU */
+#define TEGRA186_CLK_NAFLL_GPU 577
+/** @brief NAFLL clock source for M-CPU cluster */
+#define TEGRA186_CLK_NAFLL_MCPU 578
+/** @brief NAFLL clock source for B-CPU cluster */
+#define TEGRA186_CLK_NAFLL_BCPU 579
+/** @brief input from Tegra's CLK_32K_IN pad */
+#define TEGRA186_CLK_CLK_32K 608
+/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
+#define TEGRA186_CLK_CLK_M 609
+/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
+#define TEGRA186_CLK_PLL_REF 610
+/** @brief input from Tegra's XTAL_IN */
+#define TEGRA186_CLK_OSC 612
+/** @brief clock recovered from EAVB input */
+#define TEGRA186_CLK_EQOS_RX_INPUT 613
+/** @brief clock recovered from DTV input */
+#define TEGRA186_CLK_DTV_INPUT 614
+/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
+#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
+/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
+#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
+/** @brief clock recovered from I2S1 input */
+#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
+/** @brief clock recovered from I2S2 input */
+#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
+/** @brief clock recovered from I2S3 input */
+#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
+/** @brief clock recovered from I2S4 input */
+#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
+/** @brief clock recovered from I2S5 input */
+#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
+/** @brief clock recovered from I2S6 input */
+#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
+/** @brief clock recovered from SPDIFIN input */
+#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
+
+/**
+ * @brief subject to change
+ * @details maximum clock identifier value plus one.
+ */
+#define TEGRA186_CLK_CLK_MAX 624
+
+/** @} */
+
+#endif
diff --git a/dts/include/dt-bindings/gpio/meson-gxl-gpio.h b/dts/include/dt-bindings/gpio/meson-gxl-gpio.h
new file mode 100644
index 0000000000..684d0d7add
--- /dev/null
+++ b/dts/include/dt-bindings/gpio/meson-gxl-gpio.h
@@ -0,0 +1,131 @@
+/*
+ * GPIO definitions for Amlogic Meson GXL SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
+#define _DT_BINDINGS_MESON_GXL_GPIO_H
+
+#define GPIOAO_0 0
+#define GPIOAO_1 1
+#define GPIOAO_2 2
+#define GPIOAO_3 3
+#define GPIOAO_4 4
+#define GPIOAO_5 5
+#define GPIOAO_6 6
+#define GPIOAO_7 7
+#define GPIOAO_8 8
+#define GPIOAO_9 9
+
+#define GPIOZ_0 0
+#define GPIOZ_1 1
+#define GPIOZ_2 2
+#define GPIOZ_3 3
+#define GPIOZ_4 4
+#define GPIOZ_5 5
+#define GPIOZ_6 6
+#define GPIOZ_7 7
+#define GPIOZ_8 8
+#define GPIOZ_9 9
+#define GPIOZ_10 10
+#define GPIOZ_11 11
+#define GPIOZ_12 12
+#define GPIOZ_13 13
+#define GPIOZ_14 14
+#define GPIOZ_15 15
+#define GPIOH_0 16
+#define GPIOH_1 17
+#define GPIOH_2 18
+#define GPIOH_3 19
+#define GPIOH_4 20
+#define GPIOH_5 21
+#define GPIOH_6 22
+#define GPIOH_7 23
+#define GPIOH_8 24
+#define GPIOH_9 25
+#define BOOT_0 26
+#define BOOT_1 27
+#define BOOT_2 28
+#define BOOT_3 29
+#define BOOT_4 30
+#define BOOT_5 31
+#define BOOT_6 32
+#define BOOT_7 33
+#define BOOT_8 34
+#define BOOT_9 35
+#define BOOT_10 36
+#define BOOT_11 37
+#define BOOT_12 38
+#define BOOT_13 39
+#define BOOT_14 40
+#define BOOT_15 41
+#define CARD_0 42
+#define CARD_1 43
+#define CARD_2 44
+#define CARD_3 45
+#define CARD_4 46
+#define CARD_5 47
+#define CARD_6 48
+#define GPIODV_0 49
+#define GPIODV_1 50
+#define GPIODV_2 51
+#define GPIODV_3 52
+#define GPIODV_4 53
+#define GPIODV_5 54
+#define GPIODV_6 55
+#define GPIODV_7 56
+#define GPIODV_8 57
+#define GPIODV_9 58
+#define GPIODV_10 59
+#define GPIODV_11 60
+#define GPIODV_12 61
+#define GPIODV_13 62
+#define GPIODV_14 63
+#define GPIODV_15 64
+#define GPIODV_16 65
+#define GPIODV_17 66
+#define GPIODV_18 67
+#define GPIODV_19 68
+#define GPIODV_20 69
+#define GPIODV_21 70
+#define GPIODV_22 71
+#define GPIODV_23 72
+#define GPIODV_24 73
+#define GPIODV_25 74
+#define GPIODV_26 75
+#define GPIODV_27 76
+#define GPIODV_28 77
+#define GPIODV_29 78
+#define GPIOX_0 79
+#define GPIOX_1 80
+#define GPIOX_2 81
+#define GPIOX_3 82
+#define GPIOX_4 83
+#define GPIOX_5 84
+#define GPIOX_6 85
+#define GPIOX_7 86
+#define GPIOX_8 87
+#define GPIOX_9 88
+#define GPIOX_10 89
+#define GPIOX_11 90
+#define GPIOX_12 91
+#define GPIOX_13 92
+#define GPIOX_14 93
+#define GPIOX_15 94
+#define GPIOX_16 95
+#define GPIOX_17 96
+#define GPIOX_18 97
+#define GPIOCLK_0 98
+#define GPIOCLK_1 99
+#define GPIO_TEST_N 100
+
+#endif
diff --git a/dts/include/dt-bindings/mailbox/tegra186-hsp.h b/dts/include/dt-bindings/mailbox/tegra186-hsp.h
new file mode 100644
index 0000000000..f5d66e5f5f
--- /dev/null
+++ b/dts/include/dt-bindings/mailbox/tegra186-hsp.h
@@ -0,0 +1,24 @@
+/*
+ * This header provides constants for binding nvidia,tegra186-hsp.
+ */
+
+#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
+#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
+
+/*
+ * These define the type of mailbox that is to be used (doorbell, shared
+ * mailbox, shared semaphore or arbitrated semaphore).
+ */
+#define TEGRA_HSP_MBOX_TYPE_DB 0x0
+#define TEGRA_HSP_MBOX_TYPE_SM 0x1
+#define TEGRA_HSP_MBOX_TYPE_SS 0x2
+#define TEGRA_HSP_MBOX_TYPE_AS 0x3
+
+/*
+ * These defines represent the bit associated with the given master ID in the
+ * doorbell registers.
+ */
+#define TEGRA_HSP_DB_MASTER_CCPLEX 17
+#define TEGRA_HSP_DB_MASTER_BPMP 19
+
+#endif
diff --git a/dts/include/dt-bindings/mfd/tps65217.h b/dts/include/dt-bindings/mfd/tps65217.h
new file mode 100644
index 0000000000..cafb9e60cf
--- /dev/null
+++ b/dts/include/dt-bindings/mfd/tps65217.h
@@ -0,0 +1,26 @@
+/*
+ * This header provides macros for TI TPS65217 DT bindings.
+ *
+ * Copyright (C) 2016 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DT_BINDINGS_TPS65217_H__
+#define __DT_BINDINGS_TPS65217_H__
+
+#define TPS65217_IRQ_USB 0
+#define TPS65217_IRQ_AC 1
+#define TPS65217_IRQ_PB 2
+
+#endif
diff --git a/dts/include/dt-bindings/net/mscc-phy-vsc8531.h b/dts/include/dt-bindings/net/mscc-phy-vsc8531.h
deleted file mode 100644
index 2383dd20ff..0000000000
--- a/dts/include/dt-bindings/net/mscc-phy-vsc8531.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Device Tree constants for Microsemi VSC8531 PHY
- *
- * Author: Nagaraju Lakkaraju
- *
- * License: Dual MIT/GPL
- * Copyright (c) 2016 Microsemi Corporation
- */
-
-#ifndef _DT_BINDINGS_MSCC_VSC8531_H
-#define _DT_BINDINGS_MSCC_VSC8531_H
-
-/* MAC interface Edge rate control VDDMAC in milli Volts */
-#define MSCC_VDDMAC_3300 3300
-#define MSCC_VDDMAC_2500 2500
-#define MSCC_VDDMAC_1800 1800
-#define MSCC_VDDMAC_1500 1500
-#define MSCC_VDDMAC_MAX 4
-#define MSCC_SLOWDOWN_MAX 8
-
-#endif
diff --git a/dts/include/dt-bindings/pinctrl/at91.h b/dts/include/dt-bindings/pinctrl/at91.h
index bbca3d0389..2732d6c0fb 100644
--- a/dts/include/dt-bindings/pinctrl/at91.h
+++ b/dts/include/dt-bindings/pinctrl/at91.h
@@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH (1 << 2)
#define AT91_PINCTRL_PULL_DOWN (1 << 3)
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
+#define AT91_PINCTRL_OUTPUT (1 << 7)
+#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
diff --git a/dts/include/dt-bindings/pinctrl/bcm2835.h b/dts/include/dt-bindings/pinctrl/bcm2835.h
index 6f0bc37af3..e4e4fdf5d3 100644
--- a/dts/include/dt-bindings/pinctrl/bcm2835.h
+++ b/dts/include/dt-bindings/pinctrl/bcm2835.h
@@ -24,4 +24,9 @@
#define BCM2835_FSEL_ALT2 6
#define BCM2835_FSEL_ALT3 7
+/* brcm,pull property */
+#define BCM2835_PUD_OFF 0
+#define BCM2835_PUD_DOWN 1
+#define BCM2835_PUD_UP 2
+
#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */
diff --git a/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
index aafa76cb56..d33f17c8a5 100644
--- a/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
+++ b/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
@@ -89,6 +89,10 @@
#define PMA8084_GPIO_S4 2
#define PMA8084_GPIO_L6 3
+#define PM8994_GPIO_VPH 0
+#define PM8994_GPIO_S4 2
+#define PM8994_GPIO_L12 3
+
/* To be used with "function" */
#define PMIC_GPIO_FUNC_NORMAL "normal"
#define PMIC_GPIO_FUNC_PAIRED "paired"
diff --git a/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
index a15c1704d0..2e360d8f78 100644
--- a/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
+++ b/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
@@ -65,6 +65,12 @@
#define PMA8084_MPP_S4 2
#define PMA8084_MPP_L6 3
+#define PM8994_MPP_VPH 0
+/* Only supported for MPP_05-MPP_08 */
+#define PM8994_MPP_L19 1
+#define PM8994_MPP_S4 2
+#define PM8994_MPP_L12 3
+
/*
* Analog Input - Set the source for analog input.
* To be used with "qcom,amux-route" property
diff --git a/dts/include/dt-bindings/pinctrl/rockchip.h b/dts/include/dt-bindings/pinctrl/rockchip.h
index 743e66a95e..aaec8baaa3 100644
--- a/dts/include/dt-bindings/pinctrl/rockchip.h
+++ b/dts/include/dt-bindings/pinctrl/rockchip.h
@@ -25,6 +25,39 @@
#define RK_GPIO4 4
#define RK_GPIO6 6
+#define RK_PA0 0
+#define RK_PA1 1
+#define RK_PA2 2
+#define RK_PA3 3
+#define RK_PA4 4
+#define RK_PA5 5
+#define RK_PA6 6
+#define RK_PA7 7
+#define RK_PB0 8
+#define RK_PB1 9
+#define RK_PB2 10
+#define RK_PB3 11
+#define RK_PB4 12
+#define RK_PB5 13
+#define RK_PB6 14
+#define RK_PB7 15
+#define RK_PC0 16
+#define RK_PC1 17
+#define RK_PC2 18
+#define RK_PC3 19
+#define RK_PC4 20
+#define RK_PC5 21
+#define RK_PC6 22
+#define RK_PC7 23
+#define RK_PD0 24
+#define RK_PD1 25
+#define RK_PD2 26
+#define RK_PD3 27
+#define RK_PD4 28
+#define RK_PD5 29
+#define RK_PD6 30
+#define RK_PD7 31
+
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2
diff --git a/dts/include/dt-bindings/power/mt2701-power.h b/dts/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 0000000000..64cc826d64
--- /dev/null
+++ b/dts/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN 0
+#define MT2701_POWER_DOMAIN_DISP 1
+#define MT2701_POWER_DOMAIN_MFG 2
+#define MT2701_POWER_DOMAIN_VDEC 3
+#define MT2701_POWER_DOMAIN_ISP 4
+#define MT2701_POWER_DOMAIN_BDP 5
+#define MT2701_POWER_DOMAIN_ETH 6
+#define MT2701_POWER_DOMAIN_HIF 7
+#define MT2701_POWER_DOMAIN_IFR_MSC 8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
diff --git a/dts/include/dt-bindings/power/r8a7743-sysc.h b/dts/include/dt-bindings/power/r8a7743-sysc.h
new file mode 100644
index 0000000000..61cfbb2907
--- /dev/null
+++ b/dts/include/dt-bindings/power/r8a7743-sysc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7743_PD_CA15_CPU0 0
+#define R8A7743_PD_CA15_CPU1 1
+#define R8A7743_PD_CA15_SCU 12
+#define R8A7743_PD_SGX 20
+
+/* Always-on power area */
+#define R8A7743_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */
diff --git a/dts/include/dt-bindings/power/r8a7745-sysc.h b/dts/include/dt-bindings/power/r8a7745-sysc.h
new file mode 100644
index 0000000000..1844c1171c
--- /dev/null
+++ b/dts/include/dt-bindings/power/r8a7745-sysc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7745_PD_CA7_CPU0 5
+#define R8A7745_PD_CA7_CPU1 6
+#define R8A7745_PD_SGX 20
+#define R8A7745_PD_CA7_SCU 21
+
+/* Always-on power area */
+#define R8A7745_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */
diff --git a/dts/include/dt-bindings/power/tegra186-powergate.h b/dts/include/dt-bindings/power/tegra186-powergate.h
new file mode 100644
index 0000000000..388d6e228d
--- /dev/null
+++ b/dts/include/dt-bindings/power/tegra186-powergate.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
+#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
+
+#define TEGRA186_POWER_DOMAIN_AUD 0
+#define TEGRA186_POWER_DOMAIN_DFD 1
+#define TEGRA186_POWER_DOMAIN_DISP 2
+#define TEGRA186_POWER_DOMAIN_DISPB 3
+#define TEGRA186_POWER_DOMAIN_DISPC 4
+#define TEGRA186_POWER_DOMAIN_ISPA 5
+#define TEGRA186_POWER_DOMAIN_NVDEC 6
+#define TEGRA186_POWER_DOMAIN_NVJPG 7
+#define TEGRA186_POWER_DOMAIN_MPE 8
+#define TEGRA186_POWER_DOMAIN_PCX 9
+#define TEGRA186_POWER_DOMAIN_SAX 10
+#define TEGRA186_POWER_DOMAIN_VE 11
+#define TEGRA186_POWER_DOMAIN_VIC 12
+#define TEGRA186_POWER_DOMAIN_XUSBA 13
+#define TEGRA186_POWER_DOMAIN_XUSBB 14
+#define TEGRA186_POWER_DOMAIN_XUSBC 15
+#define TEGRA186_POWER_DOMAIN_GPU 43
+#define TEGRA186_POWER_DOMAIN_MAX 44
+
+#endif
diff --git a/dts/include/dt-bindings/reset/oxsemi,ox810se.h b/dts/include/dt-bindings/reset/oxsemi,ox810se.h
new file mode 100644
index 0000000000..960c26e450
--- /dev/null
+++ b/dts/include/dt-bindings/reset/oxsemi,ox810se.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_RESET_OXSEMI_OX810SE_H
+#define DT_RESET_OXSEMI_OX810SE_H
+
+#define RESET_ARM 0
+#define RESET_COPRO 1
+/* Reserved 2 */
+/* Reserved 3 */
+#define RESET_USBHS 4
+#define RESET_USBHSPHY 5
+#define RESET_MAC 6
+#define RESET_PCI 7
+#define RESET_DMA 8
+#define RESET_DPE 9
+#define RESET_DDR 10
+#define RESET_SATA 11
+#define RESET_SATA_LINK 12
+#define RESET_SATA_PHY 13
+ /* Reserved 14 */
+#define RESET_NAND 15
+#define RESET_GPIO 16
+#define RESET_UART1 17
+#define RESET_UART2 18
+#define RESET_MISC 19
+#define RESET_I2S 20
+#define RESET_AHB_MON 21
+#define RESET_UART3 22
+#define RESET_UART4 23
+#define RESET_SGDMA 24
+/* Reserved 25 */
+/* Reserved 26 */
+/* Reserved 27 */
+/* Reserved 28 */
+/* Reserved 29 */
+/* Reserved 30 */
+#define RESET_BUS 31
+
+#endif /* DT_RESET_OXSEMI_OX810SE_H */
diff --git a/dts/include/dt-bindings/reset/oxsemi,ox820.h b/dts/include/dt-bindings/reset/oxsemi,ox820.h
new file mode 100644
index 0000000000..cc6797bf01
--- /dev/null
+++ b/dts/include/dt-bindings/reset/oxsemi,ox820.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_RESET_OXSEMI_OX820_H
+#define DT_RESET_OXSEMI_OX820_H
+
+#define RESET_SCU 0
+#define RESET_LEON 1
+#define RESET_ARM0 2
+#define RESET_ARM1 3
+#define RESET_USBHS 4
+#define RESET_USBPHYA 5
+#define RESET_MAC 6
+#define RESET_PCIEA 7
+#define RESET_SGDMA 8
+#define RESET_CIPHER 9
+#define RESET_DDR 10
+#define RESET_SATA 11
+#define RESET_SATA_LINK 12
+#define RESET_SATA_PHY 13
+#define RESET_PCIEPHY 14
+#define RESET_NAND 15
+#define RESET_GPIO 16
+#define RESET_UART1 17
+#define RESET_UART2 18
+#define RESET_MISC 19
+#define RESET_I2S 20
+#define RESET_SD 21
+#define RESET_MAC_2 22
+#define RESET_PCIEB 23
+#define RESET_VIDEO 24
+#define RESET_DDR_PHY 25
+#define RESET_USBPHYB 26
+#define RESET_USBDEV 27
+/* Reserved 29 */
+#define RESET_ARMDBG 29
+#define RESET_PLLA 30
+#define RESET_PLLB 31
+
+#endif /* DT_RESET_OXSEMI_OX820_H */
diff --git a/dts/include/dt-bindings/reset/sun50i-a64-ccu.h b/dts/include/dt-bindings/reset/sun50i-a64-ccu.h
new file mode 100644
index 0000000000..db60b29ddb
--- /dev/null
+++ b/dts/include/dt-bindings/reset/sun50i-a64-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_HSIC 2
+#define RST_DRAM 3
+#define RST_MBUS 4
+#define RST_BUS_MIPI_DSI 5
+#define RST_BUS_CE 6
+#define RST_BUS_DMA 7
+#define RST_BUS_MMC0 8
+#define RST_BUS_MMC1 9
+#define RST_BUS_MMC2 10
+#define RST_BUS_NAND 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_EMAC 13
+#define RST_BUS_TS 14
+#define RST_BUS_HSTIMER 15
+#define RST_BUS_SPI0 16
+#define RST_BUS_SPI1 17
+#define RST_BUS_OTG 18
+#define RST_BUS_EHCI0 19
+#define RST_BUS_EHCI1 20
+#define RST_BUS_OHCI0 21
+#define RST_BUS_OHCI1 22
+#define RST_BUS_VE 23
+#define RST_BUS_TCON0 24
+#define RST_BUS_TCON1 25
+#define RST_BUS_DEINTERLACE 26
+#define RST_BUS_CSI 27
+#define RST_BUS_HDMI0 28
+#define RST_BUS_HDMI1 29
+#define RST_BUS_DE 30
+#define RST_BUS_GPU 31
+#define RST_BUS_MSGBOX 32
+#define RST_BUS_SPINLOCK 33
+#define RST_BUS_DBG 34
+#define RST_BUS_LVDS 35
+#define RST_BUS_CODEC 36
+#define RST_BUS_SPDIF 37
+#define RST_BUS_THS 38
+#define RST_BUS_I2S0 39
+#define RST_BUS_I2S1 40
+#define RST_BUS_I2S2 41
+#define RST_BUS_I2C0 42
+#define RST_BUS_I2C1 43
+#define RST_BUS_I2C2 44
+#define RST_BUS_SCR 45
+#define RST_BUS_UART0 46
+#define RST_BUS_UART1 47
+#define RST_BUS_UART2 48
+#define RST_BUS_UART3 49
+#define RST_BUS_UART4 50
+
+#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
diff --git a/dts/include/dt-bindings/reset/tegra186-reset.h b/dts/include/dt-bindings/reset/tegra186-reset.h
new file mode 100644
index 0000000000..8a184e3579
--- /dev/null
+++ b/dts/include/dt-bindings/reset/tegra186-reset.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ABI_MACH_T186_RESET_T186_H_
+#define _ABI_MACH_T186_RESET_T186_H_
+
+
+#define TEGRA186_RESET_ACTMON 0
+#define TEGRA186_RESET_AFI 1
+#define TEGRA186_RESET_CEC 2
+#define TEGRA186_RESET_CSITE 3
+#define TEGRA186_RESET_DP2 4
+#define TEGRA186_RESET_DPAUX 5
+#define TEGRA186_RESET_DSI 6
+#define TEGRA186_RESET_DSIB 7
+#define TEGRA186_RESET_DTV 8
+#define TEGRA186_RESET_DVFS 9
+#define TEGRA186_RESET_ENTROPY 10
+#define TEGRA186_RESET_EXTPERIPH1 11
+#define TEGRA186_RESET_EXTPERIPH2 12
+#define TEGRA186_RESET_EXTPERIPH3 13
+#define TEGRA186_RESET_GPU 14
+#define TEGRA186_RESET_HDA 15
+#define TEGRA186_RESET_HDA2CODEC_2X 16
+#define TEGRA186_RESET_HDA2HDMICODEC 17
+#define TEGRA186_RESET_HOST1X 18
+#define TEGRA186_RESET_I2C1 19
+#define TEGRA186_RESET_I2C2 20
+#define TEGRA186_RESET_I2C3 21
+#define TEGRA186_RESET_I2C4 22
+#define TEGRA186_RESET_I2C5 23
+#define TEGRA186_RESET_I2C6 24
+#define TEGRA186_RESET_ISP 25
+#define TEGRA186_RESET_KFUSE 26
+#define TEGRA186_RESET_LA 27
+#define TEGRA186_RESET_MIPI_CAL 28
+#define TEGRA186_RESET_PCIE 29
+#define TEGRA186_RESET_PCIEXCLK 30
+#define TEGRA186_RESET_SATA 31
+#define TEGRA186_RESET_SATACOLD 32
+#define TEGRA186_RESET_SDMMC1 33
+#define TEGRA186_RESET_SDMMC2 34
+#define TEGRA186_RESET_SDMMC3 35
+#define TEGRA186_RESET_SDMMC4 36
+#define TEGRA186_RESET_SE 37
+#define TEGRA186_RESET_SOC_THERM 38
+#define TEGRA186_RESET_SOR0 39
+#define TEGRA186_RESET_SPI1 40
+#define TEGRA186_RESET_SPI2 41
+#define TEGRA186_RESET_SPI3 42
+#define TEGRA186_RESET_SPI4 43
+#define TEGRA186_RESET_TMR 44
+#define TEGRA186_RESET_TRIG_SYS 45
+#define TEGRA186_RESET_TSEC 46
+#define TEGRA186_RESET_UARTA 47
+#define TEGRA186_RESET_UARTB 48
+#define TEGRA186_RESET_UARTC 49
+#define TEGRA186_RESET_UARTD 50
+#define TEGRA186_RESET_VI 51
+#define TEGRA186_RESET_VIC 52
+#define TEGRA186_RESET_XUSB_DEV 53
+#define TEGRA186_RESET_XUSB_HOST 54
+#define TEGRA186_RESET_XUSB_PADCTL 55
+#define TEGRA186_RESET_XUSB_SS 56
+#define TEGRA186_RESET_AON_APB 57
+#define TEGRA186_RESET_AXI_CBB 58
+#define TEGRA186_RESET_BPMP_APB 59
+#define TEGRA186_RESET_CAN1 60
+#define TEGRA186_RESET_CAN2 61
+#define TEGRA186_RESET_DMIC5 62
+#define TEGRA186_RESET_DSIC 63
+#define TEGRA186_RESET_DSID 64
+#define TEGRA186_RESET_EMC_EMC 65
+#define TEGRA186_RESET_EMC_MEM 66
+#define TEGRA186_RESET_EMCSB_EMC 67
+#define TEGRA186_RESET_EMCSB_MEM 68
+#define TEGRA186_RESET_EQOS 69
+#define TEGRA186_RESET_GPCDMA 70
+#define TEGRA186_RESET_GPIO_CTL0 71
+#define TEGRA186_RESET_GPIO_CTL1 72
+#define TEGRA186_RESET_GPIO_CTL2 73
+#define TEGRA186_RESET_GPIO_CTL3 74
+#define TEGRA186_RESET_GPIO_CTL4 75
+#define TEGRA186_RESET_GPIO_CTL5 76
+#define TEGRA186_RESET_I2C10 77
+#define TEGRA186_RESET_I2C12 78
+#define TEGRA186_RESET_I2C13 79
+#define TEGRA186_RESET_I2C14 80
+#define TEGRA186_RESET_I2C7 81
+#define TEGRA186_RESET_I2C8 82
+#define TEGRA186_RESET_I2C9 83
+#define TEGRA186_RESET_JTAG2AXI 84
+#define TEGRA186_RESET_MPHY_IOBIST 85
+#define TEGRA186_RESET_MPHY_L0_RX 86
+#define TEGRA186_RESET_MPHY_L0_TX 87
+#define TEGRA186_RESET_NVCSI 88
+#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89
+#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90
+#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91
+#define TEGRA186_RESET_NVDISPLAY0_MISC 92
+#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93
+#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94
+#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95
+#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96
+#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97
+#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98
+#define TEGRA186_RESET_PWM1 99
+#define TEGRA186_RESET_PWM2 100
+#define TEGRA186_RESET_PWM3 101
+#define TEGRA186_RESET_PWM4 102
+#define TEGRA186_RESET_PWM5 103
+#define TEGRA186_RESET_PWM6 104
+#define TEGRA186_RESET_PWM7 105
+#define TEGRA186_RESET_PWM8 106
+#define TEGRA186_RESET_SCE_APB 107
+#define TEGRA186_RESET_SOR1 108
+#define TEGRA186_RESET_TACH 109
+#define TEGRA186_RESET_TSC 110
+#define TEGRA186_RESET_UARTF 111
+#define TEGRA186_RESET_UARTG 112
+#define TEGRA186_RESET_UFSHC 113
+#define TEGRA186_RESET_UFSHC_AXI_M 114
+#define TEGRA186_RESET_UPHY 115
+#define TEGRA186_RESET_ADSP 116
+#define TEGRA186_RESET_ADSPDBG 117
+#define TEGRA186_RESET_ADSPINTF 118
+#define TEGRA186_RESET_ADSPNEON 119
+#define TEGRA186_RESET_ADSPPERIPH 120
+#define TEGRA186_RESET_ADSPSCU 121
+#define TEGRA186_RESET_ADSPWDT 122
+#define TEGRA186_RESET_APE 123
+#define TEGRA186_RESET_DPAUX1 124
+#define TEGRA186_RESET_NVDEC 125
+#define TEGRA186_RESET_NVENC 126
+#define TEGRA186_RESET_NVJPG 127
+#define TEGRA186_RESET_PEX_USB_UPHY 128
+#define TEGRA186_RESET_QSPI 129
+#define TEGRA186_RESET_TSECB 130
+#define TEGRA186_RESET_VI_I2C 131
+#define TEGRA186_RESET_UARTE 132
+#define TEGRA186_RESET_TOP_GTE 133
+#define TEGRA186_RESET_SHSP 134
+#define TEGRA186_RESET_PEX_USB_UPHY_L5 135
+#define TEGRA186_RESET_PEX_USB_UPHY_L4 136
+#define TEGRA186_RESET_PEX_USB_UPHY_L3 137
+#define TEGRA186_RESET_PEX_USB_UPHY_L2 138
+#define TEGRA186_RESET_PEX_USB_UPHY_L1 139
+#define TEGRA186_RESET_PEX_USB_UPHY_L0 140
+#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141
+#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142
+#define TEGRA186_RESET_TSCTNVI 143
+#define TEGRA186_RESET_EXTPERIPH4 144
+#define TEGRA186_RESET_DSIPADCTL 145
+#define TEGRA186_RESET_AUD_MCLK 146
+#define TEGRA186_RESET_MPHY_CLK_CTL 147
+#define TEGRA186_RESET_MPHY_L1_RX 148
+#define TEGRA186_RESET_MPHY_L1_TX 149
+#define TEGRA186_RESET_UFSHC_LP 150
+#define TEGRA186_RESET_BPMP_NIC 151
+#define TEGRA186_RESET_BPMP_NSYSPORESET 152
+#define TEGRA186_RESET_BPMP_NRESET 153
+#define TEGRA186_RESET_BPMP_DBGRESETN 154
+#define TEGRA186_RESET_BPMP_PRESETDBGN 155
+#define TEGRA186_RESET_BPMP_PM 156
+#define TEGRA186_RESET_BPMP_CVC 157
+#define TEGRA186_RESET_BPMP_DMA 158
+#define TEGRA186_RESET_BPMP_HSP 159
+#define TEGRA186_RESET_TSCTNBPMP 160
+#define TEGRA186_RESET_BPMP_TKE 161
+#define TEGRA186_RESET_BPMP_GTE 162
+#define TEGRA186_RESET_BPMP_PM_ACTMON 163
+#define TEGRA186_RESET_AON_NIC 164
+#define TEGRA186_RESET_AON_NSYSPORESET 165
+#define TEGRA186_RESET_AON_NRESET 166
+#define TEGRA186_RESET_AON_DBGRESETN 167
+#define TEGRA186_RESET_AON_PRESETDBGN 168
+#define TEGRA186_RESET_AON_ACTMON 169
+#define TEGRA186_RESET_AOPM 170
+#define TEGRA186_RESET_AOVC 171
+#define TEGRA186_RESET_AON_DMA 172
+#define TEGRA186_RESET_AON_GPIO 173
+#define TEGRA186_RESET_AON_HSP 174
+#define TEGRA186_RESET_TSCTNAON 175
+#define TEGRA186_RESET_AON_TKE 176
+#define TEGRA186_RESET_AON_GTE 177
+#define TEGRA186_RESET_SCE_NIC 178
+#define TEGRA186_RESET_SCE_NSYSPORESET 179
+#define TEGRA186_RESET_SCE_NRESET 180
+#define TEGRA186_RESET_SCE_DBGRESETN 181
+#define TEGRA186_RESET_SCE_PRESETDBGN 182
+#define TEGRA186_RESET_SCE_ACTMON 183
+#define TEGRA186_RESET_SCE_PM 184
+#define TEGRA186_RESET_SCE_DMA 185
+#define TEGRA186_RESET_SCE_HSP 186
+#define TEGRA186_RESET_TSCTNSCE 187
+#define TEGRA186_RESET_SCE_TKE 188
+#define TEGRA186_RESET_SCE_GTE 189
+#define TEGRA186_RESET_SCE_CFG 190
+#define TEGRA186_RESET_ADSP_ALL 191
+/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
+#define TEGRA186_RESET_UFSHC_LP_SEQ 192
+#define TEGRA186_RESET_SIZE 193
+
+#endif
diff --git a/dts/include/dt-bindings/sound/cs42l42.h b/dts/include/dt-bindings/sound/cs42l42.h
new file mode 100644
index 0000000000..399a123aed
--- /dev/null
+++ b/dts/include/dt-bindings/sound/cs42l42.h
@@ -0,0 +1,73 @@
+/*
+ * cs42l42.h -- CS42L42 ALSA SoC audio driver DT bindings header
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Author: James Schulman <james.schulman@cirrus.com>
+ * Author: Brian Austin <brian.austin@cirrus.com>
+ * Author: Michael White <michael.white@cirrus.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_CS42L42_H
+#define __DT_CS42L42_H
+
+/* HPOUT Load Capacity */
+#define CS42L42_HPOUT_LOAD_1NF 0
+#define CS42L42_HPOUT_LOAD_10NF 1
+
+/* HPOUT Clamp to GND Overide */
+#define CS42L42_HPOUT_CLAMP_EN 0
+#define CS42L42_HPOUT_CLAMP_DIS 1
+
+/* Tip Sense Inversion */
+#define CS42L42_TS_INV_DIS 0
+#define CS42L42_TS_INV_EN 1
+
+/* Tip Sense Debounce */
+#define CS42L42_TS_DBNCE_0 0
+#define CS42L42_TS_DBNCE_125 1
+#define CS42L42_TS_DBNCE_250 2
+#define CS42L42_TS_DBNCE_500 3
+#define CS42L42_TS_DBNCE_750 4
+#define CS42L42_TS_DBNCE_1000 5
+#define CS42L42_TS_DBNCE_1250 6
+#define CS42L42_TS_DBNCE_1500 7
+
+/* Button Press Software Debounce Times */
+#define CS42L42_BTN_DET_INIT_DBNCE_MIN 0
+#define CS42L42_BTN_DET_INIT_DBNCE_DEFAULT 100
+#define CS42L42_BTN_DET_INIT_DBNCE_MAX 200
+
+#define CS42L42_BTN_DET_EVENT_DBNCE_MIN 0
+#define CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT 10
+#define CS42L42_BTN_DET_EVENT_DBNCE_MAX 20
+
+/* Button Detect Level Sensitivities */
+#define CS42L42_NUM_BIASES 4
+
+#define CS42L42_HS_DET_LEVEL_15 0x0F
+#define CS42L42_HS_DET_LEVEL_8 0x08
+#define CS42L42_HS_DET_LEVEL_4 0x04
+#define CS42L42_HS_DET_LEVEL_1 0x01
+
+#define CS42L42_HS_DET_LEVEL_MIN 0
+#define CS42L42_HS_DET_LEVEL_MAX 0x3F
+
+/* HS Bias Ramp Rate */
+
+#define CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL 0
+#define CS42L42_HSBIAS_RAMP_FAST 1
+#define CS42L42_HSBIAS_RAMP_SLOW 2
+#define CS42L42_HSBIAS_RAMP_SLOWEST 3
+
+#define CS42L42_HSBIAS_RAMP_TIME0 10
+#define CS42L42_HSBIAS_RAMP_TIME1 40
+#define CS42L42_HSBIAS_RAMP_TIME2 90
+#define CS42L42_HSBIAS_RAMP_TIME3 170
+
+#endif /* __DT_CS42L42_H */