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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-07-17 16:18:11 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-07-17 16:18:11 +0200 |
| commit | 48d44d036058b7882b91024cae63c750a9c63c6f (patch) | |
| tree | c758773aa09de2ed660dfae5312b5a97a374f1ac /dts/include | |
| parent | f1d1cdd029e0fbcce38d1e9bdc309e57095a56fb (diff) | |
| download | barebox-48d44d036058b7882b91024cae63c750a9c63c6f.tar.gz barebox-48d44d036058b7882b91024cae63c750a9c63c6f.tar.xz | |
dts: update to v3.16-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/include')
| -rw-r--r-- | dts/include/dt-bindings/clock/exynos5420.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/dts/include/dt-bindings/clock/exynos5420.h b/dts/include/dt-bindings/clock/exynos5420.h index 97dcb89d37..21d51ae1d2 100644 --- a/dts/include/dt-bindings/clock/exynos5420.h +++ b/dts/include/dt-bindings/clock/exynos5420.h @@ -63,7 +63,6 @@ #define CLK_SCLK_MPHY_IXTAL24 161 /* gate clocks */ -#define CLK_ACLK66_PERIC 256 #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 @@ -203,6 +202,8 @@ #define CLK_MOUT_G3D 641 #define CLK_MOUT_VPLL 642 #define CLK_MOUT_MAUDIO0 643 +#define CLK_MOUT_USER_ACLK333 644 +#define CLK_MOUT_SW_ACLK333 645 /* divider clocks */ #define CLK_DOUT_PIXEL 768 |