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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-05 14:51:53 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-08 10:16:55 +0200 |
| commit | 6cec968f559cc22939dbe90ebbde245a7e8a85f4 (patch) | |
| tree | 28fbfdca50bc950506741206a8fd36805a78abea /dts/src/arc/hsdk.dts | |
| parent | 1dc748b3b202cadf9b799874d9af8d441ee556bc (diff) | |
| download | barebox-6cec968f559cc22939dbe90ebbde245a7e8a85f4.tar.gz barebox-6cec968f559cc22939dbe90ebbde245a7e8a85f4.tar.xz | |
dts: update to v5.1-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arc/hsdk.dts')
| -rw-r--r-- | dts/src/arc/hsdk.dts | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts index 43f17b51ee..69bc1c9e8e 100644 --- a/dts/src/arc/hsdk.dts +++ b/dts/src/arc/hsdk.dts @@ -110,12 +110,12 @@ cgu_rst: reset-controller@8a0 { compatible = "snps,hsdk-reset"; #reset-cells = <1>; - reg = <0x8A0 0x4>, <0xFF0 0x4>; + reg = <0x8a0 0x4>, <0xff0 0x4>; }; core_clk: core-clk@0 { compatible = "snps,hsdk-core-pll-clock"; - reg = <0x00 0x10>, <0x14B8 0x4>; + reg = <0x00 0x10>, <0x14b8 0x4>; #clock-cells = <0>; clocks = <&input_clk>; @@ -167,6 +167,18 @@ #clock-cells = <0>; }; + dmac_core_clk: dmac-core-clk { + compatible = "fixed-clock"; + clock-frequency = <400000000>; + #clock-cells = <0>; + }; + + dmac_cfg_clk: dmac-gpu-cfg-clk { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; + gmac: ethernet@8000 { #interrupt-cells = <1>; compatible = "snps,dwmac"; @@ -200,6 +212,7 @@ compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; reg = <0x60000 0x100>; interrupts = <15>; + resets = <&cgu_rst HSDK_USB_RESET>; dma-coherent; }; @@ -207,6 +220,7 @@ compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; reg = <0x40000 0x100>; interrupts = <15>; + resets = <&cgu_rst HSDK_USB_RESET>; dma-coherent; }; @@ -237,6 +251,21 @@ reg = <0>; }; }; + + dmac: dmac@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + interrupts = <27>; + clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; + clock-names = "core-clk", "cfgr-clk"; + + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; }; memory@80000000 { |