summaryrefslogtreecommitdiffstats
path: root/dts/src/arc/hsdk.dts
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2017-10-16 11:28:54 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-10-16 11:28:54 +0200
commitbee7083638439457f600252a8cea2c5e4165f5cd (patch)
tree1d10b86a19d4b3d7a4420d9d160e2f86eb45791b /dts/src/arc/hsdk.dts
parentb2655c3cd112729e9f8bdda47044908472fce480 (diff)
downloadbarebox-bee7083638439457f600252a8cea2c5e4165f5cd.tar.gz
barebox-bee7083638439457f600252a8cea2c5e4165f5cd.tar.xz
dts: update to v4.14-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arc/hsdk.dts')
-rw-r--r--dts/src/arc/hsdk.dts32
1 files changed, 29 insertions, 3 deletions
diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts
index 229d13adbc..8adde1b492 100644
--- a/dts/src/arc/hsdk.dts
+++ b/dts/src/arc/hsdk.dts
@@ -12,6 +12,7 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/reset/snps,hsdk-reset.h>
/ {
model = "snps,hsdk";
@@ -57,10 +58,10 @@
};
};
- core_clk: core-clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <500000000>;
+ clock-frequency = <33333333>;
};
cpu_intc: cpu-interrupt-controller {
@@ -102,6 +103,19 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ cgu_rst: reset-controller@8a0 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0x8A0 0x4>, <0xFF0 0x4>;
+ };
+
+ core_clk: core-clk@0 {
+ compatible = "snps,hsdk-core-pll-clock";
+ reg = <0x00 0x10>, <0x14B8 0x4>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
+ };
+
serial: serial@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
@@ -120,7 +134,17 @@
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
- clock-frequency = <100000000>;
+ /*
+ * DW sdio controller has external ciu clock divider
+ * controlled via register in SDIO IP. Due to its
+ * unexpected default value (it should devide by 1
+ * but it devides by 8) SDIO IP uses wrong clock and
+ * works unstable (see STAR 9001204800)
+ * So add temporary fix and change clock frequency
+ * from 100000000 to 12500000 Hz until we fix dw sdio
+ * driver itself.
+ */
+ clock-frequency = <12500000>;
#clock-cells = <0>;
};
@@ -141,6 +165,8 @@
clocks = <&gmacclk>;
clock-names = "stmmaceth";
phy-handle = <&phy0>;
+ resets = <&cgu_rst HSDK_ETH_RESET>;
+ reset-names = "stmmaceth";
mdio {
#address-cells = <1>;