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author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-07-27 07:08:56 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-07-27 11:31:04 +0200 |
commit | 1f2570eb41c8ebc983e97ff0608d77260c2ba16b (patch) | |
tree | 0ef7f7cfc9a20897cf99497facdeedb6fcfb3a61 /dts/src/arm/armada-xp-mv78230.dtsi | |
parent | 73ead6c5b1ee1ca8c7c83cec1864624b220a0c06 (diff) | |
download | barebox-1f2570eb41c8ebc983e97ff0608d77260c2ba16b.tar.gz barebox-1f2570eb41c8ebc983e97ff0608d77260c2ba16b.tar.xz |
dts: update to v6.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/armada-xp-mv78230.dtsi')
-rw-r--r-- | dts/src/arm/armada-xp-mv78230.dtsi | 257 |
1 files changed, 0 insertions, 257 deletions
diff --git a/dts/src/arm/armada-xp-mv78230.dtsi b/dts/src/arm/armada-xp-mv78230.dtsi deleted file mode 100644 index 5ea9d509cd..0000000000 --- a/dts/src/arm/armada-xp-mv78230.dtsi +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * Contains definitions specific to the Armada XP MV78230 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78230 SoC"; - compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78230 has 2 PCIe units Gen2.0: One unit can be - * configured as x4 or quad x1 lanes. One unit is - * x1 only. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 58>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 59>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 60>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 61>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie4_intc 0>, - <0 0 0 2 &pcie4_intc 1>, - <0 0 0 3 &pcie4_intc 2>, - <0 0 0 4 &pcie4_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie4_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 62>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie5_intc 0>, - <0 0 0 2 &pcie5_intc 1>, - <0 0 0 3 &pcie5_intc 2>, - <0 0 0 4 &pcie5_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - - pcie5_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <17>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>; - clocks = <&coreclk 0>; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78230-pinctrl"; -}; |