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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
| commit | 6940ba22c66ac1c713500027bf5f6832442a1410 (patch) | |
| tree | a460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/src/arm/exynos4412.dtsi | |
| parent | e66a790177410d7433e6672d97bb0b54455ba669 (diff) | |
| download | barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.gz barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.xz | |
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/exynos4412.dtsi')
| -rw-r--r-- | dts/src/arm/exynos4412.dtsi | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/dts/src/arm/exynos4412.dtsi b/dts/src/arm/exynos4412.dtsi index e5c041ec07..d20db2dfe8 100644 --- a/dts/src/arm/exynos4412.dtsi +++ b/dts/src/arm/exynos4412.dtsi @@ -716,6 +716,53 @@ cpu-offset = <0x4000>; }; +&gpu { + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <875000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <900000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <950000>; + }; + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-microvolt = <1025000>; + }; + }; +}; + &hdmi { compatible = "samsung,exynos4212-hdmi"; }; @@ -737,6 +784,8 @@ &pmu { interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; }; &pmu_system_controller { |