diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-07-17 16:18:11 +0200 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-07-17 16:18:11 +0200 |
commit | 48d44d036058b7882b91024cae63c750a9c63c6f (patch) | |
tree | c758773aa09de2ed660dfae5312b5a97a374f1ac /dts/src/arm/exynos5420.dtsi | |
parent | f1d1cdd029e0fbcce38d1e9bdc309e57095a56fb (diff) | |
download | barebox-48d44d036058b7882b91024cae63c750a9c63c6f.tar.gz barebox-48d44d036058b7882b91024cae63c750a9c63c6f.tar.xz |
dts: update to v3.16-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/exynos5420.dtsi')
-rw-r--r-- | dts/src/arm/exynos5420.dtsi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi index e38532271e..15957227ff 100644 --- a/dts/src/arm/exynos5420.dtsi +++ b/dts/src/arm/exynos5420.dtsi @@ -167,7 +167,7 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; @@ -260,6 +260,9 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, + <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "pclk0", "clk0"; }; disp_pd: power-domain@100440C0 { |