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authorSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
commit574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (patch)
tree3fbe9ed379bc0d6c536860845e85a4ede4b36bbc /dts/src/arm/exynos5420.dtsi
parent179dedbc6d85d7ea7c8013513b364a75f32943e8 (diff)
downloadbarebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.gz
dts: update to v5.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/exynos5420.dtsi')
-rw-r--r--dts/src/arm/exynos5420.dtsi90
1 files changed, 82 insertions, 8 deletions
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index 7d51e0f..d39907a 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -175,7 +175,7 @@
};
clock: clock-controller@10010000 {
- compatible = "samsung,exynos5420-clock";
+ compatible = "samsung,exynos5420-clock", "syscon";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
@@ -237,6 +237,32 @@
status = "disabled";
};
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ samsung,syscon-clk = <&clock>;
+ status = "disabled";
+ };
+
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
@@ -273,6 +299,54 @@
status = "disabled";
};
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ ppmu_dmc0_1: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@10d60000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@10d70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
@@ -434,9 +508,9 @@
i2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
- dmas = <&adma 0
- &adma 2
- &adma 1>;
+ dmas = <&adma 0>,
+ <&adma 2>,
+ <&adma 1>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@@ -455,8 +529,8 @@
i2s1: i2s@12d60000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D60000 0x100>;
- dmas = <&pdma1 12
- &pdma1 11>;
+ dmas = <&pdma1 12>,
+ <&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
clock-names = "iis", "i2s_opclk0";
@@ -471,8 +545,8 @@
i2s2: i2s@12d70000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D70000 0x100>;
- dmas = <&pdma0 12
- &pdma0 11>;
+ dmas = <&pdma0 12>,
+ <&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
clock-names = "iis", "i2s_opclk0";