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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 08:26:30 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 17:23:13 +0200 |
| commit | 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch) | |
| tree | dd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/src/arm/imx6dl.dtsi | |
| parent | 625eea2765d94aee016cf25d9cabecde8eae0775 (diff) | |
| download | barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.xz | |
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/imx6dl.dtsi')
| -rw-r--r-- | dts/src/arm/imx6dl.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi index b384913c34..f0607eb41d 100644 --- a/dts/src/arm/imx6dl.dtsi +++ b/dts/src/arm/imx6dl.dtsi @@ -33,6 +33,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, @@ -50,6 +51,29 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; |