summaryrefslogtreecommitdiffstats
path: root/dts/src/arm/imx6ull-pinfunc-snvs.h
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2018-05-08 08:14:56 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-05-08 08:14:56 +0200
commit6b85c20d46812bdbc062b863261c3e5100e30556 (patch)
treee067c9889eaf55d5e793b05a14000276f2669e9f /dts/src/arm/imx6ull-pinfunc-snvs.h
parent9d8c00bdf7c1e8b614a797f0a15fa45bf6387224 (diff)
downloadbarebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.gz
barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.xz
dts: update to v4.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/imx6ull-pinfunc-snvs.h')
-rw-r--r--dts/src/arm/imx6ull-pinfunc-snvs.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/dts/src/arm/imx6ull-pinfunc-snvs.h b/dts/src/arm/imx6ull-pinfunc-snvs.h
new file mode 100644
index 0000000000..f6fb6783c1
--- /dev/null
+++ b/dts/src/arm/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */