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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-08-09 21:17:51 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-08-09 21:17:51 +0200 |
| commit | 6187b17da4b277417f34fe0b0b90bbaddcbc599e (patch) | |
| tree | 51cbbaa0fa325c592d084eb7d197a5df0e7a43bb /dts/src/arm/r8a7742.dtsi | |
| parent | c53e1fc545e686e1f48c8efb9057fc72e158f183 (diff) | |
| download | barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.gz barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.xz | |
dts: update to v5.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/r8a7742.dtsi')
| -rw-r--r-- | dts/src/arm/r8a7742.dtsi | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/dts/src/arm/r8a7742.dtsi b/dts/src/arm/r8a7742.dtsi index dd1b976d2a..a2279686ff 100644 --- a/dts/src/arm/r8a7742.dtsi +++ b/dts/src/arm/r8a7742.dtsi @@ -47,7 +47,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -56,6 +55,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -77,6 +77,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -98,6 +99,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -119,6 +121,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -750,6 +753,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; |