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author | Sascha Hauer <s.hauer@pengutronix.de> | 2024-03-26 11:20:49 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2024-03-26 11:20:49 +0100 |
commit | 8622bc3184ea06f0f77185d5e4f77ae5deeb0a82 (patch) | |
tree | cf9e37e07dc7922a8b23530e3c3c447ff7170d41 /dts/src/arm/renesas/r8a7778.dtsi | |
parent | 8bf6a31b5e8e42da3d2b3e9200887f273ab53d94 (diff) | |
parent | 8dde7a4f17a1245a9aaf07372a7256dc4d09d1fa (diff) | |
download | barebox-8622bc3184ea06f0f77185d5e4f77ae5deeb0a82.tar.gz barebox-8622bc3184ea06f0f77185d5e4f77ae5deeb0a82.tar.xz |
Merge branch 'for-next/dts' into next
Diffstat (limited to 'dts/src/arm/renesas/r8a7778.dtsi')
-rw-r--r-- | dts/src/arm/renesas/r8a7778.dtsi | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/dts/src/arm/renesas/r8a7778.dtsi b/dts/src/arm/renesas/r8a7778.dtsi index 8d4530ed2f..b80e832c92 100644 --- a/dts/src/arm/renesas/r8a7778.dtsi +++ b/dts/src/arm/renesas/r8a7778.dtsi @@ -199,7 +199,9 @@ reg = <0xffd80000 0x30>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -214,7 +216,9 @@ reg = <0xffd81000 0x30>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -230,6 +234,7 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -250,6 +255,8 @@ reg = <0xffd90000 0x1000>, /* SRU */ <0xffd91000 0x240>, /* SSI */ <0xfffe0000 0x24>; /* ADG */ + reg-names = "sru", "ssi", "adg"; + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, <&mstp3_clks R8A7778_CLK_SSI7>, <&mstp3_clks R8A7778_CLK_SSI6>, |