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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-14 09:09:57 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-14 09:09:57 +0100 |
commit | 33fdc89d4cbd74aa54c28dc61d62972ab164e64d (patch) | |
tree | da5ceff551dc1fdf2f2cc40e97a08035f9ef84fb /dts/src/arm/rk3066a.dtsi | |
parent | 13a52906ce67ed2ce67bfc10714934ffa6c5d646 (diff) | |
download | barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.gz barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.xz |
dts: update to v5.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/rk3066a.dtsi')
-rw-r--r-- | dts/src/arm/rk3066a.dtsi | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/dts/src/arm/rk3066a.dtsi b/dts/src/arm/rk3066a.dtsi index 2ab3c4b320..30dc8af0bd 100644 --- a/dts/src/arm/rk3066a.dtsi +++ b/dts/src/arm/rk3066a.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3066a-cru.h> +#include <dt-bindings/power/rk3066-power.h> #include "rk3xxx.dtsi" / { @@ -70,6 +71,7 @@ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <8>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -87,6 +89,7 @@ clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -104,6 +107,7 @@ clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -595,6 +599,7 @@ "ppmmu2", "pp3", "ppmmu3"; + power-domains = <&power RK3066_PD_GPU>; }; &i2c0 { @@ -643,6 +648,56 @@ dma-names = "rx-tx"; }; +&pmu { + power: power-controller { + compatible = "rockchip,rk3066-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vio@RK3066_PD_VIO { + reg = <RK3066_PD_VIO>; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF1>, + <&cru ACLK_CIF1>, + <&cru HCLK_CIF1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_cif1>, + <&qos_ipp>, + <&qos_rga>; + }; + + pd_video@RK3066_PD_VIDEO { + reg = <RK3066_PD_VIDEO>; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + }; + + pd_gpu@RK3066_PD_GPU { + reg = <RK3066_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + }; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pwm0_out>; |