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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-05 14:51:50 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-08 10:16:55 +0200 |
| commit | 1dc748b3b202cadf9b799874d9af8d441ee556bc (patch) | |
| tree | 58fd3c90a40e2d0128b0c7f36d63d7fc126bb20d /dts/src/arm/rk3288-veyron.dtsi | |
| parent | 9688b49cd3bc0b61a019e8e1311236c9975a0777 (diff) | |
| download | barebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.gz barebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.xz | |
dts: update to v5.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/rk3288-veyron.dtsi')
| -rw-r--r-- | dts/src/arm/rk3288-veyron.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/dts/src/arm/rk3288-veyron.dtsi b/dts/src/arm/rk3288-veyron.dtsi index d8bf939a3a..0bc2409f69 100644 --- a/dts/src/arm/rk3288-veyron.dtsi +++ b/dts/src/arm/rk3288-veyron.dtsi @@ -10,6 +10,10 @@ #include "rk3288.dtsi" / { + chosen { + stdout-path = "serial2:115200n8"; + }; + /* * The default coreboot on veyron devices ignores memory@0 nodes * and would instead create another memory node. |