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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-09 14:49:17 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-17 09:37:13 +0100 |
commit | f826d85b7ab0924d5bf1a5458c49e7f7d8207a23 (patch) | |
tree | dd6354e00da0aa143d1db6164e1a455dddb9b892 /dts/src/arm/rk3288.dtsi | |
parent | 0e37f94fbe1bd189f35b3e1718549ec2f4a710ee (diff) | |
download | barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.gz barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.xz |
dts: update to v5.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/rk3288.dtsi')
-rw-r--r-- | dts/src/arm/rk3288.dtsi | 115 |
1 files changed, 54 insertions, 61 deletions
diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi index 68d5a58cfe..ea7416c31f 100644 --- a/dts/src/arm/rk3288.dtsi +++ b/dts/src/arm/rk3288.dtsi @@ -154,50 +154,6 @@ }; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xffb20000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -487,15 +443,27 @@ status = "disabled"; }; + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + thermal-zones { - reserve_thermal: reserve_thermal { + reserve_thermal: reserve-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ thermal-sensors = <&tsadc 0>; }; - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -539,7 +507,7 @@ }; }; - gpu_thermal: gpu_thermal { + gpu_thermal: gpu-thermal { polling-delay-passive = <100>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -665,6 +633,19 @@ status = "disabled"; }; + dmac_bus_ns: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + i2c0: i2c@ff650000 { compatible = "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -1329,75 +1310,87 @@ }; qos_gpu_r: qos@ffaa0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaa0000 0x0 0x20>; }; qos_gpu_w: qos@ffaa0080 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaa0080 0x0 0x20>; }; qos_vio1_vop: qos@ffad0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0000 0x0 0x20>; }; qos_vio1_isp_w0: qos@ffad0100 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0100 0x0 0x20>; }; qos_vio1_isp_w1: qos@ffad0180 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0180 0x0 0x20>; }; qos_vio0_vop: qos@ffad0400 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0400 0x0 0x20>; }; qos_vio0_vip: qos@ffad0480 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0480 0x0 0x20>; }; qos_vio0_iep: qos@ffad0500 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0500 0x0 0x20>; }; qos_vio2_rga_r: qos@ffad0800 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0800 0x0 0x20>; }; qos_vio2_rga_w: qos@ffad0880 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0880 0x0 0x20>; }; qos_vio1_isp_r: qos@ffad0900 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0900 0x0 0x20>; }; qos_video: qos@ffae0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffae0000 0x0 0x20>; }; qos_hevc_r: qos@ffaf0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaf0000 0x0 0x20>; }; qos_hevc_w: qos@ffaf0080 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaf0080 0x0 0x20>; }; + dmac_bus_s: dma-controller@ffb20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xffb20000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + }; + efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0x0 0xffb40000 0x0 0x20>; |