summaryrefslogtreecommitdiffstats
path: root/dts/src/arm/socfpga.dtsi
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2015-07-08 14:44:21 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2015-07-08 14:44:21 +0200
commit87360e3dd42bb627a9f2611f961728c0789e1c21 (patch)
treeafefc88c862d9feafb0cdb075badeb8d32d8efd2 /dts/src/arm/socfpga.dtsi
parent80936d6aaeea1b10ce4eb81c54eece2f55f8e209 (diff)
downloadbarebox-87360e3dd42bb627a9f2611f961728c0789e1c21.tar.gz
barebox-87360e3dd42bb627a9f2611f961728c0789e1c21.tar.xz
dts: update to v4.2-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/socfpga.dtsi')
-rw-r--r--dts/src/arm/socfpga.dtsi20
1 files changed, 19 insertions, 1 deletions
diff --git a/dts/src/arm/socfpga.dtsi b/dts/src/arm/socfpga.dtsi
index d9176e6061..80f924deed 100644
--- a/dts/src/arm/socfpga.dtsi
+++ b/dts/src/arm/socfpga.dtsi
@@ -36,6 +36,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "altr,socfpga-smp";
cpu@0 {
compatible = "arm,cortex-a9";
@@ -451,6 +452,14 @@
clk-phase = <0 135>;
};
+ sdmmc_clk_divided: sdmmc_clk_divided {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&sdmmc_clk>;
+ clk-gate = <0xa0 8>;
+ fixed-divider = <4>;
+ };
+
nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
@@ -488,6 +497,8 @@
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -504,6 +515,8 @@
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -635,7 +648,7 @@
fifo-depth = <0x400>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+ clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
};
@@ -655,6 +668,11 @@
status = "disabled";
};
+ scu: snoop-control-unit@fffec000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffec000 0x100>;
+ };
+
spi1: spi@fff01000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;