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authorSascha Hauer <s.hauer@pengutronix.de>2014-09-01 09:47:17 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2014-09-02 11:01:29 +0200
commita595ff6eea05b919567f96d71e7e2c7b6236b8ac (patch)
tree2d7cea529b6a06be744116e29e8a97b0c8de1981 /dts/src/arm/zynq-parallella.dts
parent7955f4315187665690f51e20698d4c12c68e008f (diff)
downloadbarebox-a595ff6eea05b919567f96d71e7e2c7b6236b8ac.tar.gz
dts: update to v3.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/zynq-parallella.dts')
-rw-r--r--dts/src/arm/zynq-parallella.dts64
1 files changed, 64 insertions, 0 deletions
diff --git a/dts/src/arm/zynq-parallella.dts b/dts/src/arm/zynq-parallella.dts
new file mode 100644
index 0000000..41afd9d
--- /dev/null
+++ b/dts/src/arm/zynq-parallella.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014 SUSE LINUX Products GmbH
+ *
+ * Derived from zynq-zed.dts:
+ *
+ * Copyright (C) 2011 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ * Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Adapteva Parallella Board";
+ compatible = "adapteva,parallella", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
+ linux,stdout-path = "/amba/serial@e0001000";
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet_phy: ethernet-phy@0 {
+ /* Marvell 88E1318 */
+ compatible = "ethernet-phy-id0141.0e90",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
+ <0x3 0x11 0xfff0 0xa>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};