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authorSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
commitebde8820a04dd73a09f50ba84b8cf8ec3773d6ba (patch)
tree031d15dcd26f5b737adddc5042a3ddabbb6051f7 /dts/src/arm64/broadcom/stingray/stingray.dtsi
parent15af9fc8cc9e18409893d2375271d64cac76924a (diff)
downloadbarebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.gz
barebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.xz
dts: update to v4.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/broadcom/stingray/stingray.dtsi')
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray.dtsi136
1 files changed, 136 insertions, 0 deletions
diff --git a/dts/src/arm64/broadcom/stingray/stingray.dtsi b/dts/src/arm64/broadcom/stingray/stingray.dtsi
index 49933cf16c..e6f75c6336 100644
--- a/dts/src/arm64/broadcom/stingray/stingray.dtsi
+++ b/dts/src/arm64/broadcom/stingray/stingray.dtsi
@@ -152,6 +152,12 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
+ ccn: ccn@00000000 {
+ compatible = "arm,ccn-502";
+ reg = <0x00000000 0x900000>;
+ interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@02c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@@ -261,6 +267,9 @@
};
};
+ #include "stingray-fs4.dtsi"
+ #include "stingray-sata.dtsi"
+
hsls {
compatible = "simple-bus";
#address-cells = <1>;
@@ -269,6 +278,37 @@
#include "stingray-pinctrl.dtsi"
+ mdio_mux_iproc: mdio-mux@0002023c {
+ compatible = "brcm,mdio-mux-iproc";
+ reg = <0x0002023c 0x14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* PCIe serdes */
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@2 { /* SATA */
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@3 { /* USB */
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@10 { /* RGMII */
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
pwm: pwm@00010000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
@@ -277,6 +317,93 @@
status = "disabled";
};
+ timer0: timer@00030000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00030000 0x1000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer1: timer@00040000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00040000 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
+
+ timer2: timer@00050000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00050000 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer3: timer@00060000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00060000 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer4: timer@00070000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00070000 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer5: timer@00080000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00080000 0x1000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer6: timer@00090000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00090000 0x1000>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer7: timer@000a0000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x000a0000 0x1000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@000b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
@@ -424,6 +551,15 @@
iommus = <&smmu 0x6000 0x0000>;
};
+ enet: ethernet@00340000{
+ compatible = "brcm,amac";
+ reg = <0x00340000 0x1000>;
+ reg-names = "amac_base";
+ dma-coherent;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ status= "disabled";
+ };
+
nand: nand@00360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,