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authorSascha Hauer <s.hauer@pengutronix.de>2022-08-24 08:46:04 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-08-25 15:39:39 +0200
commiteddd8312948329e28f00a6f1ca52b3e7f3c330ee (patch)
tree1b4ef77f92f72af55f853e09be1789a4206fbcb6 /dts/src/arm64/freescale/imx8mp.dtsi
parenteed776a50f486d4c1951da32a30d3fd1588ac6e2 (diff)
downloadbarebox-eddd8312948329e28f00a6f1ca52b3e7f3c330ee.tar.gz
barebox-eddd8312948329e28f00a6f1ca52b3e7f3c330ee.tar.xz
dts: update to v6.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/freescale/imx8mp.dtsi')
-rw-r--r--dts/src/arm64/freescale/imx8mp.dtsi31
1 files changed, 26 insertions, 5 deletions
diff --git a/dts/src/arm64/freescale/imx8mp.dtsi b/dts/src/arm64/freescale/imx8mp.dtsi
index 410d0d5e6f..fe178b7d06 100644
--- a/dts/src/arm64/freescale/imx8mp.dtsi
+++ b/dts/src/arm64/freescale/imx8mp.dtsi
@@ -195,7 +195,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency= <133000000>;
+ clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -293,7 +293,7 @@
arm,no-tick-in-suspend;
};
- soc@0 {
+ soc: soc@0 {
compatible = "fsl,imx8mp-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -791,6 +791,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
sec_jr1: jr@2000 {
@@ -903,7 +904,7 @@
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -917,7 +918,7 @@
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -931,7 +932,7 @@
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -1018,6 +1019,26 @@
};
};
+ noc: interconnect@32700000 {
+ compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
+ reg = <0x32700000 0x100000>;
+ clocks = <&clk IMX8MP_CLK_NOC>;
+ #interconnect-cells = <1>;
+ operating-points-v2 = <&noc_opp_table>;
+
+ noc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200M {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+
+ opp-1000M {
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+ };
+ };
+
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;